CN205656615U - Treater based on MPC824x provides generic interface - Google Patents

Treater based on MPC824x provides generic interface Download PDF

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CN205656615U
CN205656615U CN201620353747.XU CN201620353747U CN205656615U CN 205656615 U CN205656615 U CN 205656615U CN 201620353747 U CN201620353747 U CN 201620353747U CN 205656615 U CN205656615 U CN 205656615U
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processor
control unit
mpc824x
interface
ethernet
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陈岗
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Guangdong Industry Technical College
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Guangdong Industry Technical College
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Abstract

The utility model discloses a treater based on MPC824x provides generic interface, including central control unit to and the MPC603E microprocessor kernel that links to each other with central control unit respectively, store controller, PCI the control unit, double -H groove weld ART unit, ethernet controller, I2C unit etc. Adopt general fei sikaer MPC603e treater, high processing capacity, and multiple general communication interface is provided, including the PCI interface, the ethernet interface, serial communication interface, I2C bus interface etc, can extensively be used for wireless LAN, router / switch, embedded calculator, multichannel modem, the network storage, an image display system, the IO input -output process of enterprise ware, ethernet visit equipment, RAID system disk controller, copy the printing apparatus controller.

Description

一种基于MPC824x提供通用接口的处理器A Processor Providing General Interface Based on MPC824x

技术领域technical field

本实用新型涉及处理器研究领域,特别涉及一种基于MPC824x提供通用接口的处理器。The utility model relates to the field of processor research, in particular to a processor providing a general interface based on MPC824x.

背景技术Background technique

在各种互联网和数据通信的高端应用中,处理器作为通信以及控制的中心,是不可缺少的一个核心模块。由于处理器模块技术复杂,接口众多,这大大增加了开发的技术难度。In various high-end applications of the Internet and data communication, the processor, as the center of communication and control, is an indispensable core module. Due to the complex technology of the processor module and numerous interfaces, this greatly increases the technical difficulty of development.

采用高性能的处理器通用模块,使开发者从复杂的处理器设计工作中解放出来,只集中关注外围电路的设计以及应用,可以在项目开发过程中减少处理器部分调试所花费时间和可能出现的错误,极大地缩短设计周期、加快上市速度并减少升级的时间和复杂性,从而降低了总拥有成本并提供了杰出的可扩展性。The use of high-performance general-purpose processor modules frees developers from complex processor design work, and only focuses on the design and application of peripheral circuits, which can reduce the time spent on debugging part of the processor and possible occurrences during project development. errors, greatly shortening design cycles, speeding time to market, and reducing the time and complexity of upgrades, resulting in lower total cost of ownership and outstanding scalability.

MPC824X是高速度低价格的第二代PowerPC,具有PCI 2.2接口,是中端设备经典之作,有非常强的嵌入式表现,具有优异的性能、较低的能量损耗以及较低的散热量,在实际工作中得到广泛应用。MPC824X is the second-generation PowerPC with high speed and low price. It has PCI 2.2 interface. It is widely used in practical work.

因此,研制基于MPC824x处理器,并提供各种通用的接口,例如PCI接口、I2C接口、以太网接口、RS485接口等,对于满足各种互联网和数据通信的高端应用以及缩短开发周期等具有重要应用价值。Therefore, the development is based on the MPC824x processor and provides various general interfaces, such as PCI interface, I 2 C interface, Ethernet interface, RS485 interface, etc., which are of great significance for meeting various high-end applications of Internet and data communication and shortening the development cycle. important application value.

实用新型内容Utility model content

本实用新型的目的在于克服现有技术的缺点与不足,提供一种基于MPC824x提供通用接口的处理器,该处理器具有多种接口,处理能力强,应用场合广泛。The purpose of the utility model is to overcome the shortcomings and deficiencies of the prior art, and provide a processor based on MPC824x that provides a general interface. The processor has multiple interfaces, strong processing capability, and wide application occasions.

本实用新型的目的通过以下的技术方案实现:一种基于MPC824x的处理器,包括中央控制单元,以及分别与中央控制单元相连的MPC603E微处理器内核、存储控制器、PCI控制单元和双UART单元。所述中央控制单元是MPC824x处理器芯片内的核心控制部件,通过60X总线与MPC603E微处理器内核、Boot(启动程序器)、Flash、SDRAM(Synchronous Dynamic Random Access Memory,同步动态随机存储器)连接,用于负责对MPC603E微处理器内核和外围所有部件之间的控制以及通信。所述存储控制器通过存储控制线与Flash、SDRAM连接,同时支持双Boot启动。所述双UART单元中其中一UART控制器外接一RS232电平转换芯片,用于提供RS232电平标准的调试串口;另一个UART控制器直接连接到子卡插座,用于母板采用RS485电平进行串行通信。The purpose of this utility model is realized by following technical scheme: a kind of processor based on MPC824x comprises central control unit, and the MPC603E microprocessor kernel that links to each other with central control unit, storage controller, PCI control unit and double UART unit . Described central control unit is the core control unit in the MPC824x processor chip, is connected with MPC603E microprocessor kernel, Boot (startup program device), Flash, SDRAM (Synchronous Dynamic Random Access Memory, synchronous dynamic random access memory) by 60X bus line, It is responsible for the control and communication between the MPC603E microprocessor core and all peripheral components. The storage controller is connected with Flash and SDRAM through a storage control line, and supports dual-boot startup at the same time. One of the UART controllers in the dual UART unit is externally connected to an RS232 level conversion chip, which is used to provide a debugging serial port of the RS232 level standard; for serial communication.

优选的,所述处理器包括以太网控制器,所述以太网控制器与PCI控制单元通过PCI总线相连,外接一以太网电平转换芯片,用于提供10M/100M自适应以太网通信接口。Preferably, the processor includes an Ethernet controller, the Ethernet controller is connected to the PCI control unit through a PCI bus, and is externally connected with an Ethernet level conversion chip for providing a 10M/100M adaptive Ethernet communication interface.

优选的,所述处理器包括I2C单元,所述I2C单元与中央控制单元相连,用于提供I2C标准通信接口。Preferably, the processor includes an I 2 C unit, and the I 2 C unit is connected to the central control unit for providing an I 2 C standard communication interface.

具体的,所述RS232电平转换芯片采用ADM3202ARN。Specifically, the RS232 level conversion chip adopts ADM3202ARN.

具体的,所述以太网电平转换芯片采用PHY器件MS5153。Specifically, the Ethernet level conversion chip adopts a PHY device MS5153.

本实用新型与现有技术相比,具有如下优点和有益效果:Compared with the prior art, the utility model has the following advantages and beneficial effects:

本实用新型采用通用的菲斯卡尔MPC603E微处理器,处理能力强,并提供了多种通用通信接口,包括PCI接口、以太网接口、串行通信接口、I2C总线接口等,可广泛用于无线LAN、路由器/交换机、嵌入式计算器、多通道调制解调器、网络存储、图像显示系统、企业I/O输入输出处理器、以太网访问设备、RAID系统磁盘控制器、复印打印设备控制器。The utility model adopts the universal Fiscal MPC603E microprocessor, which has strong processing ability, and provides various general communication interfaces, including PCI interface, Ethernet interface, serial communication interface, I 2 C bus interface, etc., which can be widely used In wireless LAN, router/switch, embedded calculator, multi-channel modem, network storage, image display system, enterprise I/O input and output processor, Ethernet access device, RAID system disk controller, copying and printing device controller.

附图说明Description of drawings

图1是本实用新型装置的结构原理示意图。Fig. 1 is the structural schematic diagram of the utility model device.

具体实施方式detailed description

下面结合实施例及附图对本实用新型作进一步详细的描述,但本实用新型的实施方式不限于此。The utility model will be further described in detail below in conjunction with the embodiments and accompanying drawings, but the implementation of the utility model is not limited thereto.

实施例1Example 1

如图1所示,本实施例所述处理器,采用菲思卡尔POWERPC系列MPC824x作为主控芯片,该主控芯片集成MPC603E微处理器内核、32位PCI主桥、64位总线SDRAM控制器。具有高性能的处理能力,处理能力达488MIPS@266MHz。同时提供标准的PCI接口,最高支持272MB ROM、2GBSDRAM,支持双Boot启动。MPC603E集成浮点单元、运行/存储单元、系统寄存器单元等功能。As shown in Fig. 1, the processor described in this embodiment adopts Fiscal POWERPC series MPC824x as the main control chip, and the main control chip integrates MPC603E microprocessor core, 32-bit PCI main bridge, and 64-bit bus SDRAM controller. With high-performance processing capability, the processing capability reaches 488MIPS@266MHz. At the same time, it provides a standard PCI interface, supports up to 272MB ROM, 2GB SDRAM, and supports dual Boot. MPC603E integrates functions such as floating point unit, operation/storage unit, and system register unit.

本实施例采用双通道集成DMA控制器,支持直接模式或链接模式,支持PCI与PCI之间、本地与PCI之间,本地与本地之间,每通道64字节传送队列。所述存储控制器通过存储控制线与Flash、SDRAM连接,同时支持双Boot启动。所述处理器中,MPC603E微处理器内核、中央控制单元均分别通过60X总线与Flash、SDRAM相连,同时支持双Boot启动。This embodiment adopts a dual-channel integrated DMA controller, supports direct mode or link mode, supports between PCI and PCI, between local and PCI, and between local and local, and each channel has a 64-byte transmission queue. The storage controller is connected with Flash and SDRAM through a storage control line, and supports dual-boot startup at the same time. In the processor, the MPC603E microprocessor core and the central control unit are respectively connected to the Flash and SDRAM through the 60X bus, and support dual-Boot startup at the same time.

本实施例包括PCI控制单元,用于提供PCI总线接口,接口信号为P_CLK、P_IDSEL、P_IDSEL2、P_INT<3..0>、P_REQ<3..0>、P_GNT<3..0>、REQ2、GNT2、P_FRAME、P_DEVSEL、P_IRDY、P_LOCK、P_PAR、P_TRDY、P_PERR、P_STOP、P_SERR、P_CBE<3..0>、P_AD<31..0>、。兼容PCI2.2规范,32位总线,最大支持66MHZ。支持最多可连接5个PCI设备,通过REQ<4..0>、GNT<4..0>进行请求和许可。支持工作于PCI主模式或PCI从模式,具体实施方法为:This embodiment includes a PCI control unit for providing a PCI bus interface, and the interface signals are P_CLK, P_IDSEL, P_IDSEL2, P_INT<3..0>, P_REQ<3..0>, P_GNT<3..0>, REQ2, GNT2, P_FRAME, P_DEVSEL, P_IRDY, P_LOCK, P_PAR, P_TRDY, P_PERR, P_STOP, P_SERR, P_CBE<3..0>, P_AD<31..0>,. Compatible with PCI2.2 specification, 32-bit bus, maximum support 66MHZ. Support up to 5 PCI devices to be connected, request and permission through REQ<4..0>, GNT<4..0>. Support to work in PCI master mode or PCI slave mode, the specific implementation method is:

(1)当工作于PCI主模式时(PCI_MODE=0),P_REQ<3..0>、P_GNT<3..0>用于外接的PCI设备。P_REQ4\P_GNT4用于模块内部的PCI设备RTL8139。(1) When working in PCI master mode (PCI_MODE=0), P_REQ<3..0>, P_GNT<3..0> are used for external PCI devices. P_REQ4\P_GNT4 is used for PCI device RTL8139 inside the module.

(2)当工作于PCI从模式时(PCI_MODE=1),P_REQ3/P_GNT3用于本MPC824x向主PCI申请总线使用权,REQ2/GNT2用于本模块内以太网控制器RTL8139向主PCI申请总线使用权。(2) When working in PCI slave mode (PCI_MODE=1), P_REQ3/P_GNT3 is used for this MPC824x to apply for bus usage right from the main PCI, and REQ2/GNT2 is used for the Ethernet controller RTL8139 in this module to apply for bus usage from the main PCI right.

本实施例所述处理器还包括一RTL8139以太网控制器,所述RTL8139以太网控制器挂接于PCI总线上,外接PHY器件MS5153以太网电平转换芯片,可提供10M/100M自适应以太网通信接口,接口信号为FE_TX+、FE_TX-、FE_RX+、FE_RX-。The processor described in this embodiment also includes an RTL8139 Ethernet controller, the RTL8139 Ethernet controller is connected to the PCI bus, and the external PHY device MS5153 Ethernet level conversion chip can provide 10M/100M adaptive Ethernet Communication interface, the interface signals are FE_TX+, FE_TX-, FE_RX+, FE_RX-.

本实施例提供兼容于ST16550的双UART单元,该单元包括两个UART控制器。其中一个UART控制器外接PHY器件RS232电平转换芯片ADM3202ARN,提供RS232电平标准的调试接口,用于与电脑串行通信口进行联机调试,接口信号为RS232_TX、RS232_RX。另一个UART控制器直接连接到子卡插座,用于母板采用RS485电平进行串行通信,接口信号为RS485TX、RS485TEN、RS485RX、RS485REN。This embodiment provides a dual UART unit compatible with ST16550, which includes two UART controllers. One of the UART controllers is externally connected to the PHY device RS232 level conversion chip ADM3202ARN, which provides an RS232 level standard debugging interface for online debugging with the computer serial communication port, and the interface signals are RS232_TX and RS232_RX. Another UART controller is directly connected to the daughter card socket for serial communication on the motherboard using RS485 level, and the interface signals are RS485TX, RS485TEN, RS485RX, RS485REN.

本实施例所述处理器还包括一I2C单元,所述I2C单元与中央控制单元相连,用于提供I2C标准通信接口,接口信号为I2C_SCL、I2C_SDA。The processor in this embodiment further includes an I 2 C unit, which is connected to the central control unit and used to provide an I 2 C standard communication interface, and the interface signals are I2C_SCL and I2C_SDA.

本实施例模块对外输出接口信号如表1所示。The external output interface signals of the module in this embodiment are shown in Table 1.

表1 模块对外接口信号定义Table 1 Module external interface signal definition

上述实施例为本实用新型较佳的实施方式,但本实用新型的实施方式并不受上述实施例的限制,其他的任何未背离本实用新型的精神实质与原理下所作的改变、修饰、替代、组合、简化,均应为等效的置换方式,都包含在本实用新型的保护范围之内。The above-mentioned embodiment is a preferred implementation mode of the present utility model, but the implementation mode of the present utility model is not limited by the above-mentioned embodiment, and any other changes, modifications and substitutions made without departing from the spirit and principle of the present utility model , combination, and simplification, all should be equivalent replacement methods, and are all included in the protection scope of the present utility model.

Claims (5)

1. the processor that general-purpose interface is provided based on MPC824x, it is characterised in that include central authorities' control Unit processed, and be connected with central control unit respectively MPC603E micro-processor kernel, storage control, PCI control unit and dual uart unit, in described central control unit is MPC824x processor chips Core control part, by 60X bus and MPC603E micro-processor kernel, Boot, Flash, SDRAM Connect, for being responsible for the control between MPC603E micro-processor kernel and other all parts and leading to Letter;Described storage control is connected with Flash, SDRAM by storage control line, supports double Boot simultaneously Start;The wherein external RS232 electrical level transferring chip of a UART controller in described dual uart unit, For providing the debugging serial ports of RS232 level standard;Another UART controller is directly connected to subcard and inserts Seat, uses RS485 level to carry out serial communication for motherboard.
The processor that general-purpose interface is provided based on MPC824x the most according to claim 1, its feature Being, described processor includes that ethernet controller, described ethernet controller pass through with PCI control unit Pci bus is connected, and an external Ethernet electrical level transferring chip is used for providing 10M/100M self adaptation Ethernet Communication interface.
The processor that general-purpose interface is provided based on MPC824x the most according to claim 1, its feature Being, described processor includes I2C cell, described I2C cell is connected with central control unit, is used for providing I2C standard communication interface.
The processor that general-purpose interface is provided based on MPC824x the most according to claim 1, its feature Being, described RS232 electrical level transferring chip uses ADM3202ARN.
The processor that general-purpose interface is provided based on MPC824x the most according to claim 2, its feature Being, described Ethernet electrical level transferring chip uses PHY device MS5153.
CN201620353747.XU 2016-04-25 2016-04-25 Treater based on MPC824x provides generic interface Expired - Fee Related CN205656615U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107390626A (en) * 2017-08-28 2017-11-24 上海斐讯数据通信技术有限公司 RPDU communication cards and distribution system based on Power PC Processor
CN109257306A (en) * 2018-10-22 2019-01-22 国网江苏省电力有限公司淮安供电分公司 The embedded L3 Switching device of low-power consumption

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107390626A (en) * 2017-08-28 2017-11-24 上海斐讯数据通信技术有限公司 RPDU communication cards and distribution system based on Power PC Processor
CN109257306A (en) * 2018-10-22 2019-01-22 国网江苏省电力有限公司淮安供电分公司 The embedded L3 Switching device of low-power consumption

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