CN205648136U - System energy saver - Google Patents

Abstract

The utility model discloses a system energy saver, include: first relay, second relay, the first inductance and the second inductance of series connection, MCU module to and the power module, acquisition unit, power line carrier module and the drive unit that link to each other with the MCU module respectively, wherein, first inductance is the excessive pressure winding, the second inductance is for falling power windings, power module does the MCU module provides operating voltage, the power line carrier signal that is sent by the centralized control ware is received to the power line carrier module, and will power line carrier signals carries out sending behind the demodulation processing module for MCU, and receive the feedback instruction of MCU module feedback, and will the feedback instruction converts power line carrier signals to to through be coupled to it send on the alternating -current power line for the centralized control ware, the feedback instruction is the operating condition information of current discharge lamp, the utility model has the advantages that: easy operation facilitates the use.

Description

A kind of system power saver

Technical field

This utility model relates to a kind of system power saver.

Background technology

Along with improving constantly of living standard, people are more and more higher to the requirement of city illumination environment, necessary not only for emergency lighting, also add the illumination promoting city image.Relevant department specifies: in the normal illumination period, and the illumination that the standard that should reach specifies need not the normal illumination period (the such as time after midnight), can only retain safe illumination, and its brightness value typically rests in the half of standard.And at present city image illumination is often several times of normal luminance, considerably beyond national standard, in the case of having only to retain safe illumination, waste the substantial amounts of energy.Therefore in the period that need not city image illumination, making illumination drop to safe illumination becomes inevitable to reach energy-conservation purpose.

Utility model content

The purpose of this utility model is to provide a kind of system power saver, and it can solve disadvantages mentioned above of the prior art.

This utility model is by the following technical solutions:

A kind of system power saver, including: the first relay, the second relay, the first inductance of series connection and the second inductance, MCU module, and power module, collecting unit, power line carrier module and the driver element being connected with MCU module respectively；

Wherein, described first inductance is overvoltage winding, and described second inductance is fall power winding；

Described power module provides running voltage for described MCU module；

Described power line carrier module receives the power carrier signal that sent by Centralized Controller, and is sent to MCU module after being demodulated described power carrier signal processing；And receive the feedback command of described MCU module feedback, and described feedback command is converted into power carrier signal, and is sent to described Centralized Controller on AC power cord by coupling it to；Described feedback command is the work state information of present discharge lamp: described power line carrier module includes the first power carrier coupling channel, the second power carrier coupling channel；Described first power carrier coupling channel is arranged between the live wire of ac cable and zero line, receives and send first carrier signal between the live wire and zero line of ac cable；Described second power carrier coupling channel is arranged between the ground wire of ac cable and zero line, between the ground wire and zero line of ac cable, receive and send the second carrier signal, also include filter circuit, power carrier processes circuit and carrier power amplifier circuit, described first power carrier coupling channel, second power carrier coupling channel is in parallel and is connected with one end of described filter circuit, the input that the other end of described filter circuit processes circuit with power carrier is connected, described power carrier processes the outfan of circuit and is connected with the input of carrier power amplifier circuit, the outfan of described carrier power amplifier circuit respectively with described first power carrier coupling channel, second power carrier coupling channel is connected；

The power carrier signal that described MCU module sends according to described power line carrier module, or the voltage signal after insulation blocking that the described collecting unit received gathers, generate corresponding MCU instruction；

Described driver element receives described MCU instruction, drives described first relay or second actuating of relay, and described driver element includes, pulse square wave-generator and at least one driving module；

The outfan of described pulse square wave-generator connects the first input end driving module, and this pulse square wave-generator is to the first input end input high frequency square wave pulse signal driving module, described driving module also has the second input for inputting low frequency drive signal, this driving module includes signaling conversion circuit unit and drive circuit unit, is connected by pulse transformer between signaling conversion circuit unit and drive circuit unit；

When the second input of described driving module is high level, the low frequency drive signal inputted and high frequency square wave pulse signal are converted to ac high frequency pulse signal by described signaling conversion circuit unit, and described pulse transformer passes through described drive circuit unit outputting drive voltage signal after carrying out this ac high frequency pulse signal isolating transformation；Described driving module is set at least two, and the first input end of each driving module connects the outfan of described pulse square wave-generator respectively, and the second input of each driving module is respectively used to input corresponding low frequency drive signal；

Described power module includes; one voltage conversion unit, an Overvoltage protecting unit and a power supply unit; the input of described voltage conversion unit is connected with described power supply unit to receive the first voltage that described power supply unit provides, and the outfan of described voltage conversion unit is connected with electronic component；Described Overvoltage protecting unit includes signal input part, signal processing circuit, low pressure amplitude limiter circuit, high pressure amplitude limiter circuit, and wherein, described signal input part is connected to input resistance；Described low pressure amplitude limiter circuit includes that the first amplitude limit controls voltage, the first divider resistance, the second divider resistance, the first amplitude limit electric capacity and NPN bipolar transistor；Described high pressure amplitude limiter circuit includes that the second amplitude limit controls voltage, the 3rd divider resistance, the 4th divider resistance, the second amplitude limit electric capacity and PNP bipolar transistor；

Described collecting unit includes: for system to be measured carries out the data acquisition module of data acquisition and/or output；Be connected with described data acquisition module, for described data acquisition module carried out logic control from Logic control module；For with the described main logic control module communicated from Logic control module and host computer bus；Described have the electrical isolation module for carrying out electrical isolation from connection between Logic control module and described main logic control module；Described main logic control module is also associated with bus bridge module, and described bus bridge module is for realizing the communication between described main logic control module and described host computer bus；Described electrical isolation module includes: be connected from Logic control module and described main logic control module with described respectively, for carrying out the power isolation module of isolated from power；It is connected from Logic control module and described main logic control module with described respectively, for carrying out the signal isolation module of signal isolation；Described include from Logic control module: from data package module, it is connected with described data acquisition module and described electrical isolation module respectively, for the first data of described data collecting module collected being packaged and through described electrical isolation module transfer to described main logic control module；Described main logic control module includes: master data decapsulation module, it is connected with described electrical isolation module and described bus bridge module respectively, for the first data received through described electrical isolation module being carried out decapsulation process and being sent to described host computer bus through described bus bridge module；And/or, described also include from Logic control module: from data decapsulation module, be connected with described electrical isolation module, for the second data received through described electrical isolation module being carried out decapsulation process and exporting to system side to be measured.

One end that the junction point that described first relay and the second relay are connected is connected with described first inductance and the second inductance is connected；The other end of described first inductance is connected with the first stationary contact of described first relay, and the other end of described second inductance is connected with the second stationary contact of described second relay；The movable contact of described first relay is connected with described collecting unit, and the movable contact of described second relay is connected with standard inductance.

Described voltage conversion unit includes: power supply circuits, energy storage booster circuit, malleation produce circuit, negative voltage generating circuit and reference voltage generating circuit；Wherein, described energy storage booster circuit includes boost chip and inductance；

The outfan of described power supply circuits the first end with the input of described boost chip and described inductance respectively is connected；

The input that second end of described inductance produces the input of circuit, the input of described negative voltage generating circuit and described reference voltage generating circuit with the control end of described boost chip, described malleation respectively connects；

Described power supply circuits are used for providing unipolar input voltage；

Described boost chip is for controlling the voltage at described inductance two ends, and the voltage at described inductance two ends is respectively supplied to described malleation generation circuit, described negative voltage generating circuit and described reference voltage generating circuit；

Described malleation produces circuit and produces positive voltage for the voltage according to described inductance two ends；

Described negative voltage generating circuit produces negative voltage for the voltage according to described inductance two ends；

Described reference voltage generating circuit produces reference voltage for the voltage according to described inductance two ends.

It is the first charge pump circuit that described malleation produces circuit, and wherein, described first charge pump circuit produces positive voltage for the voltage according to described inductance two ends, and described first charge pump circuit includes N level charge pump circuit, and N is the positive integer more than or equal to 1.

The N level charge pump circuit of described first charge pump circuit includes the first electric capacity, the first diode and the second diode；Wherein,

Second end of the negative pole of described first electric capacity and described inductance connects, and the positive pole of described first electric capacity negative pole with the positive pole of described first diode and described second diode respectively is connected；The positive pole of described second diode is connected with the negative pole of the first diode in the N-1 level charge pump circuit of described first charge pump circuit；

The negative pole of described first diode exports described positive voltage according to the voltage at described inductance two ends and the cathode voltage of described first electric capacity.

The emitter stage of described NPN bipolar transistor and the emitter stage of PNP bipolar transistor are all connected on the input of signal processing circuit；Described first divider resistance is series at the first amplitude limit and controls between voltage and the base stage of NPN bipolar transistor；Described second divider resistance and the first amplitude limit electric capacity are in parallel, and one end of this second divider resistance and the first amplitude limit electric capacity is all connected with the base stage of NPN bipolar transistor；The colelctor electrode of described second divider resistance and the other end of the first amplitude limit electric capacity and NPN bipolar transistor is both connected to reference on the ground；Described 3rd divider resistance is series at the second amplitude limit and controls between voltage and the base stage of PNP bipolar transistor；Described 4th divider resistance and the second amplitude limit electric capacity are in parallel, and one end of the 4th divider resistance and the second amplitude limit electric capacity all base stages with PNP bipolar transistor are connected；The colelctor electrode of described 4th divider resistance and the other end of the second amplitude limit electric capacity and PNP bipolar transistor is both connected to reference on the ground.

Described first amplitude limit controls voltage and the second amplitude limit controls voltage and is external dc voltage source, and the first amplitude limit controls voltage and is less than with reference to ground voltage, and the second amplitude limit controls voltage higher than with reference to ground voltage.

Described negative voltage generating circuit is the second charge pump circuit, and wherein, described second charge pump circuit exports described negative voltage for the voltage according to described inductance two ends, and described second charge pump circuit includes M level charge pump circuit, and M is the positive integer more than or equal to 1.

Described signaling conversion circuit unit includes NAND gate unit and full bridge inversion circuit unit, two outfans of described NAND gate unit connect two inputs of described full bridge inversion circuit unit respectively, described pulse transformer has primary side winding and secondary windings, two outfans of described full bridge inversion circuit unit connect two inputs of described primary side winding respectively, and two outfans of described secondary windings are connected with two inputs of described drive circuit unit respectively；

When the second input of described driving module is high level, described low frequency drive signal and high frequency square wave pulse signal are converted to the direct current high-frequency pulse signal that two-way is complementary by described NAND gate unit, and the frequency of this direct current high-frequency pulse signal is identical with described high frequency square wave pulse signal with pulsewidth, the direct current high-frequency pulse signal inversion that two-way is complementary is ac high frequency pulse signal by described full bridge inversion circuit unit.

In described NAND gate unit, the first input end of NAND gate device UA is the first input end IN1 of described driving module, second input of this NAND gate device UA connects the first input end of NAND gate device UB, the first input end of NAND gate device UB is the outfan of the second input described NAND gate device UA of connection of the second input IN2 of described driving module, this NAND gate device UB.

The utility model has the advantages that: simple to operate, convenient use.

Accompanying drawing explanation

Below in conjunction with embodiment and accompanying drawing, this utility model is described in detail, wherein:

Fig. 1 is structural representation of the present utility model.

Fig. 2 is the structured flowchart of power module.

Fig. 3 is the circuit diagram of Fig. 2.

Fig. 4 is the structural representation of voltage conversion unit.

Fig. 5 is the circuit diagram of driver element of the present utility model.

Fig. 6 is the circuit diagram of the driving module of Fig. 5.

Fig. 7 is the circuit diagram of power line carrier module of the present utility model.

Fig. 8 is the circuit diagram of collecting unit of the present utility model.

Detailed description of the invention

Of the present utility model detailed description of the invention be expanded on further below in conjunction with the accompanying drawings:

As shown in Figure 1, disclosed in embodiment of the present utility model, a kind of system power saver, specifically includes that the first relay K A1, the first inductance L2, first relay coil 101, second relay K A2, the second inductance L3, the second relay coil 102, MCU module 103, power module 104, power line carrier module 105, collecting unit 106 and driver element 107.

Power module 104, power line carrier module 105, collecting unit 106, driver element 107 is connected with MCU module 103 respectively, this power module 104 receives electrical network, and (L in Fig. 1 represents live wire, N represents zero line) in the voltage of exchange AC220V ± 20%, and the photovoltaic conversion received is become the running voltage of MCU module 103, in order to MCU module 103 normally works.Centralized Controller (not indicating in figure) at power line carrier module 105 and discharge lamp control chamber carries out communication, is used for sending and receiving power carrier signal.When Centralized Controller sends power carrier signal to electricity-saving appliance of the present utility model, the power carrier signal that Centralized Controller sends is received by power line carrier module 105, and send to MCU module 103 after demodulated for this power carrier signal, corresponding MCU instruction, drive output signal is generated again by MCU module 103.When MCU module 103 needs to feed back corresponding information to Centralized Controller, the i.e. work state information of present discharge lamp, dependent instruction is sent to power line carrier module 105 by MCU module 103, the instruction received is converted into power carrier signal by this power line carrier module 105, and sends to Centralized Controller on AC power cord by coupling it to.Communication is carried out, it is possible to realize the long-range control to discharge lamp 108, i.e. complete the Based Intelligent Control of discharge lamp 108 illumination by power line carrier module 105 and Centralized Controller.

Sampling module 106 is mainly used in gathering the voltage signal in circuit, and sends the voltage signal collected to MCU module 103 after insulation blocking.MCU module 103 is mainly used in receiving the voltage signal through sampling module 106 process and the power carrier signal of power line carrier module 105 transmission, and generate corresponding MCU instruction according to the signal received, and by power line carrier module 105 to the work state information of Centralized Controller feedback present discharge lamp 108.

Driver element 107 is mainly used in receiving the MCU instruction that MCU module 103 sends, and then makes the first relay coil 101 or the second relay coil 102 obtain electric, dead electricity according to this MCU instruction, and then drives the first relay K A1 or the second relay K A2 action.As shown in fig. 1, the first relay coil 101 is connected with driver element 107 respectively with the second relay coil 102.

First relay K A1 and the second relay K A2, all have three contacts, i.e. movable contacts, the first stationary contact and the second stationary contact.In this utility model disclosed embodiment, second stationary contact of the first relay K A1 and the first stationary contact of the second relay K A2 are connected, first inductance L2 and the second inductance L3 series connection, and first the one end connected with described first inductance L2 and the second inductance L3 at the junction point that is connected of relay K A1 and the second relay K A2 be connected, as shown in Figure 1.

Additionally, the other end of the first inductance L2 is then connected with the first stationary contact of the first relay K A1, the other end of the second inductance L3 is then connected with the second stationary contact of the second relay K A2；The movable contact of the first relay K A1 is then connected with collecting unit 106, and the movable contact of the second relay K A2 then standard inductance L1 original with discharge lamp circuit is connected.

It should be noted that the first inductance L2 is overvoltage winding, when line voltage distribution is too high, MCU module 103 sends corresponding MCU instruction, make driver element 107 drive the first relay K A1 action, the first inductance L2 is linked in circuit.

Additionally, the second inductance L3 is fall power winding, needs reduce discharge lamp power when, MCU module 103 controls the second relay K A2 action, the second inductance L3 is linked in circuit.

As shown in Figure 2,3, described power module 10 includes voltage conversion unit 12, Overvoltage protecting unit 16 and a power supply unit 18.Described voltage conversion unit 12 is connected with described Overvoltage protecting unit 16.Described power supply unit 18 is all connected with described voltage conversion unit 12 and described Overvoltage protecting unit 16.Described voltage conversion unit 12 for being converted into running voltage by the first voltage that described power supply unit 18 provides, and is exported from the outfan of described voltage conversion unit 12 by the voltage after conversion.Described Overvoltage protecting unit 16, when the voltage exported at the outfan of described voltage conversion unit 12 is more than running voltage, controls described power supply unit 18 and stops voltage output, thus to protecting.

Described Overvoltage protecting unit 16 includes that overvoltage crowbar, overvoltage crowbar include signal input part Vs, signal processing circuit, low pressure amplitude limiter circuit, high pressure amplitude limiter circuit, and wherein, described signal input part Vs is connected to input resistance Ri；Described low pressure amplitude limiter circuit includes that the first amplitude limit controls voltage Ve, the first divider resistance R11, the second divider resistance R12, the first amplitude limit electric capacity C11 and NPN bipolar transistor Q1；Described high pressure amplitude limiter circuit includes that the second amplitude limit controls voltage Vc, the 3rd divider resistance R13, the 4th divider resistance R14, the second amplitude limit electric capacity C12 and PNP bipolar transistor Q2；The emitter stage of described NPN bipolar transistor Q1 and the emitter stage of PNP bipolar transistor Q2 are all connected on the input Vi of signal processing circuit；Described first divider resistance R1 is series at the first amplitude limit and controls between voltage Ve and the base stage of NPN bipolar transistor Q1；Described second divider resistance R2 and the first amplitude limit electric capacity C11 is in parallel, and one end of this second divider resistance R12 and the first amplitude limit electric capacity C11 is all connected with the base stage of NPN bipolar transistor Q1；The colelctor electrode of described second divider resistance R12 and the other end of the first amplitude limit electric capacity C11 and NPN bipolar transistor Q1 is both connected to reference on ground GND；Described 3rd divider resistance R13 is series at the second amplitude limit and controls between voltage Vc and the base stage of PNP bipolar transistor Q2；Described 4th divider resistance R14 and the second amplitude limit electric capacity C12 are in parallel, and one end of the 4th divider resistance R14 and the second amplitude limit electric capacity C12 all base stages with PNP bipolar transistor Q2 are connected；The colelctor electrode of described 4th divider resistance R14 and the other end of the second amplitude limit electric capacity C12 and PNP bipolar transistor Q2 is both connected to reference on ground GND.

Described first amplitude limit controls voltage Ve and the second amplitude limit controls voltage Vc and is external dc voltage source, and the first amplitude limit controls voltage Ve and is less than with reference to ground GND voltage, and the second amplitude limit controls voltage Vc higher than reference ground GND voltage.

Given first amplitude limit controls voltage Ve and the second amplitude limit controls voltage Vc, the base voltage of NPN bipolar transistor Q1 is fixed on Va, the base voltage of Va=Ve × R12/ (R11+R12), PNP bipolar transistor Q2 is fixed on Vb, Vb=Vc × R14/ (R13+R14)；When the input terminal voltage Vi of signal processing circuit is less than the base voltage Va of NPN bipolar transistor Q1, the emitter junction positively biased of NPN bipolar transistor Q1, collector junction are reverse-biased, NPN bipolar transistor Q1 is operated in magnifying state, and the input terminal voltage Vi of signal processing circuit is restricted to the base voltage Va of NPN bipolar transistor Q1 and deducts its emitter junction junction voltage；When the input terminal voltage Vi of signal processing circuit is higher than the base voltage Vb of PNP bipolar transistor Q2, the emitter junction positively biased of PNP bipolar transistor Q2, collector junction are reverse-biased, PNP bipolar transistor Q2 is operated in magnifying state, and the input terminal voltage Vi of signal processing circuit is restricted to the base voltage Vb of PNP bipolar transistor Q2 plus its emitter junction junction voltage.Va and Vb is played filter action by the first amplitude limit electric capacity C11 and the second amplitude limit electric capacity C12 respectively.The advantage of overvoltage crowbar is that circuit structure is simple, and amplitude limit precision is high, can conveniently change limiting voltage size.

As shown in Figure 4, negative voltage generating circuit 4 is a 1 grade of charge pump circuit that can produce negative voltage, wherein, electric capacity C2 and diode D2, D3 constitute a charge pump circuit, then the second electric capacity is C2, and the left end of the second electric capacity C2 is positive pole, and right-hand member is negative pole, 3rd diode is D2, and the 4th diode is D3.The positive pole of the second electric capacity C2 is connected with the right-hand member of inductance L1, and the negative pole of the second electric capacity C2 is connected with the positive pole of the 3rd diode D2 and the negative pole of the 4th diode D3 respectively, the positive pole output negative voltage of the 4th diode D3, the minus earth of the 3rd diode D2.The specific works principle of negative voltage generating circuit 4 is as follows: first charged electric capacity C2 by the output voltage of inductance L1, and electric capacity C2 polarity is left positive right negative, is then turned off inductance L1 to electric capacity C2 charging path；Because the voltage at electric capacity C2 two ends can not suddenly change, therefore, the cathode voltage on the right will obtain negative voltage VGL by diode D3 output.If M is more than or equal to 2, then the negative pole of the 3rd diode D2 and the positive pole connection of the 3rd diode in M-1 level charge pump circuit, be thusly-formed multiple-stage charge pump.Negative voltage generating circuit 4 can also increase electric capacity C3 and Zener diode D8, electric capacity C3 at the outfan of M level charge pump circuit and be used for being filtered the negative voltage of output processing, and Zener diode D8 realizes voltage stabilizing output.Reference voltage generating circuit includes at least one Zener diode, and the positive pole of Zener diode is connected with the second end of inductance, and the negative pole of Zener diode is according to the cathode voltage output reference voltage of Zener diode.

Reference voltage generating circuit 5 includes that Zener diode D1, the positive pole of Zener diode D1 are connected with the right-hand member of inductance L1, negative pole output negative voltage VGL.Reference voltage generating circuit 5 can also increase an electric capacity C1, and electric capacity C1 is for being filtered processing to the negative voltage of output.

The voltage conversion circuit that the present embodiment provides, uses multiple-stage charge pump to realize the output of positive voltage, negative voltage respectively, changes the positive voltage of output and the size of negative voltage by changing the progression of charge pump circuit, and circuit structure is simple, and the most adjustable.This drive circuit realizes by design of integer electro-circuit utilizing pulse transformer to carry out signal isolation, thus the signal isolation method of photoelectric coupling is used compared with conventional driving circuit, drive circuit of the present utility model is without extra independent current source such that it is able to save power supply, its better working stability.

As shown in Figure 5,6, driver element of the present utility model includes, a kind of drive circuit, drives module MD2 including a pulse square wave-generator MD1 and one；The outfan OUT of pulse square wave-generator MD1 connects the first input end IN1 driving module MD2, module MD2 is driven also to have the second input IN2 for inputting low frequency drive signal DRIVEA, this driving module includes signaling conversion circuit unit 100 and drive circuit unit 200, is connected by pulse transformer T1 between signaling conversion circuit unit 100 and drive circuit unit 200.

Signaling conversion circuit unit 100 includes that two outfans of NAND gate unit 111 and full bridge inversion circuit unit 112 NAND gate unit 101 connect two inputs of full bridge inversion circuit unit 112 respectively, and pulse transformer T1 has primary side winding And secondary windings, two outfans of full bridge inversion circuit unit 112 connect two inputs of primary side winding respectively, and two outfans of secondary windings are connected with two inputs of drive circuit unit 200 respectively；Above-mentioned drive circuit unit 200 includes full bridge rectifier 201 and output circuit 202, full bridge rectifier 201 is connected with two outfans of pulse transformer T1 secondary windings, this full bridge rectifier 201 has cathode output end and cathode output end, and output circuit 202 is connected with described cathode output end and cathode output end.

Wherein, in above-mentioned NAND gate unit 111, the first input end of NAND gate device UA is the first input end IN1 driving module MD2, second input of this NAND gate device UA connects the first input end of NAND gate device UB, the first input end of NAND gate device UB is the outfan of the second input connection NAND gate device UA of the second input IN2, this NAND gate device UB that drive module MD2.nullIn above-mentioned full bridge inversion circuit unit 112，One end of gate electrode resistance R101 and gate electrode resistance R103 outfan with NAND gate device UB respectively is connected，The other end of gate electrode resistance R101 connects the gate pole of P-channel field-effect transistor (PEFT) pipe V1，The source electrode of P-channel field-effect transistor (PEFT) pipe V1 connects one end of current-limiting resistance R105，The other end of current-limiting resistance R105 connects power supply VCC，Power supply VCC is also connected with current-limiting resistance R106，The other end of this current-limiting resistance R106 connects the source electrode of P-channel field-effect transistor (PEFT) pipe V2，The gate pole of P-channel field-effect transistor (PEFT) pipe V2 connects gate electrode resistance R102，The other end of gate electrode resistance R102 connects the outfan of NAND gate device UA，The outfan of this NAND gate device UA is also connected with gate electrode resistance R104，The other end of gate electrode resistance R104 connects the gate pole of N-channel field effect transistor V4，The source electrode of this N-channel field effect transistor V4 connects power supply ground，The other end of gate electrode resistance R103 is connected with the gate pole of N-channel field effect transistor V3，The source electrode of this N-channel field effect transistor V3 also connects power supply ground，The drain electrode of P-channel field-effect transistor (PEFT) pipe V2 and the drain electrode of N-channel field effect transistor V4 one end with pulse transformer T1 primary side winding respectively is connected，The drain electrode of P-channel field-effect transistor (PEFT) pipe V1 with the drain electrode of N-channel field effect transistor V3 respectively the other end with pulse transformer T1 primary side winding be connected.

Above-mentioned full bridge rectifier 201 includes four diode D101, D102, D10103, D104, one end of pulse transformer T1 secondary windings connects anode and the negative electrode of diode D10103 of diode D101 respectively, the negative electrode of diode D101 connects the negative electrode of diode D102, the anode of diode D102 is connected the other end of pulse transformer T1 secondary windings respectively with the negative electrode of diode D104, the anode of diode D104 is connected with the anode of diode D10103, in this full bridge rectifier 201, the anode of diode D101 or diode D102 is above-mentioned cathode output end, the negative electrode of diode D10103 or diode D104 is above-mentioned cathode output end.

Above-mentioned output circuit 202 includes diode D105, P-channel field-effect transistor (PEFT) pipe V5, resistance R107 and resistance R108, the anode of diode D105 connects above-mentioned cathode output end, the gate pole of P-channel field-effect transistor (PEFT) pipe V5 and resistance R107, the other end of resistance R107 connects above-mentioned cathode output end and the drain electrode of P-channel field-effect transistor (PEFT) pipe V5, drive voltage signal outfan is formed between source electrode and the other end G of resistance R108, resistance R108 and the above-mentioned cathode output end E of the negative electrode connection P-channel field-effect transistor (PEFT) pipe V5 of diode D105.Field effect transistor V1, V2, V3, V4 and V5 can be MOSFET.

This drive circuit, the mainly operation principle of driving module is: drive the outfan OUT of the first input end IN1 and pulse square wave-generator MD1 of module MD2 to be connected, the the second input IN2 driving module MD2 drives signal to be connected with external low frequency, under normal circumstances, the frequency range of the pulse square wave of pulse square wave-generator MD1 output is tens KHz to tens KHz, and the external low frequency being connected with input IN2 drives the frequency range of signal DRIVEA between several hertz of zero point to hundreds of hertz；Under conditions of the second input IN2 driving module MD2 is high level: when the first input end IN1 driving module MD2 is high level, the output pin of NAND gate device UA is low level, and the output pin of NAND gate device UB is then high level；When the first input end IN1 driving module MD2 is low level, the output pin of NAND gate device UA is high level, and the output pin of NAND gate device UB is then low level.nullSo when input IN2 is high level，The output pin output two-way frequency of NAND gate device UA with UB and pulsewidth and described direct current high-frequency impulse complementary signal identical for first input end IN1，The signal of this two-way complementation is by gate electrode resistance R101、R102、R103 and R104 drives by P-channel field-effect transistor (PEFT) pipe V1、V2 and N-channel field effectiveness pipe V3、The full bridge inverter that V4 is formed，And then be ac high frequency pulse signal by direct current high-frequency pulse signal inversion，Ac high frequency pulse signal isolates transformation via pulse transformer T1 again，The ac high frequency pulse signal of pulse transformer T1 output is through diode D101、D102、After full bridge rectifier 201 rectification of D10103 and D104 composition，Its cathode output end then has positive voltage to export，Now P-channel field-effect transistor (PEFT) pipe V5 is in cut-off state owing to gate pole is identical with source voltage，So now just having driving voltage on drive voltage signal outfan G and E，Driven power tube is finally made to turn on；Under the conditions of the second input IN2 of driving module MD2 is low level: the output pin of NAND gate device UA and UB all exports high level, so that field effect transistor V3 in inverter bridge and V4 conducting, thus pulse transformer T1 primary side winding two ends all with power supply be connected and no-voltage, now pulse transformer T1 outfan does not has voltage yet, cause and produce voltage difference between gate pole and the source electrode of P-channel field-effect transistor (PEFT) pipe V5 and turn it on, drive voltage signal outfan G with E is made to be turned on by R108, voltage is lost between i.e. G and E, ultimately result in driven power tube and be in blocking state.In a word, between drive voltage signal outfan G and E, the drive voltage signal of output follows the low frequency drive signal driven on module MD2 the second input IN2, when this second input IN2 is high level, drive and just have driving signal on G and E of module, otherwise then without driving signal, it is achieved thereby that the purpose of drive circuit.The voltage conversion circuit that the present embodiment provides, uses multiple-stage charge pump to realize the output of positive voltage, negative voltage respectively, changes the positive voltage of output and the size of negative voltage by changing the progression of charge pump circuit, and circuit structure is simple, and the most adjustable.This drive circuit realizes by design of integer electro-circuit utilizing pulse transformer to carry out signal isolation, thus the signal isolation method of photoelectric coupling is used compared with conventional driving circuit, drive circuit of the present utility model is without extra independent current source such that it is able to save power supply, its better working stability.

As shown in Figure 7, first power carrier coupling channel the 1051, second power carrier coupling channel 1052, filter circuit 1053, power carrier process circuit 1054 and carrier power amplifier circuit 1055, described first power carrier coupling channel 1051 is arranged between the live wire AC_L of ac cable and zero line AC_N, receives and send first carrier signal between the live wire AC_L and zero line AC_N of ac cable；Described second power carrier coupling channel 1052 is arranged between the ground wire AC_PE of ac cable and zero line AC_N, receives and send the second carrier signal between the ground wire AC_PE and zero line AC_N of ac cable.Owing to existing noise and interference are main between live wire and zero line, high-frequency interferencing signal ratio is more serious, couples a signal on zero line and ground wire, because not having voltage between zero line and ground wire or not having High-frequency Interference, comparatively speaking, do not have the interference signal between live wire and zero line big.Power carrier signal is after carrier power amplifier circuit sends, power carrier signal is coupled to the first power carrier coupling channel 1051 simultaneously, in second power carrier coupling channel 1,052 two passage, if the jam-to-signal between live wire and zero line is bigger, so power carrier signal can be by the channel transfer of zero line and ground wire to next equipment, next equipment have received the coupled signal of two passages simultaneously, as long as there being a passage can normally receive signal, so communication will go on, when well avoiding single channel transmission data, the problem causing transmitting information because of interference.Meanwhile, as long as this circuit increases by a road power carrier coupling channel, i.e. can realize multichannel carrier coupling, the transformation to available circuit is little, and cost is little.

Simultaneously because two passages can transmit signal, can also carry out data transmission at unidirectional current or in the case of there is no voltage between ground wire AC_PE and zero line AC_N, just can only can carry out data transmission in the case of there is alternating current with existing, expand practicality.

Described first power carrier coupling channel 1051 includes inductance L51 on May Day, the one or five electric capacity C51 and the first coupling transformer T1, described May Day inductance L51 and electric capacity C51 series connection on May Day and one end be connected with live wire AC_L, the other end and the first coupling transformer T1 are connected, the side of described first coupling transformer T1 is connected with zero line AC_N with live wire AC_L respectively, and opposite side is connected with outfan, the filter circuit 1053 of carrier power amplifier circuit 1055.Described second power carrier coupling channel 1052 includes the second inductance L52, five or two electric capacity C52 and the second coupling transformer T2, described second inductance L52 and the five or two electric capacity C52 series connection and one end are connected with ground wire AC_PE, the other end and the second coupling transformer T2 are connected, the side of described second coupling transformer T2 is connected with zero line AC_N with ground wire AC_PE respectively, and opposite side is connected with outfan, the filter circuit 1053 of carrier power amplifier circuit 1055.

Coupled modes of the present utility model can carry out high-low pressure isolation, and insulating pressure can reach 4KV.Have employed triple insulated wire two-wire rich mode simultaneously.Owing to this utility model is 1:1 coupling, noise or interference will not be amplified, utilize triple insulated wire carry out two-wire and have mercy on simultaneously, compare traditional independent winding mode, interference can be reduced, it is ensured that signal is undistorted.Described first power carrier coupling channel the 1051, second power carrier coupling channel 1052 is in parallel and is connected with one end of described filter circuit 1053, the input that the other end of described filter circuit 1053 processes circuit 1054 with power carrier is connected, described power carrier processes the outfan of circuit 1054 and is connected with the input of carrier power amplifier circuit 1055, and the outfan of described carrier power amplifier circuit 1055 is connected with described first power carrier coupling channel the 1051, second power carrier coupling channel 1052 respectively.

nullDescribed filter circuit includes high resistant low-resistance third-order filter、Attenuator and amplitude limiter circuit，Described high resistant low-resistance third-order filter includes: the May 4th electric capacity C54 in parallel and the May 4th inductance L54、Five or five electric capacity C55 in parallel and the five or five inductance L55、Five or six electric capacity C56 in parallel and the 6th inductance L6，Five or seven electric capacity C57 and the five or eight electric capacity C58，The five or five electric capacity C55 and the five or five inductance L55 one end of described parallel connection are connected with earth terminal，The other end and the May 4th electric capacity C54 in parallel and one end of the May 4th inductance L54、One end of five or eight electric capacity C58 is connected，One end of described five or seven electric capacity C57 is connected with coupling channel，The other end of described five or seven electric capacity C57 is connected with the other end of the May 4th electric capacity C54 in parallel and the May 4th inductance L54，The other end of described five or eight electric capacity C58 is connected with one end of the five or six electric capacity C56 in parallel and the five or six inductance L56.The present embodiment uses T-shaped third-order filter to be filtered, and bandwidth is relatively wide, and filter effect is more preferable, in other embodiments, it would however also be possible to employ traditional π type filtering.Described the May 4th inductance L54 and the May 4th electric capacity C54 is in parallel, and the five or six inductance L56 and the five or six electric capacity C56 is in parallel, has intercepted the high frequency waves of more than 140K；Five or five inductance L55 and the five or five electric capacity C55 is in parallel, has intercepted the high frequency waves of below 120K, it is achieved thereby that the filtering of high resistant low-resistance.

Described attenuator includes resistance R51 on May Day, the five or two resistance R52, switching tube Q51 on May Day and control signal end CAGC, described May Day resistance R51 one end ground connection, described May Day, the other end of resistance R51 was connected with control signal end CAGC, the control of switching tube Q51 on May Day, described May Day switching tube Q51 one end ground connection, one end of the other end and the five or two resistance R52 is connected, and the other end of described five or two resistance R52 connects power carrier and processes circuit 1054.Can be by power carrier signal by this circuit decay 60db by attenuator, with decay interference signal.

Described amplitude limiter circuit includes diode D51 and D52 that both direction is contrary and in parallel, one end ground connection of the diode of described parallel connection, and another termination power carrier processes circuit.Owing to the conducting voltage of diode is 0.7V, by carrier signal amplitude limit within 0.7V, in order to avoid signal is excessive burns carrier chip.

As shown in Figure 8, collecting unit of the present utility model includes: data acquisition module 211, from Logic control module 212, main logic control module 213, electrical isolation module 214 and bus bridge module 215.For system to be measured being carried out the data acquisition module of data acquisition and/or output；Be connected with described data acquisition module, for described data acquisition module carried out logic control from Logic control module；For with described from Logic control module and main logic control module；Described have the electrical isolation module for carrying out electrical isolation from connection between Logic control module and described main logic control module；Described main logic control module is also associated with bus bridge module, and described bus bridge module is for realizing the communication of described main logic control module；Described electrical isolation module includes: be connected from Logic control module and described main logic control module with described respectively, for carrying out the power isolation module of isolated from power；It is connected from Logic control module and described main logic control module with described respectively, for carrying out the signal isolation module of signal isolation；Described include from Logic control module: from data package module, it is connected with described data acquisition module and described electrical isolation module respectively, for the first data of described data collecting module collected being packaged and through described electrical isolation module transfer to described main logic control module；Described main logic control module includes: master data decapsulation module, it is connected with described electrical isolation module and described bus bridge module respectively, for the first data received through described electrical isolation module being carried out decapsulation process and sending through described bus bridge module；And/or, described also include from Logic control module: from data decapsulation module, be connected with described electrical isolation module, for the second data received through described electrical isolation module being carried out decapsulation process and exporting to system side to be measured；Described main logic control module also includes: master data package module, it is connected with described bus bridge module and electrical isolation module respectively, for the second data received through described bus bridge module being packaged process and being sent to through described electrical isolation module described from Logic control module；Described main logic control module also includes: the first storage control and first memory；Described first storage control is connected with described master data decapsulation module, described first memory and described bus bridge module respectively, for the first data that described master data decapsulation module exports being stored to described first memory the first data of being stored by described first memory through described bus bridge module Batch sending by several times；And/or, the second storage control and second memory；Described second storage control is connected with described master data package module, described second memory and described bus bridge module respectively, for the second data received through described bus bridge module being stored to described second memory the second data extremely described master data package module of Batch sending by several times of being stored by described second memory.Described signal isolation module is: isolating chip, Magnetic isolation device, optical coupling isolator or photoisolator.Described is from FPGA module from Logic control module, and described main logic control module is main FPGA module.Described main logic control module also includes: the first buffer being connected with described first storage control, and described first buffer is for caching the first data of described master data decapsulation module output the first data of being cached through described first storage control Batch sending by several times to described first memory under the control of described first storage control；And/or, the second buffer being connected with described second storage control, described second buffer is for caching the second data received from described bus bridge module the second data cached through described second storage control Batch sending by several times to described from Logic control module under the control of described second storage control.

Described bus bridge module is pci bridge chip.Described data acquisition module includes: numeral input/output module, D/A converter module and/or analog-to-digital conversion module.Described numeral input/output module includes multi-path digital input channel and multi-path digital output channel；And/or, described D/A converter module includes Multi-path synchronous analog output channel；And/or, the figure place of described analog-to-digital conversion module is 24 bits, and sample rate is 4,000,000 samplings per second；Or, described analog-to-digital conversion module has multichannel analog signals input channel, described analog-to-digital conversion module includes that input selects unit, programmable gain amplifier unit and AD conversion unit, described input selects unit for described multichannel analog signals input channel carries out gating control, described programmable gain amplifier unit is for amplifying by the analogue signal of described multichannel analog signals input channel input, and described AD conversion unit analogue signal after amplifying is converted to digital signal and exports；And/or, described numeral input/output module, described D/A converter module and described analog-to-digital conversion module communicate to connect successively.

Acquisition module of the present utility model, arrange from Logic control module in nearly system side to be measured, in nearly host computer (also referred to as main frame) side, main logic control module is set, it is digital signal from the data of transmission between Logic control module and main logic control module, electrical isolation module is arranged at the part i.e. signal isolation link of data collecting card transmission digital signal and is arranged at the numerical portion of signal, not only avoid the common-mode voltage etc. introducing measured system to disturb, and avoid and analogue signal is isolated the loss of signal caused, achieve the isolated collection of data at lower cost.

The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all any amendment, equivalent and improvement etc. made within spirit of the present utility model and principle, within should be included in protection domain of the present utility model.

Claims (10)

1. a system power saver, it is characterised in that including: the first relay, the second relay, the first inductance of series connection and the second inductance, MCU module, and power module, collecting unit, power line carrier module and the driver element being connected with MCU module respectively；

Wherein, described first inductance is overvoltage winding, and described second inductance is fall power winding；

Described power module provides running voltage for described MCU module；

Described power line carrier module receives the power carrier signal that sent by Centralized Controller, and is sent to MCU module after being demodulated described power carrier signal processing；And receive the feedback command of described MCU module feedback, and described feedback command is converted into power carrier signal, and is sent to described Centralized Controller on AC power cord by coupling it to；Described feedback command is the work state information of present discharge lamp: described power line carrier module includes the first power carrier coupling channel, the second power carrier coupling channel；Described first power carrier coupling channel is arranged between the live wire of ac cable and zero line, receives and send first carrier signal between the live wire and zero line of ac cable；Described second power carrier coupling channel is arranged between the ground wire of ac cable and zero line, between the ground wire and zero line of ac cable, receive and send the second carrier signal, also include filter circuit, power carrier processes circuit and carrier power amplifier circuit, described first power carrier coupling channel, second power carrier coupling channel is in parallel and is connected with one end of described filter circuit, the input that the other end of described filter circuit processes circuit with power carrier is connected, described power carrier processes the outfan of circuit and is connected with the input of carrier power amplifier circuit, the outfan of described carrier power amplifier circuit respectively with described first power carrier coupling channel, second power carrier coupling channel is connected；

The power carrier signal that described MCU module sends according to described power line carrier module, or the voltage signal after insulation blocking that the described collecting unit received gathers, generate corresponding MCU instruction；

Described driver element receives described MCU instruction, drives described first relay or second actuating of relay, and described driver element includes, pulse square wave-generator and at least one driving module；

The outfan of described pulse square wave-generator connects the first input end driving module, and this pulse square wave-generator is to the first input end input high frequency square wave pulse signal driving module, described driving module also has the second input for inputting low frequency drive signal, this driving module includes signaling conversion circuit unit and drive circuit unit, is connected by pulse transformer between signaling conversion circuit unit and drive circuit unit；

When the second input of described driving module is high level, the low frequency drive signal inputted and high frequency square wave pulse signal are converted to ac high frequency pulse signal by described signaling conversion circuit unit, and described pulse transformer passes through described drive circuit unit outputting drive voltage signal after carrying out this ac high frequency pulse signal isolating transformation；Described driving module is set at least two, and the first input end of each driving module connects the outfan of described pulse square wave-generator respectively, and the second input of each driving module is respectively used to input corresponding low frequency drive signal；

Described power module includes; one voltage conversion unit, an Overvoltage protecting unit and a power supply unit; the input of described voltage conversion unit is connected with described power supply unit to receive the first voltage that described power supply unit provides, and the outfan of described voltage conversion unit is connected with electronic component；Described Overvoltage protecting unit includes signal input part, signal processing circuit, low pressure amplitude limiter circuit, high pressure amplitude limiter circuit, and wherein, described signal input part is connected to input resistance；Described low pressure amplitude limiter circuit includes that the first amplitude limit controls voltage, the first divider resistance, the second divider resistance, the first amplitude limit electric capacity and NPN bipolar transistor；Described high pressure amplitude limiter circuit includes that the second amplitude limit controls voltage, the 3rd divider resistance, the 4th divider resistance, the second amplitude limit electric capacity and PNP bipolar transistor；

Described collecting unit includes: for system to be measured carries out the data acquisition module of data acquisition and/or output；Be connected with described data acquisition module, for described data acquisition module carried out logic control from Logic control module；For with described from Logic control module and main logic control module；Described have the electrical isolation module for carrying out electrical isolation from connection between Logic control module and described main logic control module；Described main logic control module is also associated with bus bridge module, and described bus bridge module is for realizing the communication of described main logic control module；Described electrical isolation module includes: be connected from Logic control module and described main logic control module with described respectively, for carrying out the power isolation module of isolated from power；It is connected from Logic control module and described main logic control module with described respectively, for carrying out the signal isolation module of signal isolation；Described include from Logic control module: from data package module, it is connected with described data acquisition module and described electrical isolation module respectively, for the first data of described data collecting module collected being packaged and through described electrical isolation module transfer to described main logic control module；Described main logic control module includes: master data decapsulation module, is connected with described electrical isolation module and described bus bridge module respectively, for the first data received through described electrical isolation module are carried out decapsulation process；And/or, described also include from Logic control module: from data decapsulation module, be connected with described electrical isolation module, for the second data received through described electrical isolation module being carried out decapsulation process and exporting to system side to be measured.

System power saver the most according to claim 1, it is characterised in that one end that the junction point that described first relay and the second relay are connected is connected with described first inductance and the second inductance is connected；The other end of described first inductance is connected with the first stationary contact of described first relay, and the other end of described second inductance is connected with the second stationary contact of described second relay；The movable contact of described first relay is connected with described collecting unit, and the movable contact of described second relay is connected with standard inductance.

System power saver the most according to claim 2, it is characterised in that described voltage conversion unit includes: power supply circuits, energy storage booster circuit, malleation produce circuit, negative voltage generating circuit and reference voltage generating circuit；Wherein, described energy storage booster circuit includes boost chip and inductance；

The outfan of described power supply circuits the first end with the input of described boost chip and described inductance respectively is connected；

The input that second end of described inductance produces the input of circuit, the input of described negative voltage generating circuit and described reference voltage generating circuit with the control end of described boost chip, described malleation respectively connects；

Described power supply circuits are used for providing unipolar input voltage；

Described boost chip is for controlling the voltage at described inductance two ends, and the voltage at described inductance two ends is respectively supplied to described malleation generation circuit, described negative voltage generating circuit and described reference voltage generating circuit；

Described malleation produces circuit and produces positive voltage for the voltage according to described inductance two ends；

Described negative voltage generating circuit produces negative voltage for the voltage according to described inductance two ends；

Described reference voltage generating circuit produces reference voltage for the voltage according to described inductance two ends.

System power saver the most according to claim 3, it is characterized in that, it is the first charge pump circuit that described malleation produces circuit, wherein, described first charge pump circuit produces positive voltage for the voltage according to described inductance two ends, and described first charge pump circuit includes N level charge pump circuit, N is the positive integer more than or equal to 1.

System power saver the most according to claim 4, it is characterised in that the N level charge pump circuit of described first charge pump circuit includes the first electric capacity, the first diode and the second diode；Wherein,

Second end of the negative pole of described first electric capacity and described inductance connects, and the positive pole of described first electric capacity negative pole with the positive pole of described first diode and described second diode respectively is connected；The positive pole of described second diode is connected with the negative pole of the first diode in the N-1 level charge pump circuit of described first charge pump circuit；

The negative pole of described first diode exports described positive voltage according to the voltage at described inductance two ends and the cathode voltage of described first electric capacity.

System power saver the most according to claim 5, it is characterised in that the emitter stage of described NPN bipolar transistor and the emitter stage of PNP bipolar transistor are all connected on the input of signal processing circuit；Described first divider resistance is series at the first amplitude limit and controls between voltage and the base stage of NPN bipolar transistor；Described second divider resistance and the first amplitude limit electric capacity are in parallel, and one end of this second divider resistance and the first amplitude limit electric capacity is all connected with the base stage of NPN bipolar transistor；The colelctor electrode of described second divider resistance and the other end of the first amplitude limit electric capacity and NPN bipolar transistor is both connected to reference on the ground；Described 3rd divider resistance is series at the second amplitude limit and controls between voltage and the base stage of PNP bipolar transistor；Described 4th divider resistance and the second amplitude limit electric capacity are in parallel, and one end of the 4th divider resistance and the second amplitude limit electric capacity all base stages with PNP bipolar transistor are connected；The colelctor electrode of described 4th divider resistance and the other end of the second amplitude limit electric capacity and PNP bipolar transistor is both connected to reference on the ground.

System power saver the most according to claim 6, it is characterized in that, described first amplitude limit controls voltage and the second amplitude limit controls voltage and is external dc voltage source, and the first amplitude limit controls voltage and is less than with reference to ground voltage, and the second amplitude limit controls voltage higher than with reference to ground voltage.

System power saver the most according to claim 7, it is characterized in that, described negative voltage generating circuit is the second charge pump circuit, wherein, described second charge pump circuit exports described negative voltage for the voltage according to described inductance two ends, and described second charge pump circuit includes M level charge pump circuit, M is the positive integer more than or equal to 1.

System power saver the most according to claim 8, it is characterized in that, described signaling conversion circuit unit includes NAND gate unit and full bridge inversion circuit unit, two outfans of described NAND gate unit connect two inputs of described full bridge inversion circuit unit respectively, described pulse transformer has primary side winding and secondary windings, two outfans of described full bridge inversion circuit unit connect two inputs of described primary side winding respectively, and two outfans of described secondary windings are connected with two inputs of described drive circuit unit respectively；

When the second input of described driving module is high level, described low frequency drive signal and high frequency square wave pulse signal are converted to the direct current high-frequency pulse signal that two-way is complementary by described NAND gate unit, and the frequency of this direct current high-frequency pulse signal is identical with described high frequency square wave pulse signal with pulsewidth, the direct current high-frequency pulse signal inversion that two-way is complementary is ac high frequency pulse signal by described full bridge inversion circuit unit.

System power saver the most according to claim 9, it is characterized in that, in described NAND gate unit, the first input end of NAND gate device UA is the first input end IN1 of described driving module, second input of this NAND gate device UA connects the first input end of NAND gate device UB, the first input end of NAND gate device UB is the outfan of the second input described NAND gate device UA of connection of the second input IN2 of described driving module, this NAND gate device UB.