CN112702088A - Master-slave bus type bipolar waveform power carrier communication - Google Patents
Master-slave bus type bipolar waveform power carrier communication Download PDFInfo
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Abstract
A master-slave bus type bipolar waveform power carrier communication comprises a master transceiver and n slave transceivers connected with the master transceiver in parallel through a two-wire bus, wherein the master transceiver comprises a master communication control port, a master sending module and a master receiving module, the master sending module and the master receiving module are controlled by the master communication control port, and the output ends of the master sending module and the master receiving module are respectively connected with a master wire core of the bus; the slave transceiver comprises a slave communication control port, a slave transmitting module, a slave receiving module and a power module, wherein the input end of the power module is connected with the bus in parallel to obtain electric energy to supply power to the slave transceiver, and the input end of the slave receiving module is connected with the bus in parallel to receive signals from the master transceiver. The communication scheme has high reliability, long transmission distance, good flexibility and expansibility and strong continuous sending capability and anti-interference capability, and is particularly suitable for consumable application scenes such as electronic detonators or the arrangement of a large number of micro sensors and the arrangement and application of a low-voltage controllable LED lighting network.
Description
Technical Field
The invention relates to a communication system, in particular to master-slave bus type bipolar waveform power carrier communication based on low-voltage direct current input.
Background
The prior art mainly has the following defects:
1. common power carrier communication technology is generally designed based on a 220V alternating current environment and lines of a mains supply, and has the advantages of high communication speed, long distance, high implementation cost, large number of required elements and large volume, and high voltage has safety problems.
2. The low-voltage direct-current power carrier communication scheme used in some special industries realizes power supply and communication in a pulse superposition or low-voltage pulling mode, can realize smaller volume, but has generally poor communication interference resistance and shorter effective communication distance.
Disclosure of Invention
The invention aims to provide master-slave bus type bipolar waveform power carrier communication based on low-voltage direct current input so as to overcome the defects in the prior art.
The technical scheme of the invention is as follows: a master-slave bus type bipolar waveform power carrier communication comprises a master end transceiver and n slave end transceivers, wherein the n slave end transceivers are connected with the master end transceiver in parallel through a two-wire bus;
the main-end transceiver comprises a main-end communication control port, a main-end sending module and a main-end receiving module, wherein one output end of the main-end sending module is connected with the input end of the main-end receiving module, the other output end of the main-end sending module is connected with a main-line wire core X1 of the bus, the output end of the main-end receiving module is connected with a main-line wire core X2 of the bus, and the main-end communication control port is respectively connected with the control ends of the main-end sending module and the main-end;
the n slave end transceivers have the same structure and comprise a slave end communication control port, a slave end sending module, a slave end receiving module and a power supply module, wherein the input end of the power supply module is connected with the main line wire core X1 and the main line wire core X2 in parallel to obtain electric energy, and the output end of the power supply module is respectively connected with the slave end communication control port, the slave end sending module and the slave end receiving module to provide working power supply for the slave end communication control port, the slave end sending module and the slave end receiving module; the input end of the slave end receiving module is connected with the main line wire core X1 and the main line wire core X2 in parallel to receive signals from the main end transceiver, and the slave end communication control port is respectively connected with the control ends of the slave end transmitting module and the master and slave end receiving module; the value of n is any integer between 1 and 300.
The further technical scheme is as follows: the main end sending module is an electronic switch circuit and comprises an H-bridge type circuit formed by combining four MOS tubes, the main end communication control port controls the combination of 4 MOS tubes to be switched on or switched off, the function of the double-pole double-throw switch is realized, and therefore a bus generates a bipolar waveform, and the connection relation is as follows:
the drain of the upper left P-channel MOS tube V4 is connected with the drain of the lower left N-channel MOS tube V6 and then is connected with a main line core X1 as an output end, the grid of the upper left P-channel MOS tube V4 is connected with two control ends of a main end communication control port respectively, the drain of the upper right P-channel MOS tube V5 is connected with the drain of the lower right N-channel MOS tube V7 and then is connected with a main line core X2 as another output end, the grid of the upper right P-channel MOS tube V4 is connected with the other two control ends of the main end communication control port respectively, the sources of the MOS tube V4 and the MOS tube V5 are connected with the positive electrode of a rear power supply, and the sources of;
when the voltage of the main line wire core X1 is higher than the voltage of the main line wire core X2, the original code of the bus corresponding to the generated bipolar waveform is 1; when the voltage of the main line wire core X1 is lower than the voltage of the main line wire core X2, the original code corresponding to the generated bipolar waveform is 0;
the main terminal receiving module comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C5, a capacitor C6, a bidirectional current detection chip N2, a bidirectional current detection chip N3, a diode VD5, a diode VD6, an operational amplifier N4A, an operational amplifier N4B, an operational amplifier N4C and an operational amplifier N4D;
the resistor R8 connected in series on the bus is a current sampling resistor, the bidirectional current detection chip N2 and the bidirectional current detection chip N3 are used for analog output and can accurately amplify micro voltage drops at two ends of the current sampling resistor, and the diode VD5, the diode VD6 and the resistor R9 are used for processing signals output by the bidirectional current detection chip N2 and the bidirectional current detection chip N3 into absolute values of proportional voltages; the operational amplifier N4A, the operational amplifier N4B, the operational amplifier N4C and the operational amplifier N4D work in a single power state, and the operational amplifier N4A is in a forward follower connection method and is used for isolating an input signal to avoid influence on the input signal by post-stage processing; a band-pass filter is formed by the capacitor C5, the capacitor C6, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14 and the operational amplifier N4B and is used for filtering out direct-current components and high-frequency interference in input signals, a slowly-falling pulse response waveform is obtained after current pulse signals are subjected to band-pass filtering, then the slowly-falling pulse response waveform is sent to the operational amplifier N4C connected with a comparator, and is compared with a threshold reference value and then output to a processor of a main-end communication control port for capturing and identifying;
the resistor R15 and the resistor R16 are used for dividing voltage to obtain a voltage, and the voltage is connected into the operational amplifier N4C as the threshold reference voltage of the comparator after passing through the operational amplifier N4D connected by the forward follower, so that the interference and the burr with smaller amplitude in the pulse signal are removed; and finally, the output waveform is sent to an I/O pin of a communication control port of the main terminal for pulse capture directly, and can also be sent to a trigger circuit for further shaping to form a standard digital signal waveform for receiving by a controller module.
Further: the slave power supply module comprises a rectifier bridge circuit consisting of a rectifier diode VD1, a rectifier diode VD1, a rectifier diode VD2, a rectifier diode VD3 and a rectifier diode VD4, wherein the input end of the rectifier bridge circuit is connected with the 12V voltage of a bus, the output of the rectifier bridge is changed into a +5V power supply through a three-port voltage stabilizer N1 to supply power to a slave transceiver, a capacitor C1 is a power supply input filter capacitor, and a capacitor C2 is a power supply output filter capacitor;
the rectifier bridge circuit and the 2 MOS tube circuits form a slave receiving module, the 2 MOS tube circuits comprise an MOS tube V1 and an MOS tube V2, gates of the MOS tube V1 and the MOS tube V2 are respectively connected with a bus through a resistor R3 and a resistor R4, one output end of the rectifier bridge circuit is respectively connected with sources of the MOS tube V1 and the MOS tube V2 and grounded, the other output end of the rectifier bridge circuit is respectively connected with drains of the MOS tube V1 and the MOS tube V2 through a resistor R1 and a resistor R5, drains of the MOS tube V1 and the MOS tube V2 are respectively connected with a terminal 'Rec 1' and a terminal 'Rec 2' of a slave communication control port, and therefore the drains and the sources of the MOS tube V1 and the MOS tube V2 form two groups of output ends to output a pair of differential;
the rectifier bridge circuit and the 1 MOS tube circuit form a slave end sending module which comprises an MOS tube V3, one output end of the rectifier bridge circuit is connected with the source electrode of the MOS tube V3 and grounded, the other output end of the rectifier bridge circuit is connected with the drain electrode of the MOS tube V3 through a resistor R7, and the grid electrode and the source electrode of the MOS tube V3 form an output end to output current pulses.
And further: the model of the bidirectional current detection chip N2 and the model of the bidirectional current detection chip N3 are INA199A 2; the operational amplifier N4A, operational amplifier N4B, operational amplifier N4C, and operational amplifier N4D are rail-to-rail operational amplifiers.
Due to the adoption of the technical scheme, compared with the prior art, the master-slave bus type bipolar waveform power carrier communication has the following beneficial effects:
(1) the communication scheme is a master-slave bus type bipolar waveform power carrier communication based on low-voltage direct current input, and provides a better communication scheme for some special application scenes, such as electronic detonator networking and micro-sensor networking, a master-end transceiver of the communication scheme can be simultaneously connected with a plurality of slave-end transceivers through a bus to carry out bidirectional communication and supply power for the slave-end transceivers, and the slave-end transceivers have the thin characteristics of small volume, simple structure, easy integration and low cost, and are particularly suitable for consumable application scenes such as electronic detonators, or the arrangement of a large number of micro-sensors and the arrangement and application of a low-voltage controllable LED lighting network;
(2) according to the communication scheme, the master transceiver sends information to the slave transceiver, so that differential signal sending can be realized, the anti-interference capability is high, the reliability is high, the transmission distance is long, the number of current pulses used for returning signals from the slave transceiver to the master transceiver is small, the heating is low, and the continuous sending capability is good;
(3) the communication scheme does not use large-volume filtering frequency division elements such as inductance and capacitance which are difficult to integrate by chips, has simple structure and small volume, is easy to realize chip integration, and has simple structure and low cost of a slave-end hardware circuit;
(4) the communication scheme has good flexibility and expansibility, and can further improve the communication reliability by superposing other coding modes or using digital frequency modulation on the original basis in a software or hardware mode.
The technical features of a master-slave bus type bipolar waveform power carrier communication according to the present invention will be further described with reference to the accompanying drawings and embodiments.
Drawings
Fig. 1-2 are schematic diagrams of a master-slave bus type bipolar waveform power carrier communication structure according to the present invention;
FIG. 1 is a general connection diagram, and FIG. 2 is a block diagram;
FIG. 3 is a circuit diagram of a slave transceiver;
FIG. 4 is a circuit diagram of a master transceiver;
fig. 5 to 6 are circuit diagrams of the master transmission module (electronic switch circuit):
FIG. 5 is a first state, and FIG. 6 is a second state;
FIG. 7 is a schematic diagram of bus generation of bipolar waveform and original code comparison;
FIG. 8 is a circuit diagram of a slave receive module;
FIG. 9 is a circuit diagram of the slave side supply;
FIG. 10 is a circuit diagram of a slave transmit module;
FIG. 11 is a schematic diagram of the current pulse output from the slave sending module;
in the figure:
1-master end transceiver, 2-slave end transceiver, 11-master end communication control port, 12-master end sending module, 13-master end receiving module, 21-slave end communication control port, 22-slave end sending module, 23-slave end receiving module and 24-power module.
Detailed Description
A master-slave bus type bipolar waveform power carrier communication comprises a master end transceiver 1 and n slave end transceivers, wherein the n slave end transceivers are connected with the master end transceiver in parallel through a two-wire system bus;
the main-end transceiver comprises a main-end communication control port 11, a main-end sending module 12 and a main-end receiving module 13, wherein one output end of the main-end sending module is connected with the input end of the main-end receiving module, the other output end of the main-end sending module is connected with a main-line wire core X1 of a bus, the output end of the main-end receiving module is connected with a main-line wire core X2 of the bus, and the main-end communication control port is respectively connected with the control ends of the main-end sending module 12 and the main-end receiving;
the n slave end transceivers have the same structure and comprise a slave end communication control port 21, a slave end transmitting module 22, a slave end receiving module 23 and a power module 24, wherein the input end of the power module 24 is connected with a main line wire core X1 and a main line wire core X2 in parallel to obtain electric energy, and the output end of the power module 24 is respectively connected with the slave end communication control port 21, the slave end transmitting module 22 and the slave end receiving module 23 to provide working power for the slave end communication control port 21, the slave end transmitting module 22 and the slave end receiving module 23; the input end of the slave receiving module 23 receives signals from the master transceiver in parallel with the master cable core X1 and the master cable core X2, and the slave communication control port is connected to the control ends of the slave transmitting module 22 and the slave receiving module 23, respectively.
The value of n is any integer between 1 and 300.
The master sending module 12 is an electronic switch circuit, and includes an H-bridge type circuit composed of four MOS tubes, and controls the on/off of the 4 MOS tubes through a master communication control port, so as to implement the function of a double-pole double-throw switch, and thus the bus generates a bipolar waveform, and the connection relationship is as follows:
the drain of the upper left P-channel MOS transistor V4 is connected to the drain of the lower left N-channel MOS transistor V6 and then connected to the main line core X1 as an output, the gate thereof is connected to two control ends of the main communication control port 11, the drain of the upper right P-channel MOS transistor V5 is connected to the drain of the lower right N-channel MOS transistor V7 and then connected to the main line core X2 as another output, the gate thereof is connected to the other two control ends of the main communication control port 11, the sources of the MOS transistor V4 and the MOS transistor V5 are connected to the positive electrode of the power supply, and the sources of the MOS transistor V5 and the MOS transistor V7 are connected and then grounded (see fig. 5-6);
when the voltage of the main line wire core X1 is higher than the voltage of the main line wire core X2, the original code of the bus corresponding to the generated bipolar waveform is 1, and when the voltage of the main line wire core X1 is lower than the voltage of the main line wire core X2, the original code corresponding to the generated bipolar waveform is 0;
bus generated bipolar waveforms against the original code see fig. 7: the curve "voltage of the main line wire core X1" and "voltage of the main line wire core X2" represent voltage changes of two branch wires of the main line, and "A" represents a voltage amplitude of the bus, namely, voltage of a direct current power supply supplying power to the main line;
the main terminal receiving module 13 comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C5, a capacitor C6, a bidirectional current detection chip N2, a bidirectional current detection chip N3, a diode VD5, a diode VD6, an operational amplifier N4A, an operational amplifier N4B, an operational amplifier N4C and an operational amplifier N4D;
the resistor R8 connected in series on the bus is a current sampling resistor, the bidirectional current detection chip N2 and the bidirectional current detection chip N3 are used for analog output and can accurately amplify micro voltage drops at two ends of the current sampling resistor, and the diode VD5, the diode VD6 and the resistor R9 are used for processing signals output by the bidirectional current detection chip N2 and the bidirectional current detection chip N3 into absolute values of proportional voltages; the operational amplifier N4A, the operational amplifier N4B, the operational amplifier N4C and the operational amplifier N4D work in a single power state, and the operational amplifier N4A is in a forward follower connection method and is used for isolating an input signal to avoid influence on the input signal by post-stage processing; a band-pass filter is formed by the capacitor C5, the capacitor C6, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14 and the operational amplifier N4B and is used for filtering out direct-current components and high-frequency interference in input signals, a slowly-falling pulse response waveform is obtained after current pulse signals are subjected to band-pass filtering, then the slowly-falling pulse response waveform is sent to the operational amplifier N4C connected with a comparator, and is compared with a threshold reference value and then output to a processor of a main-end communication control port for capturing and identifying;
the resistor R15 and the resistor R16 are used for dividing voltage to obtain a voltage, and the voltage is connected into the operational amplifier N4C as the threshold reference voltage of the comparator after passing through the operational amplifier N4D connected by the forward follower, so that the interference and the burr with smaller amplitude in the pulse signal are removed; and shaping the signal into a standard digital signal waveform for receiving by the controller module.
The power module 24 at the slave end comprises a rectifier bridge circuit consisting of a rectifier diode VD1, a rectifier diode VD1, a rectifier diode VD2, a rectifier diode VD3 and a rectifier diode VD4, wherein the input end of the rectifier bridge circuit is connected with the 12V voltage of the bus, the output of the rectifier bridge is changed into a +5V power supply through a three-port voltage stabilizer N1 to supply power to a slave end transceiver, a capacitor C1 is a power supply input filter capacitor, and a capacitor C2 is a power supply output filter capacitor (see the attached figure 8);
the rectifier bridge circuit and the 2 MOS transistor circuits form a slave receiving module 23, the 2 MOS transistor circuits include a MOS transistor V1 and a MOS transistor V2, gates of the MOS transistor V1 and the MOS transistor V2 are connected to the bus through a resistor R3 and a resistor R4, respectively, one output end of the rectifier bridge circuit is connected to the sources of the MOS transistor V1 and the MOS transistor V2 and grounded, the other output end is connected to the drains of the MOS transistor V1 and the MOS transistor V2 through a resistor R1 and a resistor R5, and drains of the MOS transistor V1 and the MOS transistor V2 are connected to a terminal "Rec 1" and a terminal "Rec 2" of the slave communication control port, respectively, so that the drains and the sources of the MOS transistor V1 and the MOS transistor V2 form two sets of output ends to output a pair of differential waveform signals (see fig. 9;
the rectifier bridge circuit and 1 MOS transistor circuit form a slave side sending module 22, which includes a MOS transistor V3, one output terminal of the rectifier bridge circuit is connected to the source of the MOS transistor V3 and grounded, the other output terminal is connected to the drain of the MOS transistor V3 through a resistor R7, and the gate and the source of the MOS transistor V3 form an output terminal output current pulse (see fig. 10).
The model of the bidirectional current detection chip N2 and the model of the bidirectional current detection chip N3 are INA199A 2; the operational amplifier N4A, operational amplifier N4B, operational amplifier N4C, and operational amplifier N4D are rail-to-rail operational amplifiers.
An optimized implementation of the slave receive module and the slave transmit module circuits is as follows:
the output end 'Rec 1', the output end 'Rec 2' and the output end 'Send' are connected with I/O pins of the slave communication control port, wherein the pins connecting the output end 'Rec 1' and the output end 'Rec 2' are in an input state, the pins connecting the output end 'Send' are in an output state, and a low level or a high resistance state is output under the default condition;
the receiving function mainly depends on an MOS tube V1 and an MOS tube V2, and the sending function is composed of an MOS tube V3 and a resistor R7;
the input resistance of the MOS transistor "V1" and the MOS transistor "V2" is very large, when the voltage of the main line core X1 in the bus is higher than the voltage of the main line core X2, the MOS transistor V1 turns on the MOS transistor V2 to be turned off, the level of the output terminal "Rec 1" connected to the I/O pin of the slave communication control port is pulled low, the level of the output terminal "Rec 2" is pulled high, the slave communication control port can interpret the code element as "1", when the voltage of the main line core X2 is higher than the voltage of the main line core X1, the MOS transistor V2 turns on the MOS transistor V21 to be turned off, the level of the output terminal "Rec 2" connected to the I/O pin of the slave communication control port is pulled low, the level of the output terminal "Rec 1" is pulled high, and the code element can be interpreted by the slave communication;
whether the MOS tube V1 and the MOS tube V2 are switched on or not is switched on near a bus voltage reversal zero crossing point, a hysteresis voltage comparison threshold is provided for voltage zero crossing detection by the resistor R1, the resistor R3, the resistor R4 and the resistor R6, the interference of voltage jitter on the zero crossing detection can be effectively inhibited, a receiving circuit has certain hardware anti-interference capability, when the bus voltage change is in the threshold interval, the output end 'Rec 1' and the output end 'Rec 2' are both in low level, and at the moment, code element interpretation is not carried out;
the return function is realized by controlling the conduction of the MOS tube V3 through a level signal of an output end 'Send', current pulses are produced under the appropriate state of the bus, and the amplitude of the pulses is set by a resistor R7.
This communication theory of operation:
the invention provides a master-slave bus type bipolar waveform power carrier communication scheme based on low-voltage direct current input; the master transceiver uses low-voltage direct current as power input and is connected with a plurality of slave transceivers through a two-wire bus, the slave transceivers can be connected to the bus in a non-polar parallel mode and work by directly obtaining electric power from the bus, the master transceiver can actively control and turn over the voltage polarity on the bus to form a bipolar waveform to represent information and send the information to all the slave transceivers on the wire, and the slave transceivers can receive and interpret the received information and transmit the information back to the master transceiver in a mode of manufacturing bus current pulse marks during a proper bus polarity period according to needs.
Claims (4)
1. A master-slave bus type bipolar waveform power carrier communication is characterized in that: the system comprises a main-end transceiver (1) and n slave-end transceivers (2), wherein the n slave-end transceivers are connected with the main-end transceiver in parallel through a two-wire bus;
the main-end transceiver comprises a main-end communication control port (11), a main-end sending module (12) and a main-end receiving module (13), wherein one output end of the main-end sending module is connected with the input end of the main-end receiving module, the other output end of the main-end sending module is connected with a main-line core X1 of a bus, the output end of the main-end receiving module is connected with a main-line core X2 of the bus, and the main-end communication control port (11) is respectively connected with the control ends of the main-end sending module (12) and the main-end receiving module (;
the n slave end transceivers have the same structure and comprise a slave end communication control port (21), a slave end transmitting module (22), a slave end receiving module (23) and a power supply module (24), wherein the input end of the power supply module is connected with the main line wire core X1 and the main line wire core X2 in parallel to obtain electric energy, and the output end of the power supply module is respectively connected with the slave end communication control port (21), the slave end transmitting module (22) and the slave end receiving module (23) to provide working power supply for the slave end communication control port, the slave end transmitting module (22) and the slave end receiving module (23; the input end of the slave receiving module (23) is connected with a main line core X1 and a main line core X2 in parallel to receive signals from a main transceiver, and the slave communication control port (21) is respectively connected with the control ends of the slave sending module (22) and the slave receiving module (23); the value of n is any integer between 1 and 300.
2. The master-slave bus based bipolar waveform power carrier communication of claim 1, wherein: the main end sending module (12) is an electronic switch circuit, comprises an H-bridge type circuit formed by combining four MOS tubes, controls the combination of 4 MOS tubes to be switched on or switched off through a main end communication control port, realizes the function of a double-pole double-throw switch, and enables a bus to generate a double-pole waveform, and the connection relation is as follows:
the drain of the upper left P-channel MOS tube V4 is connected with the drain of the lower left N-channel MOS tube V6 and then is connected with a main line core X1 as an output end, the grid of the upper left P-channel MOS tube V4 is connected with two control ends of a main end communication control port (11) respectively, the drain of the upper right P-channel MOS tube V5 is connected with the drain of the lower right N-channel MOS tube V7 and then is connected with the main line core X2 as another output end, the grid of the upper right P-channel MOS tube V5 is connected with the other two control ends of the main end communication control port (11) respectively, the sources of the MOS tube V4 and the MOS tube V5 are connected with the anode of a rear power supply, and the sources of the;
when the voltage of the main line wire core X1 is higher than the voltage of the main line wire core X2, the original code of the bus corresponding to the generated bipolar waveform is '1'; when the voltage of the main line wire core X1 is lower than the voltage of the main line wire core X2, the original code corresponding to the generated bipolar waveform is '0';
the main terminal receiving module (13) comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, a capacitor C5, a capacitor C6, a bidirectional current detection chip N2, a bidirectional current detection chip N3, a diode VD5, a diode VD6, an operational amplifier N4A, an operational amplifier N4B, an operational amplifier N4C and an operational amplifier N4D;
the resistor R8 connected in series on the bus is a current sampling resistor, the bidirectional current detection chip N2 and the bidirectional current detection chip N3 are used for analog output and can accurately amplify micro voltage drops at two ends of the current sampling resistor, and the diode VD5, the diode VD6 and the resistor R9 are used for processing signals output by the bidirectional current detection chip N2 and the bidirectional current detection chip N3 into absolute values of proportional voltages; the operational amplifier N4A, the operational amplifier N4B, the operational amplifier N4C and the operational amplifier N4D work in a single power state, and the operational amplifier N4A is in a forward follower connection method and is used for isolating an input signal to avoid influence on the input signal by post-stage processing; a band-pass filter is formed by the capacitor C5, the capacitor C6, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14 and the operational amplifier N4B and is used for filtering out direct-current components and high-frequency interference in input signals, a slowly-falling pulse response waveform is obtained after current pulse signals are subjected to band-pass filtering, then the slowly-falling pulse response waveform is sent to the operational amplifier N4C connected with a comparator, and is compared with a threshold reference value and then output to a processor of a main-end communication control port for capturing and identifying;
the resistor R15 and the resistor R16 are used for dividing voltage to obtain a voltage, and the voltage is connected into the operational amplifier N4C as the threshold reference voltage of the comparator after passing through the operational amplifier N4D connected by the forward follower, so that the interference and the burr with smaller amplitude in the pulse signal are removed; and finally, the output waveform is sent to an I/O pin of a communication control port of the main terminal for pulse capture directly, and can also be sent to a trigger circuit for further shaping to form a standard digital signal waveform for receiving by a controller module.
3. A master-slave bus based bipolar waveform power carrier communication as claimed in claim 2, wherein:
the power module (24) of the slave end comprises a rectifier bridge circuit consisting of a rectifier diode VD1, a rectifier diode VD1, a rectifier diode VD2, a rectifier diode VD3 and a rectifier diode VD4, wherein the input end of the rectifier bridge circuit is connected with the 12V voltage of a bus, the output of the rectifier bridge is changed into a +5V power supply through a three-port voltage stabilizer N1 to supply power to a slave end transceiver, a capacitor C1 is a power input filter capacitor, and a capacitor C2 is a power output filter capacitor;
the rectifier bridge circuit and the 2 MOS tube circuits form a slave receiving module (23), and the slave receiving module comprises an MOS tube V1 and an MOS tube V2, gates of the MOS tube V1 and the MOS tube V2 are respectively connected with a bus through a resistor R3 and a resistor R4, one output end of the rectifier bridge circuit is respectively connected with sources of the MOS tube V1 and the MOS tube V2 and grounded, the other output end of the rectifier bridge circuit is respectively connected with drains of the MOS tube V1 and the MOS tube V2 through a resistor R1 and a resistor R5, drains of the MOS tube V1 and the MOS tube V2 are respectively connected with a terminal 'Rec 1' and a terminal 'Rec 2' of a slave communication control port, and therefore the drains and the sources of the MOS tube V1 and the MOS tube V2 form two groups of output ends for;
the rectifier bridge circuit and the 1 MOS tube circuit form a slave end sending module (22) which comprises an MOS tube V3, one output end of the rectifier bridge circuit is connected with the source electrode of the MOS tube V3 and grounded, the other output end of the rectifier bridge circuit is connected with the drain electrode of the MOS tube V3 through a resistor R7, and the grid electrode and the source electrode of the MOS tube V3 form an output end to output current pulses.
4. A master-slave bus based bipolar waveform power carrier communication as claimed in claim 2, wherein: the model of the bidirectional current detection chip N2 and the model of the bidirectional current detection chip N3 are INA199A 2; the operational amplifier N4A, operational amplifier N4B, operational amplifier N4C, and operational amplifier N4D are rail-to-rail operational amplifiers.
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