CN205647542U - Two net gape supply circuit - Google Patents
Two net gape supply circuit Download PDFInfo
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- CN205647542U CN205647542U CN201620391621.1U CN201620391621U CN205647542U CN 205647542 U CN205647542 U CN 205647542U CN 201620391621 U CN201620391621 U CN 201620391621U CN 205647542 U CN205647542 U CN 205647542U
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Abstract
The utility model provides a two net gape supply circuit, include: a second net gape, a MOS pipe, the 2nd MOS pipe and load resistance for receiving come from a PSE's first power first net gape, be used for receiving the second source that comes from the 2nd PSE, the first end of first net gape with load resistance's first end is connected, the second of first net gape end with the D of MOS pipe extremely connects, the first end of second net gape with load resistance's first end is connected, the second of second net gape end with the D of the 2nd MOS pipe extremely connects, the S utmost point of MOS pipe with load resistance's second end is connected, the S utmost point of the 2nd MOS pipe with load resistance's second end is connected, load resistance's second end is not held for ground. Through the technical scheme of the utility model, the power of consumption on the MOS pipe is very low, can be similar to to 0 to the power consumption on the route can be effectively reduced, power efficiency is effectively promoted.
Description
Technical field
This utility model relates to circuit engineering field, particularly relates to a kind of double network interface power supply circuits.
Background technology
PoE (Power Over Ethernet, active Ethernet) powering refers to: in the case of Ethernet wiring architecture does not makes any changes, while for IP-based wireless terminal device (such as IP telephone machine, wireless local network connecting point, web camera etc.) transmission data, moreover it is possible to the technology of direct current supply is provided for this wireless terminal device.PoE electric power system includes PSE (Power Sourcing Equipment, feeder ear equipment) and PD (Powered Device, receiving end equipment) two parts, PSE is the equipment powered for wireless terminal device, such as switch etc., and PD is the wireless terminal device accepting power supply.
Along with the development of PoE power supply technique, in PoE power supply technique, the power supply scene shown in Fig. 1 and the power supply scene shown in Fig. 2 can be used.In fig. 1 and 2, netting twine 1 is identical with the effect of netting twine 2, and netting twine 1 while data, is also powered for PD between transmission PSE1 and PD, and netting twine 2 while data, is also powered for PD between transmission PSE2 and PD, thus the PoE realizing double netting twine powers.
As shown in Figure 3, in the PoE power supply technique of double netting twines, two PD control chips are included in PD, the power supply that PSE1 provides is exported to diode D1 by PD control chip 1, the power supply that PSE2 provides is exported to diode D2 by PD control chip 2, so, the power supply from PSE1 exports to load resistance R after diode D1L, the power supply from PSE2 exports to load resistance R after diode D2L。
Due to diode D1 and diode D2, all to there is inherent voltage poor, even if the Schottky diode that forward conduction voltage drop is minimum, the inherent voltage that there is also about 0.8V is poor, therefore, is being exported power supply to load resistance R by diode D1/ diode D2LTime, consume the power on diode D1/ diode D2 the highest, such as the highest 0.48W that can reach, therefore, loss power on the diode is bigger.
Utility model content
This utility model provides a kind of double network interface power supply circuits, including: for receiving the first network interface of the first power supply from a PSE, for receiving the second network interface of second source, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and load resistance from the 2nd PSE；First end of described first network interface is connected with the first end of described load resistance, and the second end of described first network interface is connected with the D pole of described first metal-oxide-semiconductor；First end of described second network interface is connected with the first end of described load resistance, and the second end of described second network interface is connected with the D pole of described second metal-oxide-semiconductor；The S pole of described first metal-oxide-semiconductor is connected with the second end of described load resistance；The S pole of described second metal-oxide-semiconductor is connected with the second end of described load resistance.
Based on technique scheme, in this utility model embodiment, by using MOS (Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) pipe realizes the PoE of double netting twine and powers, owing to metal-oxide-semiconductor has good switch handoff functionality, when metal-oxide-semiconductor is in the conduction state, this metal-oxide-semiconductor is equivalent to short circuit.Therefore, when metal-oxide-semiconductor is in the conduction state, the conduction voltage drop in this metal-oxide-semiconductor can be approximated to be 0, i.e. consume the power on metal-oxide-semiconductor the lowest, can be approximated to be 0, such that it is able to effectively reduce the power attenuation on path, the power of loss is negligible, thus effectively promotes power-efficient.
Accompanying drawing explanation
In order to this utility model embodiment or technical scheme of the prior art are clearly described, the accompanying drawing used required in this utility model embodiment or description of the prior art will be briefly described below, apparently, accompanying drawing in describing below is only some embodiments described in this utility model, for those of ordinary skill in the art, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 and Fig. 2 is the power supply scene schematic diagram in PoE power supply technique；
Fig. 3 is the power supply scene schematic diagram of the PoE power supply technique of double netting twine；
Fig. 4 is the schematic diagram of the double network interface power supply circuits in this utility model embodiment；
Fig. 5 is the schematic diagram being powered PD by line sequence 1, line sequence 2, line sequence 3, line sequence 6 in this utility model embodiment；
Fig. 6 is the schematic diagram being powered PD by line sequence 4, line sequence 5, line sequence 7, line sequence 8 in this utility model embodiment；
Fig. 7 is the schematic diagram of the metal-oxide-semiconductor having parasitic diode in this utility model embodiment；
Fig. 8-Figure 11 is the schematic diagram of the double network interface power supply circuits in this utility model embodiment；
Figure 12 is the schematic diagram of the first control circuit in this utility model embodiment；
Figure 13 is the schematic diagram of the second control circuit in this utility model embodiment；
Figure 14 is the schematic diagram of the not gate electronic circuit in this utility model embodiment；
Figure 15 is the schematic diagram of the first control circuit in this utility model embodiment；
Figure 16 is the schematic diagram of the second control circuit in this utility model embodiment.
Detailed description of the invention
The term used at this utility model merely for the sake of describing the purpose of specific embodiment, and unrestricted this utility model." a kind of ", " described " and " being somebody's turn to do " of singulative used in this utility model and claims is also intended to include most form, unless context clearly shows that other implication.It is also understood that term "and/or" used herein refers to comprise any or all possible combination of one or more project of listing being associated.Although should be appreciated that in this utility model possible employing term first, second, third, etc. to describe various information, but these information should not necessarily be limited by these terms.These terms are only used for same type of information is distinguished from each other out.Such as, in the case of without departing from this utility model scope, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information, depends on linguistic context.
For problems of the prior art, proposing a kind of double network interface power supply circuits in this utility model embodiment, this pair of network interface power supply circuits are applied on PD, and for the device needing power supply in PD is powered.In double network interface power supply circuits, the device needing power supply can be equivalent to load resistance R in PDL, this load resistance RLFor equivalent resistance, therefore, this pair of network interface power supply circuits are for load resistance RLIt is powered.
As shown in Figure 4, this pair of network interface power supply circuits include: the first network interface, the second network interface, a MOS (Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) pipe, the second metal-oxide-semiconductor and load resistance RL.First end of the first network interface and load resistance RLThe first end connect, the D pole connection of the second end of the first network interface and the first metal-oxide-semiconductor；First end of the second network interface and load resistance RLThe first end connect, the D pole connection of the second end of the second network interface and the second metal-oxide-semiconductor；The S pole of the first metal-oxide-semiconductor is connected with the second end of load resistance；The S pole of the second metal-oxide-semiconductor is connected with the second end of load resistance.
Wherein, the first network interface is for receiving the first power supply from a PSE, and the second network interface is for receiving the second source from the 2nd PSE.In fig. 1 and 2, the first network interface connects PSE1 by netting twine 1, and to receive the first power supply from PSE1, the second network interface connects PSE2 by netting twine 2, to receive the second source from PSE2.The PoE that can be realized double netting twine by the first network interface and the second network interface is powered.
In one example, during PD is powered by PSE by netting twine, owing to 8 line sequence can be comprised in netting twine, it is respectively line sequence 1, line sequence 2, line sequence 3, line sequence 4, line sequence 5, line sequence 6, line sequence 7, line sequence 8, therefore, PD can be powered by PSE by line sequence 1, line sequence 2, line sequence 3, line sequence 6, it is also possible to is powered PD by line sequence 4, line sequence 5, line sequence 7, line sequence 8.
As it is shown in figure 5, be schematic diagram PD being powered by line sequence 1, line sequence 2, line sequence 3, line sequence 6.Illustrate as a example by the power supply process of PSE1, line sequence 1,2 link can be formed positive pole, and it is input to the first end of the first network interface, now, first end of the first network interface is anode, line sequence 3,6 link is formed negative pole, and is input to the second end of the first network interface, now, the second end of the first network interface is negative terminal.
As shown in Figure 6, for schematic diagram PD being powered by line sequence 4, line sequence 5, line sequence 7, line sequence 8.Illustrate as a example by the power supply process of PSE1, line sequence 4,5 link can be formed positive pole, and it is input to the first end of the first network interface, now, first end of the first network interface is anode, line sequence 7,8 link is formed negative pole, and is input to the second end of the first network interface, now, the second end of the first network interface is negative terminal.
In actual use, netting twine and the netting twine of 100M optical fiber for 10M optical fiber, use 4 line sequence just can meet the needs of data transmission, therefore, line sequence 1, line sequence 2, line sequence 3, line sequence 6 is generally used to transmit data, and line sequence 4, line sequence 5, line sequence 7, line sequence 8 do not transmit data, it is in idle condition.Based on this, can power in the way of using shown in Fig. 5, or the mode shown in Fig. 6 of employing is powered.In fig. 5 and fig., line sequence 1, line sequence 2 are referred to as a DATA PAIR (data to), line sequence 3, line sequence 6 are referred to as a DATA PAIR.In figure 6, line sequence 4, line sequence 5 are referred to as a SPARE PAIR (idle to), line sequence 7, line sequence 8 are referred to as a SPARE PAIR.
Netting twine for 1000M optical fiber, generally use 8 line sequence just can meet the needs of data transmission, therefore, use line sequence 1, line sequence 2, line sequence 3, line sequence 6, line sequence 4, line sequence 5, line sequence 7, line sequence 8 to transmit data, now only have DATA PAIR, and there is no SPARE PAIR.Based on this, can power in the way of using shown in Fig. 5, line sequence 1, line sequence 2 are referred to as a DATA PAIR, line sequence 3, line sequence 6 are referred to as a DATA PAIR, line sequence 4, line sequence 5 are referred to as a DATA PAIR, line sequence 7, line sequence 8 are referred to as a DATA PAIR, the most only depict line sequence 1, line sequence 2, line sequence 3, line sequence 6.
Two examples that PD is simply powered by Fig. 5 and Fig. 6; all modes that PD is powered by PSE are all within this utility model protection domain; as long as the first network interface is able to receive that the first power supply from a PSE, the second network interface are able to receive that the second source from the 2nd PSE.In subsequent process, with the first end of the first network interface as anode, the second end is negative terminal, and the first end of the second network interface is anode, and the second end is to illustrate as a example by negative terminal.Certainly, the first end of the first network interface is negative terminal, and the second end is anode, and the first end of the second network interface is negative terminal, and the second end is that the processing procedure of anode is similar to, and follow-up repeats no more.
Metal-oxide-semiconductor generally comprises D pole (drain, i.e. drain electrode), S pole (source, i.e. source electrode), G pole (gate, i.e. grid), a D pole switch similar with S of metal-oxide-semiconductor, when D pole is opened with S pole, then metal-oxide-semiconductor is in cut-off state, and this metal-oxide-semiconductor is equivalent to open circuit, when D pole closes with S pole, then metal-oxide-semiconductor is in the conduction state, and this metal-oxide-semiconductor is equivalent to short circuit, so that metal-oxide-semiconductor has good switch handoff functionality.In actual applications, can also have parasitic diode in metal-oxide-semiconductor, this parasitic diode is connected in parallel between D pole and S pole, as it is shown in fig. 7, be the schematic diagram of the metal-oxide-semiconductor having parasitic diode.Based on this, when D pole is opened with S pole, then metal-oxide-semiconductor is in cut-off state, and this metal-oxide-semiconductor can be operated under parasitic diode.When D pole closes with S pole, then metal-oxide-semiconductor is in the conduction state, and this metal-oxide-semiconductor is equivalent to short circuit.In this utility model embodiment, metal-oxide-semiconductor is in cut-off state and refers to open between D pole and S pole, and metal-oxide-semiconductor in the conduction state referring to closes between D pole and S pole.
Operation principle based on metal-oxide-semiconductor, when receiving the first power supply by the first network interface, now, the first metal-oxide-semiconductor is in cut-off state, then, when being powered load resistance by described first power supply, electric current is through the parasitic diode within the first metal-oxide-semiconductor；If the first metal-oxide-semiconductor is in the conduction state, then current when being powered load resistance by described first power supply, electric current is through the first metal-oxide-semiconductor, by the circuit between D pole and S pole.The process being received second source by the second network interface is similar, does not repeats them here.
When the first metal-oxide-semiconductor is in cut-off state, form loop between parasitic diode within the first end of the first network interface, load resistance, the first metal-oxide-semiconductor, the second end of the first network interface, load resistance to be powered by the first power supply.When the first metal-oxide-semiconductor is in the conduction state, D pole within the first end of the first network interface, load resistance, the first metal-oxide-semiconductor and S pole, the first network interface the second end between form loop, load resistance to be powered by the first power supply.The power supply of the second metal-oxide-semiconductor is similar, does not repeats them here.
In this utility model embodiment, as shown in Figure 8, this pair of network interface power supply circuits also include a PD control chip and the 2nd PD control chip.Wherein, the first end of a PD control chip can be connected with the first end of the first network interface, and the second end of a PD control chip can be connected with the first end of load resistance, and turns between the first end of a PD control chip and the second end of a PD control chip.3rd end of the oneth PD control chip can be connected with the second end of the first network interface, 4th end of the oneth PD control chip can be connected with the D pole of the first metal-oxide-semiconductor, and also includes the 3rd metal-oxide-semiconductor between the 3rd end and the 4th end of a PD control chip of a PD control chip.Additionally, the first end of the 2nd PD control chip can be connected with the first end of the second network interface, the second end of the 2nd PD control chip can be connected with the first end of load resistance, and turns between the first end of the 2nd PD control chip and the second end of the 2nd PD control chip.3rd end of the 2nd PD control chip can be connected with the second end of the second network interface, 4th end of the 2nd PD control chip can be connected with the D pole of the second metal-oxide-semiconductor, and also includes the 4th metal-oxide-semiconductor between the 3rd end and the 4th end of the 2nd PD control chip of the 2nd PD control chip.
As shown in Figure 8, under initial situation, the 3rd metal-oxide-semiconductor in a PD control chip is in cut-off state.When inserting netting twine at the first network interface, the first network interface receives the power supply of the first power supply, and a PD control chip can be according to preset strategy, it may be judged whether be powered load resistance, and this judge process does not repeats them here.If be not powered load resistance, then a PD control chip keeps the 3rd metal-oxide-semiconductor to be in cut-off state.If load resistance is powered, then PD control chip control the 3rd metal-oxide-semiconductor is in the conduction state, between first end and second end of such PD control chip in the conduction state, between 3rd end and the 4th end in the conduction state, therefore, be equivalent to a PD control chip and be in short-circuit condition.
As shown in Figure 8, under initial situation, the 4th metal-oxide-semiconductor in the 2nd PD control chip is in cut-off state.When inserting netting twine at the second network interface, the second network interface receives the power supply of second source, and the 2nd PD control chip can be according to preset strategy, it may be judged whether be powered load resistance, and this judge process does not repeats them here.If be not powered load resistance, then the 2nd PD control chip keeps the 4th metal-oxide-semiconductor to be in cut-off state.If load resistance is powered, then the 2nd PD control chip control the 4th metal-oxide-semiconductor is in the conduction state, between first end and second end of such 2nd PD control chip in the conduction state, between 3rd end and the 4th end in the conduction state, therefore, be equivalent to the 2nd PD control chip and be in short-circuit condition.
In this utility model embodiment, as it is shown in figure 9, this pair of network interface power supply circuits also include: the first electric capacity and the second electric capacity.First end (not shown in FIG.) of the first electric capacity is connected with the second end of a PD control chip, and second end (not shown in FIG.) of the first electric capacity is connected with the 4th end of a PD control chip.First end (not shown in FIG.) of the second electric capacity is connected with the second end of the 2nd PD control chip, and second end (not shown in FIG.) of the second electric capacity is connected with the 4th end of the 2nd PD control chip.
Wherein, the first electric capacity and the second electric capacity are used for carrying out discharge and recharge process.Such as, when powering load resistance, being charged, when stopping powering load resistance, discharge, this process repeats no more.
Control opportunity for the conduction and cut-off of the first metal-oxide-semiconductor, and the second control opportunity of conduction and cut-off of metal-oxide-semiconductor, can be in the way of using cross-over control, in the conduction state or the cut-off state by first Control of Voltage the second metal-oxide-semiconductor between D pole and the S pole of the first metal-oxide-semiconductor, and controlled by the tertiary voltage between D pole and the S pole of the second metal-oxide-semiconductor that the first metal-oxide-semiconductor is in the conduction state or cut-off state.
On this basis, in this utility model embodiment, as shown in Figure 10, this pair of network interface power supply circuits also include: first control circuit and second control circuit.Wherein, Figure 10 is on the basis of the double network interface power supply circuits shown in Fig. 4, increases first control circuit and the schematic diagram of second control circuit.It is of course also possible on the basis of the double network interface power supply circuits shown in Fig. 8 or Fig. 9, increasing first control circuit and second control circuit, its processing procedure is similar with the processing procedure of Figure 10, follow-up illustrates as a example by Figure 10.
The D pole of the first metal-oxide-semiconductor is connected with the first input end of first control circuit, and the S pole of the first metal-oxide-semiconductor is connected with the second input of first control circuit；First outfan of first control circuit and the G pole of the second metal-oxide-semiconductor connect, and the second outfan of first control circuit and the S pole of the second metal-oxide-semiconductor connect.The D pole of the second metal-oxide-semiconductor is connected with the first input end of second control circuit, and the S pole of the second metal-oxide-semiconductor is connected with the second input of second control circuit；First outfan of second control circuit and the G pole of the first metal-oxide-semiconductor connect, and the second outfan of second control circuit and the S pole of the first metal-oxide-semiconductor connect.Wherein, when the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is less than preset first threshold value, then the second voltage between the first outfan and second outfan of first control circuit is low level, and ensures that the second metal-oxide-semiconductor is in cut-off state.When the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is more than or equal to preset first threshold value, then the second voltage between the first outfan and second outfan of first control circuit is high level, and ensures that the second metal-oxide-semiconductor is in the conduction state.Tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is less than when presetting Second Threshold, then the 4th voltage between the first outfan and second outfan of second control circuit is low level, and ensures that the first metal-oxide-semiconductor is in cut-off state.Tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is more than or equal to when presetting Second Threshold, then the 4th voltage between the first outfan and second outfan of second control circuit is high level, and ensures that the first metal-oxide-semiconductor is in the conduction state.
In order to make PD know, which PSE current provides power supply for this PD, then the double network interface power supply circuits shown in Figure 11, i.e. the 3rd outfan of first control circuit can also be used to be connected with the first input end of observation circuit；3rd outfan of second control circuit is connected with the second input of observation circuit.
In one example, this observation circuit specifically can include but not limited to central processing unit.
Wherein, when the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is less than preset first threshold value, then the 3rd outfan output logic low of first control circuit；When the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is more than or equal to preset first threshold value, then the 3rd outfan output logic high of first control circuit.Tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is less than when presetting Second Threshold, then the 3rd outfan of second control circuit exports logic low；Tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is for more than or equal to when presetting Second Threshold, then the 3rd outfan of second control circuit exports logic high.
When the first input end of observation circuit receives logic high, and when the second input of observation circuit receives logic low, then it represents that currently by second source, load resistance is powered.When the first input end of observation circuit receives logic low, and when the second input of observation circuit receives logic high, then it represents that currently by the first power supply, load resistance is powered.When the first input end of observation circuit receives logic low, and when the second input of observation circuit receives logic low, then it represents that currently by the first power supply and second source, load resistance is powered.
Wherein, preset first threshold value and default Second Threshold all can select according to practical experience.Preset first threshold value can be identical with default Second Threshold, it is also possible to different, and, preset first threshold value and default Second Threshold can be the numerical value more than 0, such as 0.1,0.2 etc., do not repeat them here.
In this utility model embodiment, the resistance when D pole of the first metal-oxide-semiconductor turns on S pole is less than presetting the first numerical value, and the resistance when D pole of the second metal-oxide-semiconductor turns on S pole is less than presetting second value.Wherein, presetting the first numerical value can be identical with default second value, it is also possible to different, presets the first numerical value and default second value is the numerical value slightly larger than 0, such as 0.1,0.2 etc..Under normal conditions, the resistance when D pole of the first metal-oxide-semiconductor turns on S pole is approximately 0, and the resistance when D pole of the second metal-oxide-semiconductor turns on S pole is approximately 0.Based on this, the conduction voltage drop in the first metal-oxide-semiconductor and the second metal-oxide-semiconductor can be approximated to be 0, or conduction voltage drop can be described in detail less times greater than 0 below in conjunction with two kinds of situations.
The first situation, as a example by the conduction voltage drop in the first metal-oxide-semiconductor and the second metal-oxide-semiconductor is 0.
Application scenarios 1, PD is powered by PSE1, and PD is not powered by PSE2.
The supply voltage assuming PSE1 is 54 volts, and the voltage of the first end of the first network interface is+54 volts, and the voltage of the second end is 0 volt.Owing to the voltage of the voltage of the first end of load resistance and the first end of the first network interface is identical, therefore it is+54 volts.Owing to the voltage of the voltage of D pole of the first metal-oxide-semiconductor and the second end of the first network interface is identical, therefore it is 0 volt.Owing to the conduction voltage drop in the first metal-oxide-semiconductor is 0, therefore the voltage of the D pole of the voltage of the S pole of the first metal-oxide-semiconductor and the first metal-oxide-semiconductor is identical, is 0 volt.Based on this, the first voltage between D pole and the S pole of the first metal-oxide-semiconductor is 0 volt, and 0 volt is less than preset first threshold value.The operation principle of first control circuit is: when the level that input is less than preset first threshold value, it is ensured that be output as low level, when the level that input is more than or equal to preset first threshold value, it is ensured that be output as high level.Therefore, when the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is less than preset first threshold value, the second voltage between the first outfan and second outfan of first control circuit is low level, and the 3rd outfan output logic low of first control circuit.When voltage between the G pole and D pole of the second metal-oxide-semiconductor is low level, the second metal-oxide-semiconductor can be in cut-off state, thus control the second metal-oxide-semiconductor by first control circuit and be in cut-off state.
Owing to the voltage of the voltage of the first end of load resistance and the first end of the second network interface is identical, therefore the voltage of the first end of the second network interface is+54 volts.Owing to PD is not powered by PSE2, therefore the voltage between the first end and second end of the second network interface is 0 volt, and the voltage of the second end of the i.e. second network interface is+54 volts.Owing to the voltage of the voltage of D pole of the second metal-oxide-semiconductor and the second end of the second network interface is identical, therefore it is+54 volts.Due to the voltage of S pole of the second metal-oxide-semiconductor, the voltage of the second end of load resistance, the first metal-oxide-semiconductor the voltage of S pole the most identical, therefore the voltage of the S pole of the second metal-oxide-semiconductor is 0 volt.Tertiary voltage between D pole and the S pole of the second metal-oxide-semiconductor is+54 volts, and+54 volts are more than or equal to presetting Second Threshold.The operation principle of second control circuit is: when the level that input is less than default Second Threshold, it is ensured that be output as low level, when input is for being more than or equal to the level presetting Second Threshold, it is ensured that be output as high level.Therefore, tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is more than or equal to when presetting Second Threshold, the 4th voltage between first outfan and second outfan of second control circuit is high level, the 3rd outfan output logic high of second control circuit.When voltage between the G pole and D pole of the first metal-oxide-semiconductor is high level, the first metal-oxide-semiconductor is in the conduction state, thus it is in the conduction state to control the first metal-oxide-semiconductor by second control circuit.
In these cases, the 3rd outfan output logic low due to first control circuit, 3rd outfan output logic high of second control circuit, therefore, observation circuit can receive logic low by first input end, and receives logic high by the second input, and determine and be currently powered load resistance by the first power supply, the PSE i.e. powered is PSE1 rather than PSE2.
In sum, when PD is powered by PSE1, when PD is not powered by PSE2, then can control the second metal-oxide-semiconductor by first control circuit and be in cut-off state, and it is in the conduction state to control the first metal-oxide-semiconductor by second control circuit, and may determine that the PSE of current power supply is PSE1 rather than PSE2.
Owing to the first metal-oxide-semiconductor is in the conduction state, therefore, the conduction voltage drop in this first metal-oxide-semiconductor can be approximated to be 0, i.e. consumes the power on the first metal-oxide-semiconductor the lowest, can be approximated to be 0.And, owing to now the second metal-oxide-semiconductor is in cut-off state, therefore, electric current when PD is powered by PSE1 is without going past the second metal-oxide-semiconductor, thus ensure that the second metal-oxide-semiconductor will not be burned, when avoiding the second metal-oxide-semiconductor in the conduction state, the second metal-oxide-semiconductor that electric current is caused through the second metal-oxide-semiconductor burns out problem.
Application scenarios 2, PD is all powered by PSE1 and PSE2, and the supply voltage that the supply voltage of PSE1 is more than PSE2, and such as, the supply voltage of PSE1 is 54 volts, and the supply voltage of PSE2 is 48 volts.
Under this application scenarios, the voltage of the first end of the first network interface is+54 volts, and the voltage of the second end is 0 volt.Owing to the voltage of the voltage of the first end of load resistance and the first end of the first network interface is identical, therefore it is+54 volts.Owing to the voltage of the voltage of D pole of the first metal-oxide-semiconductor and the second end of the first network interface is identical, therefore it is 0 volt.Owing to the conduction voltage drop in the first metal-oxide-semiconductor is 0, therefore the voltage of the D pole of the voltage of the S pole of the first metal-oxide-semiconductor and the first metal-oxide-semiconductor is identical, is 0 volt.Based on this, the first voltage between D pole and the S pole of the first metal-oxide-semiconductor is 0 volt, and 0 volt is less than preset first threshold value.When the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is less than preset first threshold value, then the second voltage between the first outfan and second outfan of first control circuit is low level, and the 3rd outfan output logic low of first control circuit.When voltage between the G pole and D pole of the second metal-oxide-semiconductor is low level, then the second metal-oxide-semiconductor can be in cut-off state, thus control the second metal-oxide-semiconductor by first control circuit and be in cut-off state.
Owing to the voltage of the voltage of the first end of load resistance and the first end of the second network interface is identical, therefore the voltage of the first end of the second network interface is+54 volts.Owing to the supply voltage of PSE2 is 48 volts, therefore the voltage between the first end and second end of the second network interface is 48 volts, and the voltage of the second end of the i.e. second network interface is+6 volts.Owing to the voltage of the voltage of D pole of the second metal-oxide-semiconductor and the second end of the second network interface is identical, therefore it is+6 volts.Due to the voltage of S pole of the second metal-oxide-semiconductor, the voltage of the second end of load resistance, the first metal-oxide-semiconductor the voltage of S pole the most identical, therefore the voltage of the S pole of the second metal-oxide-semiconductor is 0 volt.Tertiary voltage between D pole and the S pole of the second metal-oxide-semiconductor is+6 volts, and+6 volts are more than or equal to presetting Second Threshold.Tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is more than or equal to when presetting Second Threshold, and the 4th voltage between the first outfan and second outfan of second control circuit is high level, and the 3rd outfan output logic high of second control circuit.When voltage between the G pole and D pole of the first metal-oxide-semiconductor is high level, the first metal-oxide-semiconductor can be in the conduction state, controls the first metal-oxide-semiconductor by second control circuit in the conduction state.
In these cases, the 3rd outfan output logic low due to first control circuit, 3rd outfan output logic high of second control circuit, therefore, observation circuit can receive logic low by first input end, and receives logic high by the second input, and determine and be currently powered load resistance by the first power supply, the PSE i.e. powered is PSE1 rather than PSE2.Therefore, when PD is all powered by PSE1 and PSE2, if the supply voltage of PSE1 is different with the supply voltage of PSE2, it practice, can be only that load resistance is powered by the PSE that supply voltage is big.
In sum, when PD is powered by PSE1, when PD is powered by PSE2, then can control the second metal-oxide-semiconductor by first control circuit and be in cut-off state, and it is in the conduction state to control the first metal-oxide-semiconductor by second control circuit, and may determine that the PSE of current power supply is PSE1 rather than PSE2.
Owing to the first metal-oxide-semiconductor is in the conduction state, therefore, the conduction voltage drop in this first metal-oxide-semiconductor can be approximated to be 0, i.e. consumes the power on the first metal-oxide-semiconductor the lowest, can be approximated to be 0.And, owing to now the second metal-oxide-semiconductor is in cut-off state, therefore, electric current when PD is powered by PSE1 is without going past the second metal-oxide-semiconductor, thus ensure that the second metal-oxide-semiconductor will not be burned, when avoiding the second metal-oxide-semiconductor in the conduction state, the second metal-oxide-semiconductor that electric current is caused through the second metal-oxide-semiconductor burns out problem.
Owing to the voltage of the S pole of the second metal-oxide-semiconductor is 0 volt, the voltage of the D pole of the second metal-oxide-semiconductor is 6 volts, therefore, although there is parasitic diode in the second metal-oxide-semiconductor, but the voltage due to S pole is less than the voltage of D pole, therefore cannot the parasitic diode in the first end of the second network interface, load resistance, the second metal-oxide-semiconductor, the second network interface the second end between formed current loop, i.e. electric current the most just load resistance cannot be powered without going past the second metal-oxide-semiconductor, the second source from PSE2.
Application scenarios 3, PD is all powered by PSE1 and PSE2, and the supply voltage that the supply voltage of PSE1 is equal to PSE2, and such as, the supply voltage of PSE1 is 54 volts, and the supply voltage of PSE2 is 54 volts.
Under this application scenarios, the voltage of the first end of the first network interface is+54 volts, and the voltage of the second end is 0 volt.Owing to the voltage of the voltage of the first end of load resistance and the first end of the first network interface is identical, therefore it is+54 volts.Owing to the voltage of the voltage of D pole of the first metal-oxide-semiconductor and the second end of the first network interface is identical, therefore it is 0 volt.Owing to the conduction voltage drop in the first metal-oxide-semiconductor is 0, therefore the voltage of the D pole of the voltage of the S pole of the first metal-oxide-semiconductor and the first metal-oxide-semiconductor is identical, is 0 volt.Based on this, the first voltage between D pole and the S pole of the first metal-oxide-semiconductor is 0 volt, and 0 volt is less than preset first threshold value.When the first voltage between the D pole and S pole of the first metal-oxide-semiconductor is less than preset first threshold value, then the second voltage between the first outfan and second outfan of first control circuit is low level, and the 3rd outfan output logic low of first control circuit.When voltage between the G pole and D pole of the second metal-oxide-semiconductor is low level, then the second metal-oxide-semiconductor can be in cut-off state, thus control the second metal-oxide-semiconductor by first control circuit and be in cut-off state.
Owing to the voltage of the voltage of the first end of load resistance and the first end of the second network interface is identical, therefore the voltage of the first end of the second network interface is+54 volts.Owing to the supply voltage of PSE2 is 54 volts, therefore the voltage between the first end and second end of the second network interface is 54 volts, and the voltage of the second end of the i.e. second network interface is 0 volt.Owing to the voltage of the voltage of D pole of the second metal-oxide-semiconductor and the second end of the second network interface is identical, therefore it is 0 volt.Due to the voltage of S pole of the second metal-oxide-semiconductor, the voltage of the second end of load resistance, the first metal-oxide-semiconductor the voltage of S pole the most identical, therefore the voltage of the S pole of the second metal-oxide-semiconductor is 0 volt.Tertiary voltage between D pole and the S pole of the second metal-oxide-semiconductor is 0 volt, and 0 volt is less than default Second Threshold.Tertiary voltage between the D pole and S pole of the second metal-oxide-semiconductor is less than when presetting Second Threshold, and the 4th voltage between the first outfan and second outfan of second control circuit is low level, and the 3rd outfan output logic low of second control circuit.When voltage between the G pole and D pole of the first metal-oxide-semiconductor is low level, the first metal-oxide-semiconductor can be in cut-off state, thus control the first metal-oxide-semiconductor by second control circuit and be in cut-off state.
In these cases, the 3rd outfan output logic low due to first control circuit, 3rd outfan output logic low of second control circuit, therefore, observation circuit can receive logic low by first input end, and logic low can be received by the second input, and determine and currently by the first power supply and second source, load resistance is powered, the PSE of i.e. current power supply is PSE1 and PSE2.Therefore, when PD is all powered by PSE1 and PSE2, if the supply voltage of PSE1 is identical with the supply voltage of PSE2, it practice, load resistance all can be powered by the two PSE.
In sum, when PD is powered by PSE1, and PD is powered by PSE2, then can control the second metal-oxide-semiconductor by first control circuit and be in cut-off state, and control the first metal-oxide-semiconductor by second control circuit and be in cut-off state, and may determine that the PSE of current power supply is PSE1 and PSE2.
Owing to the voltage of the S pole of the first metal-oxide-semiconductor is 0 volt, the voltage of the D pole of the first metal-oxide-semiconductor is 0 volt, therefore when there is parasitic diode in the first metal-oxide-semiconductor, voltage due to S pole is equal to the voltage of D pole, then form current loop between the second end of the parasitic diode in the first end of the first network interface, load resistance, the first metal-oxide-semiconductor, the first network interface, i.e. electric current can be through the first metal-oxide-semiconductor, and load resistance can be powered by the first power supply from PSE1 based on the parasitic diode in the first metal-oxide-semiconductor.
Owing to the voltage of the S pole of the second metal-oxide-semiconductor is 0 volt, the voltage of the D pole of the second metal-oxide-semiconductor is 0 volt, therefore when there is parasitic diode in the second metal-oxide-semiconductor, voltage due to S pole is equal to the voltage of D pole, then form current loop between the second end of the parasitic diode in the first end of the second network interface, load resistance, the second metal-oxide-semiconductor, the second network interface, i.e. electric current can be through the second metal-oxide-semiconductor, and load resistance can be powered by the second source from PSE2 based on the parasitic diode in the second metal-oxide-semiconductor.
Application scenarios 4, PD is not powered by PSE1, and PD is powered by PSE2.
Process under this application scene 4 is similar with the process under application scenarios 1, does not repeats them here.
Application scenarios 5, PD is all powered by PSE1 and PSE2, and the supply voltage that the supply voltage of PSE1 is less than PSE2, and such as, the supply voltage of PSE1 is 48, and the supply voltage of PSE2 is 54 volts.
Process under this application scene 5 is similar with the process under application scenarios 2, does not repeats them here.
The second situation, as a example by the conduction voltage drop in the first metal-oxide-semiconductor and the second metal-oxide-semiconductor is 0.8 volt.
Similar with the 5 of the first situation application scenarios, the second situation is divided into 5 application scenarios, processing of these 5 application scenarios is similar with the process of the 5 of the first situation application scenarios, its difference is: when the first metal-oxide-semiconductor/the second metal-oxide-semiconductor is in the conduction state, then the voltage of the S pole of the first metal-oxide-semiconductor/the second metal-oxide-semiconductor is different from the voltage of D pole, assume that D pole tension is for just, S pole tension is negative, then the first voltage between D pole and S pole/tertiary voltage is-0.8 volt, and-0.8 volt is less than preset first threshold value/default Second Threshold.
For the first situation and each application scenarios of the second situation, when PD is powered by PSE, the supply voltage of this PSE is not that to directly reach be 54 volts/48 volts, but in power supply process, rises to 54 volts/48 volts from 0 volt, and finally stable at 54 volts/48 volts.And, under normal conditions, metal-oxide-semiconductor has a conduction threshold, as conduction threshold can be 3 volts, when reaching 3 volts through the voltage of metal-oxide-semiconductor, this metal-oxide-semiconductor just can be in the conduction state, when being not up to 3 volts through the voltage of metal-oxide-semiconductor, this metal-oxide-semiconductor can be in cut-off state, and the original state of metal-oxide-semiconductor is cut-off state.
Based on above-mentioned principle, illustrate as a example by PSE1 powers, when PSE1 to the supply voltage of PD less than 3 volts time, the first metal-oxide-semiconductor can be in cut-off state, and formation loop between the second end of parasitic diode the first end of the first network interface, load resistance, the first metal-oxide-semiconductor within, the first network interface.When PSE1 is more than or equal to 3 volts to the supply voltage of PD, the first metal-oxide-semiconductor can be in the conduction state.On this basis, use aforesaid way, control the second metal-oxide-semiconductor by first control circuit and be in cut-off state or conducting state, and control the first metal-oxide-semiconductor by second control circuit and be in cut-off state or conducting state.
In this utility model embodiment, at Fig. 4, Fig. 8, Fig. 9, Figure 10, Tu11Zhong, second end of load resistance is ground end, the S of the first metal-oxide-semiconductor extremely holds, the S of the second metal-oxide-semiconductor extremely holds, and the second outfan of second control circuit is ground end, and the second input of second control circuit is ground end, second outfan of first control circuit is ground end, and the second input of first control circuit is ground end.
In this utility model embodiment, in order to make first control circuit realize when input is for during less than the level of preset first threshold value, ensure to be output as low level, when the level that input is more than or equal to preset first threshold value, ensure to be output as high level, then can use the structural representation of the first control circuit shown in Figure 12.
In order to make second control circuit realize when input is the level being less than and presetting Second Threshold, ensure to be output as low level, when the level that input is more than or equal to default Second Threshold, it is ensured that be output as high level, then can use the structural representation of the second control circuit shown in Figure 13.
As shown in figure 12, first control circuit includes the first input electronic circuit, the first not gate electronic circuit, the second not gate electronic circuit, the 5th not gate electronic circuit.Wherein, the first input end of first control circuit is the input of the first input electronic circuit, second input of first control circuit is ground end, the outfan that 3rd outfan is the second not gate electronic circuit of first control circuit, the first outfan of first control circuit and the outfan that the second outfan is the 5th not gate electronic circuit.Additionally, the input of the outfan of the first input electronic circuit and the first not gate electronic circuit connects, the outfan of the first not gate electronic circuit and the input of the second not gate electronic circuit connect, and the outfan of the first not gate electronic circuit and the input of the 5th not gate electronic circuit connect.
As shown in figure 13, second control circuit includes the second input electronic circuit, the 3rd not gate electronic circuit, the 4th not gate electronic circuit, the 6th not gate electronic circuit.Wherein, the first input end of second control circuit is the input of the second input electronic circuit, second input of second control circuit is ground end, the outfan that 3rd outfan is the 4th not gate electronic circuit of second control circuit, the first outfan of second control circuit and the outfan that the second outfan is the 6th not gate electronic circuit.Additionally, the input of the outfan of the second input electronic circuit and the 3rd not gate electronic circuit connects, the outfan of the 3rd not gate electronic circuit and the input of the 4th not gate electronic circuit connect, and the outfan of the 3rd not gate electronic circuit and the input of the 6th not gate electronic circuit connect.
In actual applications, each not gate electronic circuit (such as the first not gate electronic circuit, the second not gate electronic circuit, the 3rd not gate electronic circuit, the 4th not gate electronic circuit, the 5th not gate electronic circuit, the 6th not gate electronic circuit etc.) may each be the not gate electronic circuit using audion to realize.Wherein, not gate is also called inverter circuit, phase inverter, phase inverter etc., is the elementary cell of logic circuit, when its input is high level, outfan is low level, when its input is low level, outfan is high level, say, that the level state of input and outfan is the most anti-phase.Structure for each not gate electronic circuit; this utility model embodiment does not limits; the not gate electronic circuit that all use audions are capable of is all within the protection domain of this utility model embodiment, as shown in figure 14, for the example of the structural representation of a kind of not gate electronic circuit.
For the first control circuit shown in Figure 12, after the structure introducing not gate electronic circuit, the concrete structure of this first control circuit can be as shown in figure 15.For the second control circuit shown in Figure 13, after the structure introducing not gate electronic circuit, the concrete structure of this second control circuit can be as shown in figure 16.
As shown in figure 15, end points 1 is the first input end of first control circuit.End points 2, end points 4, end points 7, end points 11 are for connecting the first end of the load resistance in Fig. 4, and the Input voltage terminal of 54 volts in this way, in the not gate electronic circuit using audion to realize, it is equivalent to the end points V in Figure 14CC.End points 5, end points 6, end points 8, end points 9, end points 12 be all hold, BGND (place of working) in this way, it is the second input of first control circuit.End points 10 is the first outfan and second outfan of first control circuit, represents the first outfan and the second outfan with an end points, be two end points, the most no longer show in actual application in figure.End points 13 is the 3rd outfan of first control circuit.End points 3 is the outfan of the first input electronic circuit.End points 14 is the outfan of the first not gate electronic circuit.
For the first input electronic circuit, diode in first input electronic circuit, for ensureing that electric current is walked only along end points 2, resistance, end points 3, diode, resistance, the direction of end points 1, and can not walk along end points 1, resistance, diode, end points 3, resistance, the direction of end points 2, thus ensure the sense of current.
For each audion in Figure 15, its function is to realize not gate function, does not repeats them here.For each resistance in Figure 15, its function is to have electric current through out-of-date, carrying out voltage division processing, do not repeat them here.
For the second not gate electronic circuit, optocoupler in second not gate electronic circuit, for completing high level to low level isolation, operation principle for optocoupler, do not repeat them here, hereinafter briefly describe the reason being used herein as optocoupler: owing to end points 13 is the 3rd outfan of first control circuit, and the logic high of the 3rd outfan output of first control circuit needs to be input to observation circuit.In actual applications, being conditional for being input to the level value of observation circuit, it can not be more than a threshold value, if greater than this threshold value, then may burn out observation circuit.Therefore, by using optocoupler, complete high level to low level isolation, thus the logic high that guarantee is input to observation circuit is not more than this threshold value.
For the 26S Proteasome Structure and Function of device each in the second control circuit shown in Figure 16, similar with the 26S Proteasome Structure and Function of each device in the first control circuit shown in Figure 15, at this, it is no longer repeated.
Based on technique scheme, in this utility model embodiment, being powered by the PoE using metal-oxide-semiconductor to realize double netting twine, owing to metal-oxide-semiconductor has good switch handoff functionality, when metal-oxide-semiconductor is in the conduction state, this metal-oxide-semiconductor is equivalent to short circuit.Therefore, when metal-oxide-semiconductor is in the conduction state, the conduction voltage drop in this metal-oxide-semiconductor can be approximated to be 0, i.e. consume the power on metal-oxide-semiconductor the lowest, can be approximated to be 0, such that it is able to effectively reduce the power attenuation on path, the power of loss is negligible, thus effectively promotes power-efficient.Compared with the power needing waste 0.48W in prior art, the power of 0.48W can be saved, it is assumed that the peak power of PD side is 25.5W, be equivalent to improved efficiency about 2%.
Only several specific embodiments of the present utility model disclosed above, but this utility model is not limited to this, and the changes that any person skilled in the art can think of all should fall into protection domain of the present utility model.
Claims (10)
1. double network interface power supply circuits, it is characterised in that including: for receiving the first network interface of the first power supply from a PSE, for receiving the second network interface of second source, the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and load resistance from the 2nd PSE；First end of described first network interface is connected with the first end of described load resistance, and the second end of described first network interface is connected with the D pole of described first metal-oxide-semiconductor；First end of described second network interface is connected with the first end of described load resistance, and the second end of described second network interface is connected with the D pole of described second metal-oxide-semiconductor；The S pole of described first metal-oxide-semiconductor is connected with the second end of described load resistance；The S pole of described second metal-oxide-semiconductor is connected with the second end of described load resistance.
The most according to claim 1 pair of network interface power supply circuits, it is characterised in that
Described pair of network interface power supply circuits also include: first control circuit and second control circuit；
The D pole of described first metal-oxide-semiconductor is connected with the first input end of described first control circuit, and the S pole of described first metal-oxide-semiconductor is connected with the second input of described first control circuit；First outfan of described first control circuit is connected with the G pole of described second metal-oxide-semiconductor, and the second outfan of described first control circuit is connected with the S pole of described second metal-oxide-semiconductor；The D pole of described second metal-oxide-semiconductor is connected with the first input end of described second control circuit, and the S pole of described second metal-oxide-semiconductor is connected with the second input of described second control circuit；First outfan of described second control circuit is connected with the G pole of described first metal-oxide-semiconductor, and the second outfan of described second control circuit is connected with the S pole of described first metal-oxide-semiconductor；
Wherein, when the first voltage between the D pole and S pole of described first metal-oxide-semiconductor is less than preset first threshold value, the second voltage between the first outfan and second outfan of the most described first control circuit is low level；When described first voltage is more than or equal to preset first threshold value, the most described second voltage is high level；
Wherein, the tertiary voltage between the D pole and S pole of described second metal-oxide-semiconductor is less than when presetting Second Threshold, and the 4th voltage between the first outfan and second outfan of the most described second control circuit is low level；When described tertiary voltage is more than or equal to when presetting Second Threshold, and the most described 4th voltage is high level.
The most according to claim 2 pair of network interface power supply circuits, it is characterised in that
3rd outfan of described first control circuit is connected with the first input end of observation circuit；3rd outfan of described second control circuit is connected with the second input of described observation circuit；
Wherein, when described first voltage is less than preset first threshold value, the 3rd outfan output logic low of the most described first control circuit；When described first voltage is more than or equal to preset first threshold value, the 3rd outfan output logic high of the most described first control circuit；When described tertiary voltage is less than when presetting Second Threshold, and the 3rd outfan of the most described second control circuit exports logic low；When described tertiary voltage is for more than or equal to when presetting Second Threshold, and the 3rd outfan of the most described second control circuit exports logic high.
The most according to claim 3 pair of network interface power supply circuits, it is characterised in that
First control circuit includes the first input electronic circuit, the first not gate electronic circuit, the second not gate electronic circuit, the first input end of described first control circuit is the input of described first input electronic circuit, second input of described first control circuit is ground end, and the 3rd outfan of described first control circuit is the outfan of described second not gate electronic circuit；The outfan of described first input electronic circuit is connected with the input of described first not gate electronic circuit, and the outfan of described first not gate electronic circuit is connected with the input of described second not gate electronic circuit；
Second control circuit includes the second input electronic circuit, the 3rd not gate electronic circuit, the 4th not gate electronic circuit, the first input end of described second control circuit is the input of described second input electronic circuit, second input of described second control circuit is ground end, the outfan that the 3rd outfan is described 4th not gate electronic circuit of described second control circuit；The outfan of described second input electronic circuit is connected with the input of described 3rd not gate electronic circuit, and the outfan of described 3rd not gate electronic circuit is connected with the input of described 4th not gate electronic circuit.
The most according to claim 2 pair of network interface power supply circuits, it is characterised in that
Described first control circuit includes the first input electronic circuit, the first not gate electronic circuit, the 5th not gate electronic circuit, the first input end of described first control circuit is the input of described first input electronic circuit, second input of described first control circuit is ground end, and the first outfan of described first control circuit and the second outfan are the outfan of described 5th not gate electronic circuit；The outfan of described first input electronic circuit is connected with the input of described first not gate electronic circuit, and the outfan of described first not gate electronic circuit is connected with the input of described 5th not gate electronic circuit；
Described second control circuit includes the second input electronic circuit, 3rd not gate electronic circuit, 6th not gate electronic circuit, the first input end of described second control circuit is the input of described second input electronic circuit, second input of described second control circuit is ground end, first outfan of described second control circuit and the second outfan are the outfan of described 6th not gate electronic circuit, the outfan of described second input electronic circuit is connected with the input of described 3rd not gate electronic circuit, the outfan of described 3rd not gate electronic circuit is connected with the input of described 6th not gate electronic circuit.
6. according to the double network interface power supply circuits described in claim 4 or 5, it is characterised in that
Each not gate electronic circuit is all the not gate electronic circuit using audion to realize.
7. according to the double network interface power supply circuits described in any one of claim 1-5, it is characterised in that
Described pair of network interface power supply circuits also include: a PD control chip, the 2nd PD control chip；
First end of a described PD control chip is connected with the first end of described first network interface, described second end of a PD control chip is connected with the first end of described load resistance, and turns between the first end of a described PD control chip and the second end of a described PD control chip；
Described 3rd end of a PD control chip is connected with the second end of described first network interface, described 4th end of a PD control chip is connected with the D pole of described first metal-oxide-semiconductor, and also includes the 3rd metal-oxide-semiconductor between the 3rd end and the 4th end of a described PD control chip of a described PD control chip；
First end of described 2nd PD control chip is connected with the first end of described second network interface, described second end of the 2nd PD control chip is connected with the first end of described load resistance, and turns between the first end of described 2nd PD control chip and the second end of described 2nd PD control chip；
Described 3rd end of the 2nd PD control chip is connected with the second end of described second network interface, described 4th end of the 2nd PD control chip is connected with the D pole of described second metal-oxide-semiconductor, and also includes the 4th metal-oxide-semiconductor between the 3rd end and the 4th end of described 2nd PD control chip of described 2nd PD control chip.
The most according to claim 7 pair of network interface power supply circuits, it is characterised in that
Described pair of network interface power supply circuits also include: the first electric capacity and the second electric capacity；
First end of described first electric capacity is connected with the second end of a described PD control chip, and the second end of described first electric capacity is connected with the 4th end of a described PD control chip；
First end of described second electric capacity is connected with the second end of described 2nd PD control chip, and the second end of described second electric capacity is connected with the 4th end of described 2nd PD control chip.
9. according to the double network interface power supply circuits described in any one of claim 1-5, it is characterised in that
Resistance when the D pole of described first metal-oxide-semiconductor turns on S pole is less than presetting the first numerical value；
Resistance when the D pole of described second metal-oxide-semiconductor turns on S pole is less than presetting second value.
10., according to the double network interface power supply circuits described in any one of claim 1-5, it is characterised in that described pair of network interface power supply circuits are applied on PD, described load resistance is equivalent resistance.
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| CN201620391621.1U CN205647542U (en) | 2016-04-29 | 2016-04-29 | Two net gape supply circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108111316A (en) * | 2016-11-25 | 2018-06-01 | 新华三技术有限公司 | A kind of PSE |
| CN115314367A (en) * | 2022-07-20 | 2022-11-08 | 杭州熠芯科技有限公司 | Network card hot standby method for double-network-port double-host-machine interface |
-
2016
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108111316A (en) * | 2016-11-25 | 2018-06-01 | 新华三技术有限公司 | A kind of PSE |
| CN108111316B (en) * | 2016-11-25 | 2020-02-11 | 新华三技术有限公司 | PSE (Power supply Environment) |
| US11025441B2 (en) | 2016-11-25 | 2021-06-01 | New H3C Technologies Co., Ltd. | Power supply |
| CN115314367A (en) * | 2022-07-20 | 2022-11-08 | 杭州熠芯科技有限公司 | Network card hot standby method for double-network-port double-host-machine interface |
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Address after: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee after: Xinhua three Technology Co., Ltd. Address before: 310052 Binjiang District Changhe Road, Zhejiang, China, No. 466, No. Patentee before: Huasan Communication Technology Co., Ltd. |
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