CN205621726U - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
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- CN205621726U CN205621726U CN201521065280.0U CN201521065280U CN205621726U CN 205621726 U CN205621726 U CN 205621726U CN 201521065280 U CN201521065280 U CN 201521065280U CN 205621726 U CN205621726 U CN 205621726U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
- H01L2224/1401—Structure
- H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model relates to a semiconductor package of introduction metal column, it includes: the base plate main part, a plurality of first distribution patterns, the configuration is on the first face of base plate main part, first bonding welding pad pattern, the configuration is on first distribution figure, inside distribution pattern, the configuration is inside the base plate main part, second bonding welding pad pattern disposes on following the inside distribution figure that exposes in second bonded region, third bonding welding pad pattern, the configuration is on first distribution figure, a semiconductor chip and the 2nd semiconductor chip, staggered arrangement is range upon range of on the base plate main part, first metal column bie is connected first chip land part with first bonding welding pad, the second metal column bie is connected second chip land part with a plurality of second bonding welding pads, third metal post, an end connection are in first chip land portion, and another tip and a semiconductor chip's back face contacts, and the fourth metal column, bie be connected second chip land part with the third bonding welding pad.
Description
Technical field
Each embodiment of the present utility model relates to a kind of encapsulation technology, is more particularly to a kind of semiconductor packages introducing metal column.
Background technology
Along with miniaturization, the high performance of electronic product, and the increase of portable type electronic product, the encapsulated space of semiconductor element is more and more less, opposes that the functional requirement of electronic product is more and more diversified mutually.Therefore, the requirement to microminiature large-capacity semiconductor memorizer increasingly increases.The bonding technology carrying out substrate and semiconductor chip being electrically connected is needed during packaging semiconductor.Bonding technology is to utilize wire bonding (Wire bonding) mode or flip-chip bonding (Flip chip bonding) mode to carry out.Wire bonding mode is the mode utilizing conductive metal wire to connect substrate and semiconductor chip, and flip-chip bonding is the mode utilizing metal column to connect substrate and semiconductor chip.
Along with semiconductor element integrated level raising, utilize the electronic equipment high performance of semiconductor element, in terms of the performance raising of reply semiconductor element, there is limitation in wire bonding mode.Therefore, flip-chip bonding pattern is utilized the mode that substrate and semiconductor chip electrically connect to be gradually increased.
Utility model content
An embodiment of the present utility model includes: base plate for packaging；First Wiring pattern, it is arranged on first of described base plate for packaging；First bonding welding pad, it is arranged on the first Wiring pattern, and described first Wiring pattern is arranged in first upper and from described first Wiring pattern the first bond area of described base plate for packaging and exposes pattern；Internal Wiring pattern, it is arranged in the inside of described base plate for packaging；Second bonding welding pad, on the inside Wiring pattern that its second bond area being configured at the outermost part in described internal Wiring pattern is exposed；Third bond pad, it is arranged on the first Wiring pattern, and described first Wiring pattern is arranged in upper and outermost part from described first Wiring pattern the third bond region of first of described base plate for packaging and exposes pattern；First semiconductor chip and the second semiconductor chip, be staggered and stacking the most each other；First metal column, is not attached the first chip-pad portions of described first semiconductor chip with described first bonding welding pad；Second metal column, is not attached the second chip-pad portions of described first semiconductor chip with described second bonding welding pad；3rd metal column, its one end is connected to the first chip bonding pad portion of described second semiconductor chip, and the other end contacts with the rear lateral portion of described first semiconductor chip；And the 4th metal column, the second chip-pad portions of described second semiconductor chip is not attached with described third bond pad.
In this utility model, described first bonding welding pad can form a line at the middle body of described base plate for packaging.
Described second bonding welding pad can to the first direction of described base plate for packaging and along relative limit marginal portion arrange, described third bond pad to be perpendicular to described first direction second direction and along relative limit marginal portion arrange.
Described second bonding welding pad separates predetermined distance from described first bonding welding pad to direction, both sides respectively.
Described base plate for packaging also includes that the second Wiring pattern, described second Wiring pattern are connected with at least one in the first Wiring pattern on be arranged in described base plate for packaging first, and are arranged on second of described base plate for packaging.
Described internal Wiring pattern can be connected with described first bonding welding pad, the second bonding welding pad or third bond pad by more than one pore electrode of crossing.
Described base plate for packaging also includes exposing described second bonding welding pad and having the groove of prescribed depth.
Described groove has the degree of depth on the position that position that the bottom surfaces making the bottom surface of groove be arranged in Wiring pattern internal with each described configured is identical.
In described first semiconductor chip and the second semiconductor chip, superposed described second semiconductor chip exposes the marginal portion of described first semiconductor chip being positioned at bottom.
Described second semiconductor chip includes the depending crown portion that marginal portion is prominent to the first direction of described base plate for packaging.
Described semiconductor chip includes that chip bonding pad portion, described chip bonding pad portion include: the first chip bonding pad portion, it is arranged in the position relative with the first bond area of described base plate for packaging；And the second chip bonding pad portion, it is arranged in the position relative with the second bond area of described base plate for packaging.
Described chip bonding pad portion configures with I font flat shape.
Described second metal column has the thickness thicker than described first metal column.
Described second semiconductor chip includes that chip bonding pad portion, described chip bonding pad portion include: the first chip bonding pad portion, it is arranged in the position corresponding with the first bond area of described base plate for packaging；And the second chip bonding pad portion, it is arranged in the position relative with the third bond region of described base plate for packaging.
Described 4th metal column can have the thickness thicker than described 3rd metal column.
First metal column of described first semiconductor chip can have identical thickness with the 3rd metal column of described second semiconductor chip, and the 4th metal column of the second metal column of described first semiconductor chip and described second semiconductor chip has identical thickness.
Described third bond pad may also include the upper side from described third bond pad and highlights specified altitude and the external connection terminals that contacts with described 4th metal column.
Described external connection terminals includes stannum ball.
According to embodiment of the present utility model, utilized chip back bonding mode by multiple semiconductor chips to vertical direction stacking.
And, flip-chip bonding pattern can be passed through by semiconductor chip to vertical direction stacking, thus prevent semiconductor chip from being pressed or tilting.
In the semiconductor packages of an embodiment of the present utility model, described semiconductor chip includes that chip bonding pad portion, described chip bonding pad portion include: the first chip bonding pad portion, it is arranged in the position relative with the first bond area of described base plate for packaging；And the second chip bonding pad portion, it is arranged in the position relative with the second bond area of described base plate for packaging.
In the semiconductor packages of an embodiment of the present utility model, described chip bonding pad portion configures with I font flat shape.
In the semiconductor packages of an embodiment of the present utility model, described second metal column has the thickness thicker than described first metal column.
In the semiconductor packages of an embodiment of the present utility model, described second semiconductor chip includes that chip bonding pad portion, described chip bonding pad portion include: the first chip bonding pad portion, it is arranged in the position corresponding with the first bond area of described base plate for packaging；And the second chip bonding pad portion, it is arranged in the position relative with the third bond region of described base plate for packaging.
In the semiconductor packages of an embodiment of the present utility model, described chip bonding pad portion configures with I font flat shape.
In the semiconductor packages of an embodiment of the present utility model, described 4th metal column has the thickness thicker than described 3rd metal column.
In the semiconductor packages of an embodiment of the present utility model, first metal column of described first semiconductor chip has identical thickness with the 3rd metal column of described second semiconductor chip, and the 4th metal column of the second metal column of described first semiconductor chip and described second semiconductor chip has identical thickness.
In the semiconductor packages of an embodiment of the present utility model, the external connection terminals that described third bond pad also includes highlighting specified altitude from the upper side of described third bond pad and contacts with described 4th metal column.
In the semiconductor packages of an embodiment of the present utility model, described external connection terminals includes stannum ball.
Accompanying drawing explanation
By accompanying drawing and additional detailed description of the invention, multiple embodiments of the present utility model will be apparent from, wherein:
Fig. 1 is the plane graph of the base plate for packaging of an embodiment.
Fig. 2 is the sectional view representing I-I ' the line cutting along Fig. 1.
Fig. 3 is the sectional view representing II-II ' the line cutting along Fig. 1.
Fig. 4 is the axonometric chart representing the semiconductor packages for an embodiment is described.
Fig. 5 is the plane graph representing the semiconductor packages from top plan view 4.
Fig. 6 is the sectional view representing I-I ' the line cutting along Fig. 4.
Fig. 7 is the sectional view representing II-II ' the line cutting along Fig. 4.
Accompanying drawing explanation labelling
100: base plate for packaging 102: base main body portion
120a: the first passivation layer the 120b: the second passivation layer
A: the first the B: the second bond area, bond area
C: third bond region 130: the first semiconductor chip
160: the second semiconductor chip 145: the first metal columns
150: the second metal column 170: the three metal columns
172: the four metal columns
Detailed description of the invention
Although by illustrating accompanying drawing embodiment of the present utility model being described, but this is simply to illustrate that the content that proposed of this utility model, limits, not by detailed embodiment, the content that this utility model is proposed.
In the specification, identical reference represents identical assembly.Therefore, even if identical reference or similar reference are not mentioned or explanation in corresponding accompanying drawing, it is possible to illustrate with reference to other accompanying drawings.And, even if not marking reference, it is possible to illustrate with reference to other accompanying drawings.
Fig. 1 is the top view of the base plate for packaging of an embodiment.Fig. 2 is the sectional view representing I-I ' the line cutting along Fig. 1.Further, Fig. 3 is the sectional view representing II-II ' the line cutting along Fig. 1.
Referring to figs. 1 through Fig. 3, include base main body portion 102 (body), the first passivation layer 120a and the second passivation layer 120b according to the substrate 100 of an embodiment of the present utility model.Base plate for packaging 100 includes the first bond area A, the second bond area B and third bond region C.First bond area A can form a line at the middle body of base plate for packaging 100.Second bond area B and third bond region C is arranged in marginal portion respectively along four limits of base plate for packaging 100.Second bond area B can form a line in marginal portion to the first direction of substrate 100 and along relative limit.Third bond region C is to being perpendicular to the second direction of first direction and can to form a line along relative limit in marginal portion.The outermost part of the first bond area A can be configured to separate the size being equivalent to the first interval D 1 with the second bond area B.And, the first bond area A can be configured to separate the size being equivalent to the second interval D 2 with third bond region C.
First bond area A, the second bond area B and third bond region C may be defined as the interconnective region of its connection member, to realize the electrical connection between the circuit layout in the first semiconductor chip, the second semiconductor chip and the base main body portion 102 being individually enclosed on substrate 100.In embodiment of the present utility model, although the base plate for packaging 100 with quadrilateral plan shape is illustrated, but is not limited to this.In one of them example, base plate for packaging 100 can have polygonal shape.First bond area A includes that the region residing for the first bonding welding pad 104, the second bond area B include the region residing for the second bonding welding pad 112.And, third bond region C includes the region residing for third bond pad 125.First bonding welding pad 104 separates predetermined distance with third bond pad 125, and is arranged side by side to the horizontal direction i.e. first direction of base plate for packaging 100.
Base main body portion 102 can be by including that first 102a and the panel component with first relative for 102a second 102b form.Base main body portion 102 can include the more than one material in the combination of insulator material being made up of polymer resin, epoxy resin or plastics.One of them example is, base main body portion 102 can be the structure that stacking includes the thin layer of described material.
First 102a in base main body portion 102 may be configured with the first passivation layer 120a.One of them example is, the first passivation layer 120a can include solder resist (solder resist).Second 102b in base main body portion 102 may be configured with the second passivation layer 120b.One of them example is, the second passivation layer 120b can include solder resist.First passivation layer 120a includes being positioned at multiple first peristomes 121 of the first bond area A, being positioned at multiple second peristomes 122 of the second bond area B and be positioned at multiple 3rd peristomes 123 of third bond region C.Each first peristome 121 exposes the first bonding welding pad 104, and each second peristome 122 exposes the second bonding welding pad 112.And, each 3rd peristome 123 exposes third bond pad 125.
In the second bond area B from the surface of the first passivation layer 120a to the depth H 1 of the upper side of the second bonding welding pad 104 more than depth H 2 from the surface of the first passivation layer 120a to the upper side of the first bonding welding pad 104 in the first bond area A.Therefore, expose a part for the first passivation layer 120a side at the first peristome 121 being positioned at the first bond area A, and expose side and a part for side, base main body portion 102 of the first passivation layer 120a at the second peristome 122 being positioned at the second bond area B.Therefore, the upper side of the first bonding welding pad 104 is positioned at ratio on the higher level of upper side of the second bonding welding pad 112.And, in the C of third bond region, depth H 3 from the surface of the first passivation layer 120a to the upper side of third bond pad 125 is identical with depth H 2 from the surface of the first passivation layer 120a to the upper side of the first bonding welding pad 104 in the first bond area A.Therefore, the upper side of third bond pad 125 is positioned on the level identical with the upper side of the first bonding welding pad 104, and than on the higher level of upper side of the second bonding welding pad 112.
With reference to Fig. 2, have according to the base plate for packaging 100 of an embodiment and include multiple first Wiring pattern 103, second Wiring pattern 106a, 106b, 106c, 106d and the multi-layer substrate structure of internal Wiring pattern 110a, 110b, 110c, 110d.One of them example is, first 102a in base main body portion 102 is configured with the first Wiring pattern 103.First Wiring pattern 103 can be electrically isolated from each other or be electrically connected to each other in other regions.First Wiring pattern 103 can electrically connect with the first bonding welding pad 104 being arranged in the first bond area A.And, the first Wiring pattern 103 can electrically connect with the third bond pad 125 being arranged in the B of third bond region.
It is configured with second Wiring pattern 106a, 106b, 106c, 106d on second 102b in base main body portion 102.Second Wiring pattern 106a, 106b, 106c, 106d can be electrically isolated from each other or be connected with each other in other regions.At least one in first Wiring pattern 103 can be crossed pore electrode 108a by first in base main body portion 102 with at least one in internal Wiring pattern 110a, 110b, 110c and electrically connect.The upper side of the first bottom surfaces and internal Wiring pattern 110a, 110c crossing pore electrode 108a is connected, and contacts with the bottom surfaces of the first Wiring pattern 103.At least one in internal Wiring pattern 110a, 110b, 110c, 110d and at least one in second Wiring pattern 106a, 106b, 106c, 106d by second cross pore electrode 108b, the 3rd pore electrode 108c and/or the 4th mistake pore electrode 108d be electrically connected to each other.Second cross pore electrode 108b, the 3rd cross pore electrode 108c and/or the 4th and cross the bottom surfaces of pore electrode 108d and the upper side bottom surfaces respectively with the upper side of the second Wiring pattern and internal Wiring pattern and contact.It addition, the first pore electrode 108a excessively, the second arrangement crossing pore electrode 108b, the 3rd mistake pore electrode 108c and/or the 4th mistake pore electrode 108d can consist of various structures according to the purposes etc. of base plate for packaging 100.
Base main body portion 102 has the groove T1 of the prescribed depth arranged by the second peristome 122 and formed at the second bond area B.The position that the degree of depth of groove T1 is configured with the bottom surfaces of each internal Wiring pattern 110a, 110b, 110c, 110d is substantially identical.The part surface of an internal layer Wiring pattern 110d in internal layer Wiring pattern exposes because of the second peristome 122 and groove T1, and is configured with the second bonding welding pad 112 on its exposing surface.It is configured with the second passivation layer 120b on second 102b and second Wiring pattern 106a, 106b, 106c, 106d in base main body portion 102.Second passivation layer 120b has multiple 3rd peristomes 107 that a part for the upper side by each second Wiring pattern 106a, 106b, 106c, 106d is exposed.Though each second Wiring pattern 106a that is the most not shown, that expose because of the 3rd peristome 107, the upper side of 106b, 106c, 106d may be configured with external connection terminals, such as, stannum ball.
Fig. 4 is the axonometric chart representing the flip chip semiconductor package for an embodiment is described.Fig. 5 is the plane graph of the flat shape representing Fig. 4.Fig. 6 is the sectional view representing I-I ' the line cutting along Fig. 4.And, Fig. 7 is the sectional view representing II-II ' the line cutting along Fig. 4.
With reference to Fig. 4 to Fig. 7, semiconductor packages 200 has and stacks gradually the first semiconductor chip 130 and structure of the second semiconductor chip 160 on base plate for packaging 200.Base plate for packaging 100 includes the base main body portion 102 with first 102a and second 102b.The base plate for packaging 100 of Fig. 4 to Fig. 7 is substantially identical with the structure at Fig. 1 to base plate for packaging 100 illustrated in fig. 3, therefore, takes the assembly with identical reference to omit or the mode of schematic illustration.
Base main body portion 102 can include the more than one material in the combination of insulator material being made up of polymer resin, epoxy resin or plastics.One of them example is, base main body portion 102 can be the structure that stacking includes the thin layer of described material.First 102a and second 102b in base main body portion 102 are each configured with the first passivation layer 120a and the second passivation layer 120b.One of them example is, the first passivation layer 120a and the second passivation layer 120b can be made up of solder resist (solder resist).
As it is shown in figure 1, base plate for packaging 100 has the first bond area A, the second bond area B and third bond region C.First bond area A is positioned at the middle body of base plate for packaging 100, the second bond area B and third bond region C can be arranged in marginal portion along the four of base plate for packaging 100 limit.Specifically, the second bond area B can form a line in marginal portion to the first direction of substrate 100 and along relative limit.And, third bond region C to being perpendicular to the second direction of first direction and can form a line along relative limit in marginal portion.
First bond area A of base plate for packaging 100 exposes the first bonding welding pad 104, and the second bond area B exposes the second bonding welding pad 112.And, third bond region C exposes third bond pad 125.Here, the first bonding welding pad 104 is configurable on first 102a in base main body portion 102 top of the first Wiring pattern 103 configured.Second bonding welding pad 112 is configurable on internal Wiring pattern, and described internal Wiring pattern second bond area B of outermost part from inside Wiring pattern 110a, 110b, 110c, the 110d being configured within base main body portion 102 exposes.Therefore, the second bonding welding pad 112 is positioned on the level lower than the upper side of the first bonding welding pad 104.And, third bond pad 125 is configurable on the first Wiring pattern, and described first Wiring pattern third bond region of outermost part from multiple first Wiring patterns 103 being configured at 102 first, base main body portion 102a is exposed.
First passivation layer 120a top of base plate for packaging 100 is configured with the first semiconductor chip 130 and the second semiconductor chip 160 successively.First semiconductor chip 130 and the second semiconductor chip 160 are staggered and stacking each other.As shown in Figure 4 and Figure 5, owing to the first semiconductor chip 130 and the second semiconductor chip 160 are staggered, superposed second semiconductor chip 160 can expose the marginal portion 205 of the first semiconductor chip 130 being positioned at bottom.And, the marginal portion 210 of second semiconductor chip 160 on top will not be overlapping with the first semiconductor chip 130, and forms hanging (overhang) part prominent to the first direction of base plate for packaging 100.
Formed just like the active components such as transistor (active device) in first semiconductor chip 130, according to circumstances, may also be formed with such as the passive element such as capacitor, depositor.First semiconductor chip 130 can include it can being the first front side portion 130a (front-side) of the active layer being formed with active component and first rear lateral portion 130b (back-side) relative for front side portion 130a with first.Multiple chip bonding pad portion 135,140 it is configured with on first front side portion 130a of the first semiconductor chip 130.The chip bonding pad portion 135,140 of the first semiconductor chip 130 includes the first chip bonding pad portion 135 and the second chip bonding pad portion 140.
First bond area A (with reference to Fig. 1) of the first chip bonding pad portion 135 and base plate for packaging 100 is arranged in the middle body of the first semiconductor chip 130 accordingly, and the adjacent multiple first chip bonding pad portions 135 in respectively arranging can be spaced from each other arrangement.Second bond area B (with reference to Fig. 1) of multiple second chip bonding pad portions 140 and base plate for packaging 100 is arranged in the marginal portion of the first semiconductor chip 130 accordingly, and the adjacent multiple second chip bonding pad portions 140 in respectively arranging can be spaced from each other arrangement.Second chip bonding pad portion 140 can form a line to the first direction of base plate for packaging 100 and along marginal portion on two relative limits.First chip bonding pad portion 135 can form a line to the second direction being perpendicular to first direction.Therefore, the flat shape in the chip bonding pad portion 135,140 being configured on the first front side portion 130a of the first semiconductor chip 130 can form ' I ' font.
First semiconductor chip 130 on the first passivation layer 120a top being configured at base plate for packaging 100 is electrically connected with base plate for packaging 100 by metal column 145,150.Metal column 145,150 can have post shapes and include copper.Metal column 145,150 includes the first metal column 145 being connected to the first chip bonding pad portion 135 respectively and is connected to second metal column 150 in multiple second chip bonding pad portion 140.Specifically, the one end of the first metal column 145 is connected to the upper side being exposed in the first chip bonding pad portion 135, and the other end is connected to the upper side being exposed of the first bonding welding pad 104 with the first external connection terminals 155a for medium.One of them example is, the first external connection terminals 155a includes stannum ball.The one end of the second metal column 150 is connected to the upper side being exposed in the second chip bonding pad portion 140, and the other end is connected to the upper side being exposed of the second bonding welding pad 112 with the second external connection terminals 155b for medium.One of them example is, the second external connection terminals 155b includes stannum ball.
First metal column 145 is formed as having the first thickness BH1 from the surface of the upper side exposed in the first chip bonding pad portion 135.In contrast, the second metal column 150 is formed as having the second thickness BH2 from the surface of the upper side exposed in the second chip bonding pad portion 140.Here, the second thickness BH2 of the second metal column 150 is more than the first thickness BH1 of the first metal column 145.Therefore, the second metal column 150 can be connected with the second bonding welding pad 112 respectively by inserting the groove T1 of the second bond area B.The first metal column 145 being connected with the first bonding welding pad 104 can be electrically connected to each other by least one in pore electrode 108a, 108b, 108c, the 108d excessively in base main body portion 102 and second Wiring pattern 106a, 106b, 106c, 106d.In contrast, the second metal column 150 being connected with the second bonding welding pad 112 will not be electrically connected to each other.Second metal column 150 is arranged in marginal portion, thus plays the effect of the support that suppression the first semiconductor chip 130 tilts to base plate for packaging 100 direction.
The top of the first semiconductor chip 130 is configured with the second semiconductor chip 160.Second semiconductor chip 160 configures with the first interlaced arrangement of semiconductor chip 130.Second semiconductor chip 160 can have the size identical with the first semiconductor chip 130.Form the active component just like transistor etc. in second semiconductor chip 160, according to circumstances, may also be formed with the passive element such as capacitor, depositor etc..Second semiconductor chip 160 can include it can being the first front side portion 160a of the active layer being formed with active component and second rear lateral portion 160b relative for front side portion 160a with first.Multiple chip bonding pad portion 165,167 it is configured with on first front side portion 160a of the second semiconductor chip 160.The chip bonding pad portion 165,167 of the second semiconductor chip 160 includes the first chip bonding pad portion 165 and the second chip bonding pad portion 167.
First chip bonding pad portion 165 forms a line at the middle body of the second semiconductor chip 160 to the first direction of base plate for packaging 100, and the first adjacent chip bonding pad portion 165 can be spaced from each other arrangement.Third bond region C (with reference to Fig. 1) of the second chip bonding pad portion 167 and base plate for packaging 100 is arranged in the marginal portion of the second semiconductor chip 160 accordingly, and the second adjacent chip bonding pad portion 167 can be spaced from each other arrangement.Second chip bonding pad portion 167 can be perpendicular to base plate for packaging 100 first direction second direction and along marginal portion configure.Second chip bonding pad portion 167 can form a line on relative two limit of base plate for packaging 100.Therefore, the flat shape in the chip bonding pad portion 165,167 being configured on the first front side portion 160a of the second semiconductor chip 160 can form ' I ' font.
Second semiconductor chip 160 is electrically connected with base plate for packaging 100 by metal column 170,172.The metal column 170,172 of the second semiconductor chip 160 can have post shapes and include copper.Metal column 170,172 includes the 3rd metal column 170 and the 4th metal column 172.The one end of the 3rd metal column 170 is connected to the upper side in the first chip bonding pad portion 165, and the other end is with the first external connection terminals 175 for medium and the second rear lateral portion 160b contact of the first semiconductor chip 130.The one end of the 4th metal column 172 is connected to the upper side in the second chip bonding pad portion 167, and the other end is connected to the second external connection terminals 177.
With reference to Fig. 7, the 3rd metal column 170 is formed as having the first thickness BH3 from the surface of the upper side being exposed in the first chip bonding pad portion 165.4th metal column 172 is formed as having the second thickness BH4 from the surface of the upper side being exposed in the second chip bonding pad portion 167.Here, the second thickness BH4 of the 4th metal column 172 is more than the first thickness BH3 of the 3rd metal column 170.
The second external connection terminals 177 connected with the 4th metal column 172 contacts with multiple 3rd external connection terminals 180 on the third bond pad 125 of base plate for packaging 100 and electrically connects.Such as, the 3rd external connection terminals 180 can include stannum ball.3rd external connection terminals 180 highlights specified altitude SH from the upper side of third bond pad 125.3rd metal column 170 of the second semiconductor chip 160 has the thickness identical with the first metal column 145 of the first semiconductor chip 130, and the 4th metal column 172 of the second semiconductor chip 160 has the thickness identical with the second metal column 150 of the first semiconductor chip 130.Therefore, the height SH that the 3rd external connection terminals 180 is highlighted has the thickness that can contact with the 4th metal column 172.4th metal column 172 is connected electrically in the third bond pad 125 of base plate for packaging 100 by the 3rd external connection terminals 180, and is connected to the second Wiring pattern 106d by internal Wiring pattern with crossing pore electrode.Therefore, the second semiconductor chip 160 can be connected electrically in base plate for packaging 100 by the 4th metal column 172.On the contrary, the 3rd metal column 170 will not electrically connect with the first semiconductor chip 130 or base plate for packaging 100.3rd metal column 170 is arranged between the 4th adjacent metal column 172, thus plays the effect preventing the second semiconductor chip 160 from being pressed.
Claims (19)
1. a semiconductor packages, comprising:
Base plate for packaging；
First Wiring pattern, it is arranged on first of described base plate for packaging；
First bonding welding pad, it is arranged on the first Wiring pattern, and described first Wiring pattern is arranged in first upper and from described first Wiring pattern the first bond area of described base plate for packaging and exposes pattern；
Internal Wiring pattern, it is arranged in the inside of described base plate for packaging；
Second bonding welding pad, it is configured on the inside Wiring pattern that the second bond area of outermost part is exposed from described internal Wiring pattern；
Third bond pad, it is arranged on the first Wiring pattern, and described first Wiring pattern is arranged in upper and outermost part from described first Wiring pattern the third bond region of first of described base plate for packaging and exposes pattern；
First semiconductor chip and the second semiconductor chip, be staggered and stacking the most each other；
First metal column, is not attached the first chip-pad portions of described first semiconductor chip with described first bonding welding pad；
Second metal column, is not attached the second chip-pad portions of described first semiconductor chip with the plurality of second bonding welding pad；
3rd metal column, its one end is connected to the first chip bonding pad portion of described second semiconductor chip, and the other end contacts with the rear lateral portion of described first semiconductor chip；And
4th metal column, is not attached the second chip-pad portions of described second semiconductor chip with described third bond pad.
Semiconductor packages the most according to claim 1, described first bonding welding pad forms a line at the middle body of described base plate for packaging.
Semiconductor packages the most according to claim 1, described second bonding welding pad arranges to the first direction of described base plate for packaging and along relative limit in marginal portion, and described third bond pad is to being perpendicular to the second direction of described first direction and arranging in marginal portion along relative limit.
Semiconductor packages the most according to claim 1, described second bonding welding pad separates predetermined distance from described first bonding welding pad to direction, both sides respectively.
Semiconductor packages the most according to claim 1, described base plate for packaging also includes the second Wiring pattern, described second Wiring pattern is connected with at least one in the first Wiring pattern on be arranged in described base plate for packaging first, and is arranged on second of described base plate for packaging.
Semiconductor packages the most according to claim 1, described internal Wiring pattern is connected with described first bonding welding pad, the second bonding welding pad or third bond pad by more than one pore electrode of crossing.
Semiconductor packages the most according to claim 1, described base plate for packaging also includes exposing described second bonding welding pad and having the groove of prescribed depth.
Semiconductor packages the most according to claim 7, described groove has the degree of depth on the position that position that the bottom surfaces making the bottom surface of groove be arranged in Wiring pattern internal with each described configured is identical.
Semiconductor packages the most according to claim 1, in described first semiconductor chip and the second semiconductor chip, superposed described second semiconductor chip exposes the marginal portion of described first semiconductor chip being positioned at bottom.
Semiconductor packages the most according to claim 1, described second semiconductor chip includes the depending crown portion that marginal portion is prominent to the first direction of described base plate for packaging.
11. semiconductor packages according to claim 1, described first semiconductor chip includes that chip bonding pad portion, described chip bonding pad portion include:
First chip bonding pad portion, it is arranged in the position relative with the first bond area of described base plate for packaging；And
Second chip bonding pad portion, it is arranged in the position relative with the second bond area of described base plate for packaging.
12. semiconductor packages according to claim 11, described chip bonding pad portion configures with I font flat shape.
13. semiconductor packages according to claim 1, described second metal column has the thickness thicker than described first metal column.
14. semiconductor packages according to claim 1, described second semiconductor chip includes that chip bonding pad portion, described chip bonding pad portion include:
First chip bonding pad portion, it is arranged in the position corresponding with the first bond area of described base plate for packaging；And
Second chip bonding pad portion, it is arranged in the position relative with the third bond region of described base plate for packaging.
15. semiconductor packages according to claim 14, described chip bonding pad portion configures with I font flat shape.
16. semiconductor packages according to claim 1, described 4th metal column has the thickness thicker than described 3rd metal column.
17. semiconductor packages according to claim 1, first metal column of described first semiconductor chip has identical thickness with the 3rd metal column of described second semiconductor chip, and the 4th metal column of the second metal column of described first semiconductor chip and described second semiconductor chip has identical thickness.
18. semiconductor packages according to claim 1, the external connection terminals that described third bond pad also includes highlighting specified altitude from the upper side of described third bond pad and contacts with described 4th metal column.
19. semiconductor packages according to claim 18, described external connection terminals includes stannum ball.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2015-0076395 | 2015-05-29 | ||
| KR1020150076395A KR20160141280A (en) | 2015-05-29 | 2015-05-29 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205621726U true CN205621726U (en) | 2016-10-05 |
Family
ID=57034525
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521065280.0U Active CN205621726U (en) | 2015-05-29 | 2015-12-18 | Semiconductor package |
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| Country | Link |
|---|---|
| KR (1) | KR20160141280A (en) |
| CN (1) | CN205621726U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109962019A (en) * | 2017-12-22 | 2019-07-02 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out-type wafer level packaging structure and method |
| CN114975333A (en) * | 2022-07-29 | 2022-08-30 | 广东大普通信技术股份有限公司 | Chip structure |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102647423B1 (en) * | 2019-03-04 | 2024-03-14 | 에스케이하이닉스 주식회사 | semiconductor package having wire-bonding connection structure and semiconductor package structure including the same |
-
2015
- 2015-05-29 KR KR1020150076395A patent/KR20160141280A/en unknown
- 2015-12-18 CN CN201521065280.0U patent/CN205621726U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109962019A (en) * | 2017-12-22 | 2019-07-02 | 中芯长电半导体（江阴）有限公司 | A kind of fan-out-type wafer level packaging structure and method |
| CN114975333A (en) * | 2022-07-29 | 2022-08-30 | 广东大普通信技术股份有限公司 | Chip structure |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20160141280A (en) | 2016-12-08 |
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