CN205609518U - Semiconductor device of ultra -thin 3D encapsulation and semiconductor device's of ultra -thin 3D encapsulation semi -manufactured goods - Google Patents
Semiconductor device of ultra -thin 3D encapsulation and semiconductor device's of ultra -thin 3D encapsulation semi -manufactured goods Download PDFInfo
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- CN205609518U CN205609518U CN201620467787.7U CN201620467787U CN205609518U CN 205609518 U CN205609518 U CN 205609518U CN 201620467787 U CN201620467787 U CN 201620467787U CN 205609518 U CN205609518 U CN 205609518U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Abstract
The utility model discloses a semiconductor device of ultra -thin 3D encapsulation and semiconductor device's of ultra -thin 3D encapsulation semi -manufactured goods, including ultra -thin base plate, the top surface of ultra -thin base plate is provided with at least one and goes up the chip, goes up the chip and passes through bonding line and bonding point and ultra -thin substrate connection and communicates, still is provided with the parcel on the top surface of ultra -thin base plate go up the plastic envelope layer of chip, bonding line and bonding point, the bottom surface flip -chip of ultra -thin base plate has lower chip, and the bottom surface of lower chip lies in the planar top in minimum place of the tin ball that ultra -thin base plate bottom surface set up. The utility model discloses an install the chip in the bottom of ultra -thin base plate will be descended to flip -chip technology, can realize that the size of whole packaging body is reduced by a wide margin, and the height of whole packaging body can have only 800 mu m, be less than far away and weld ball grid array's 1200 1400 mu m's height, lower chip is arranged in the open architecture radiating efficiency and improves greatly, saved the structure of infrabasal plate among the ordinary face down chip packaging technology, the cost reduces to it is simple relatively to lay wire.
Description
Technical field
This utility model relates to the semi-finished product during a kind of semiconductor device and described semiconductor device fabrication, particularly relates to the semi-finished product during the semiconductor device of a kind of ultra-thin 3D encapsulation and the semiconductor device fabrication of described ultra-thin 3D encapsulation.
Background technology
3D wafer-level packaging, English abbreviation (WLP), including CIS emitter, MEMS package, normal component encapsulation, refer on the premise of not changing package body sizes, stack the encapsulation technology of two or more chip in vertical direction in same packaging body, it originates from flash memory (NOR/NAND) and the stacked package of SDRAM, and main feature includes: multi-functional, high-effect；Large Copacity high density, the function in unit volume and application lifting and low cost at double, 3D encapsulation improves many performances of chip, such as lateral dimension, weight, speed, yield and power consumption.
But, conventional stacked package, as shown in Figure 1, two chip blocks 20 are stacked by it, and realize substrate 40 by the bonding technology of gold thread 30 and communicate with the connection of chip 20, then form the encapsulated layer 50 of parcel chip, and finally making pad 60 forms final products.
The development of this packaging technology has the restriction of electrical characteristics, mechanical performance, thermal characteristics, packaging cost, packaging height etc., and owing to chip is respectively positioned in the closing space of plastic packaging layer, heat cannot discharge, and therefore radiating efficiency is poor；And due to by chip-stacked together, the most whole packaging body longitudinally the biggest, Altitude control is limited, and connects up relative complex, and cost is high.
And the structure of another kind flip-chip (Flip chip) is a kind of without pin configuration, Flip chip(flip-chip) packaging technology, it is deposition tin-lead ball on chip pin, then the tin-lead ball that chip upset adds heat utilization melted is combined with ultra thin substrate, this technology is replaced conventional routing and is engaged, and is increasingly becoming the encapsulation main flow in future.
Flip chip structure as shown in Figure 2, it includes at least one chip 80 being positioned on upper substrate 70 and a chip being positioned on infrabasal plate 90 100, and being communicated by stannum ball 110 between upper substrate and infrabasal plate, infrabasal plate is provided with the stannum ball 120 being connected with other elements.
In this flip chip packaging structure, the chip being usually located on upper substrate is often used for storage, and the chip being positioned on infrabasal plate is for calculation process, therefore heat is produced bigger, and due to (chip is in approximation and closes in space) in the space that the stannum ball between upper substrate and infrabasal plate of the chip on infrabasal plate is enclosed, therefore radiating efficiency is poor.
And owing to adding the stannum ball on infrabasal plate and infrabasal plate, therefore the height of the relatively conventional stacked package of the whole height of packaging body is higher, the control of height is the most limited, and adds a substrate, and therefore the cost of the wiring on substrate and encapsulation increases the most further.
Summary of the invention
One of the purpose of this utility model is contemplated to solve the above-mentioned problems in the prior art, by the structural adjustment to semiconductor device, the reverse bonding technique of associative key zygonema and the reverse installation process of chip, thus provide the semiconductor device of a kind of ultra-thin 3D encapsulation；Another object of the present utility model is the semi-finished product during the semiconductor device fabrication providing a kind of ultra-thin 3D to encapsulate.
The purpose of this utility model is achieved through the following technical solutions:
A kind of semiconductor device of ultra-thin 3D encapsulation, including ultra thin substrate, the end face of described ultra thin substrate is provided with chip at least one, described upper chip is connected with ultra thin substrate by bonding line and bonding point and communicates, and the end face of described ultra thin substrate is additionally provided with and wraps up described upper chip, bonding line and the plastic packaging layer of bonding point；The bottom surface upside-down mounting of described ultra thin substrate has lower chip, the bottom surface of described lower chip to be positioned at the top of minimum point place plane of the stannum ball that described ultra thin substrate bottom surface is arranged.
Preferably, the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: described ultra thin substrate is resin ultra thin substrate.
Preferably, the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: the camber of described bonding line is less than 60mm.
Preferably, the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: the thickness of described plastic packaging layer is less than 150 microns.
Preferably, the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: described lower chip is connected with described ultra thin substrate by some dimpling blocks being positioned at bottom described ultra thin substrate and is communicated, and described dimpling block is coated in the Underfill layer bottom ultra thin substrate and between lower chip.
Preferably, the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: described dimpling block is gold goal or stannum ball.
A kind of semi-finished product of the semiconductor device of ultra-thin 3D encapsulation, semiconductor device including several above-mentioned ultra-thin 3D encapsulation, the semiconductor device of described ultra-thin 3D encapsulation is connected by common ultra thin substrate, and is provided with stress release mechanism between the semiconductor device of the described ultra-thin 3D encapsulation of arbitrary neighborhood.
Preferably, the semi-finished product of the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: described stress release mechanism is the breach that the end face from plastic packaging layer arranged between the semiconductor device of the described ultra-thin 3D encapsulation of gap or the arbitrary neighborhood arranged between the plastic packaging layer of the semiconductor device of the described ultra-thin 3D encapsulation of arbitrary neighborhood extends to ultra thin substrate.
Preferably, the semi-finished product of the semiconductor device of described a kind of ultra-thin 3D encapsulation, wherein: described gap or the width of breach are 0.2-0.3mm.
The advantage of technical solutions of the utility model is mainly reflected in:
This utility model deft design, simple in construction, by reverse installation process, lower chip is installed on the bottom of ultra thin substrate, and by controlling the height such as ultra thin substrate, chip, plastic packaging layer, the size being capable of whole packaging body significantly reduces, after having encapsulated, the height of whole packaging body can only have 800 μm, well below the height of the 1200-1400 μm of conventional BGA technique (welded ball array encapsulation)；Simultaneously as lower chip is positioned at the lower section of ultra thin substrate and is in open architecture, the heat therefore descending chip to produce can quickly discharge, and radiating efficiency is greatly improved.
Further, relative to common Flip-Chip Using technique, eliminating the structure of lower ultra thin substrate, cost lowers, and connects up relatively easy.
The semi-finished product of the semiconductor device of ultra-thin 3D of the present utility model encapsulation, processing is simple, can effectively realize the making of the semiconductor device of ultra-thin 3D encapsulation, and the internal stress of the ultra thin substrate deformation warpage caused owing to chip is different with the shrinkage factor of ultra thin substrate can be effectively discharged by the gap between plastic packaging layer, thus avoid the flip-chip caused because of ultra thin substrate warpage and ultra thin substrate connect that dimpling block can not be stable and that ultra thin substrate connects problem, it is ensured that the quality of the semiconductor device of ultra-thin 3D encapsulation and stability.
Accompanying drawing explanation
Fig. 1 is the structural representation of the semiconductor device of conventional 3D packaging technology in background technology；
Fig. 2 is the structural representation of the semiconductor device of reverse installation process in background technology；
Fig. 3 is structural representation of the present utility model；
Fig. 4 is the structural representation of the semi-finished product of the semiconductor device of ultra-thin 3D encapsulation in this utility model.
Detailed description of the invention
The purpose of this utility model, advantage and feature, by for illustration and explanation by the non-limitative illustration of preferred embodiment below.These embodiments are only the prominent examples of application technical solutions of the utility model, all technical schemes taking equivalent or equivalent transformation and formed, all fall within this utility model claimed within the scope of.
The semiconductor device of a kind of ultra-thin 3D encapsulation that this utility model discloses, as shown in Figure 3, including ultra thin substrate 1, described ultra thin substrate 1 can be various feasible substrates, organic substrate, mineral-type substrate in this way, preferably resin substrate, the thickness of described ultra thin substrate 1 can be less than 200 μm, is preferably 200 μm in the present embodiment.
And, described ultra thin substrate 1 is dual platen, being provided with conductor layer No.1 on its end face and some for connecting, with upper chip, the bonding point 4 communicated, its bottom surface is provided with the second conductor layer, and described conductor layer No.1 and the second conductor layer are connected by some guide holes being filled with metal and communicated.
The end face of described ultra thin substrate 1 is provided with chip 2 at least one, in the present embodiment as a example by a upper chip 2, described upper chip 2 can be various types of chip, its thickness is as the criterion with the thickness that concrete chip type is corresponding, the preferred described upper chip 2 of the present embodiment is the chip of storage class, and the heat produced during its work is relatively small and its thickness is preferably 100um.
And, the bonding point that some bonding points 4 arranged with described ultra thin substrate 1 end face match it is provided with on described upper chip 2, by bonding line 3, the bonding point on bonding point 4 on ultra thin substrate 1 and upper chip 2 is connected, thus realize the communication between described ultra thin substrate 1 and upper chip 2；Owing to the present embodiment using ultra thin substrate 1, relatively common substrate thickness is less, therefore it is required that the camber of bonding line 3 is lower, therefore this utility model makes the camber of described bonding line 3 be less than 60 μm by reverse bonding technique, thus be conducive to reducing the height of whole packaging body.
Further, the described upper chip 2 of parcel it is additionally provided with on the end face of described ultra thin substrate 1, the plastic packaging layer 5 of bonding line 3 and bonding point 4, the material of described plastic packaging layer 5 is at present with epoxy resin, phenolic resin, organic siliconresin and unsaturated polyester resin are the most commonly used, it is preferably epoxy resin plastic packaging glue, and add silicon oxide wherein, the inserts such as aluminium oxide, to improve the intensity of encapsulating material, electrical property, the performances such as viscosity, and promote the thermomechanical reliability of encapsulating structure, encapsulating material is encapsulated, after having solidified, plastic packaging layer 5 in solid, shaped, can play waterproof, moistureproof, shockproof, dust-proof, insulation, the effects such as heat radiation.
Further, since the camber of described bonding line 3 can reach less than 60 μm, so, the thickness of described plastic packaging layer 5 can also reduce accordingly, in this enforcement, the thickness of described plastic packaging layer 5 can be less than 150 μm, consequently facilitating reduce the height of whole packaging body further.
Further, the bottom surface upside-down mounting of described ultra thin substrate 1 has lower chip 6, described lower chip 6 can also be known various types of chip and highly determine according to all types of chip parameter, in the present embodiment, the most described lower chip 6 is calculation process class chip, and the heat produced during its work is relatively big and its thickness is preferably 100 μm.
Simultaneously, described lower chip 6 is connected by some dimpling blocks 8 being positioned at bottom described ultra thin substrate with described ultra thin substrate 1 and communicates, described dimpling block 8 can be the various metals with excellent conductive performance, in the present embodiment, preferred described dimpling block 8 is gold goal or stannum ball, described dimpling block 8 is coated in the Underfill layer 9 bottom ultra thin substrate and between lower chip, the material of described Underfill layer 9 can be identical with the material of described plastic packaging layer, can also be different, in the present embodiment preferably, they materials are identical.
And, the bottom surface of described ultra thin substrate 1 is additionally provided with some stannum balls 7 for communicating with external devices, the size of the tin ball 7 can be arranged as required to, in the present embodiment, the height of preferred the tin ball 7 is 250 μm, simultaneously, need the bottom surface meeting described lower chip 6 to be positioned at the top of the tin ball minimum point place plane, be so in order to avoid lower chip 6 protrudes from the bottom of stannum ball thus causes lower chip easily damaged or problem that whole packaging body is difficult to be installed on other devices.
Although the heat produced when lower chip 6 works is more, but in open architecture of the present utility model, its heat produced can quickly discharge such that it is able to the effective problem solving prior art poor heat radiation.
Architectural characteristic due to the semiconductor device of above-mentioned ultra-thin 3D encapsulation, in its manufacturing process, owing to the shrinkage factor of the material of plastic packaging layer 5 correspondence is different from the shrinkage factor of resin substrate, the shrinkage factor of general resin substrate is little, the shrinkage factor of plastic packaging layer 5 is big, therefore after injection forms plastic packaging layer 5, described resin substrate there will be certain deformation warpage, now, owing to the size of described dimpling block 8 is the least, the most limited with the contact area of resin substrate, therefore on the resin substrate bottom surface of arc, contact area between dimpling block 8 and resin substrate is reduced further, cause being bonded stability cannot ensure, dimpling block 8 and resin substrate loose contact or the problem got loose easily occur, thus affect quality and the service life of the semiconductor product of ultra-thin 3D encapsulation.
In order to solve above-mentioned problem, inventor attempts at high temperature press against uncooled injected plastics material to prevent ultra thin substrate 1 from deforming with weight, weight is taken off after forming plastic packaging layer 5 Deng injected plastics material natural cooling, carry out again planting ball, but after planting chou bundle, ultra thin substrate 1 still there will be the problem of warpage, poor effect.
On the other hand, inventor further contemplates and uses the material that contraction ratio is close or identical to avoid the warpage issues of the different ultra thin substrate 1 caused of shrinkage factor of both materials to make ultra thin substrate 1 with forming plastic packaging layer 1, but cannot effectively find the material that two kinds of materials are close or identical to meet the processing request of above-mentioned semiconductor device, simultaneously need to spend substantial amounts of human and material resources, financial resources, the lowest.
For this kind of problem, this utility model further discloses the processing method of the semiconductor device of a kind of above-mentioned ultra-thin 3D encapsulation, this method is by overall package and by eliminating the internal stress of substrate by the way of plastic packaging layer 5 is carried out precut, thus solving the buckling deformation problem of ultra thin substrate, it specifically comprises the following steps that
S1, upper chip package step: according to specified layout mode, the end face of one piece of ultra thin substrate 1 is fixed the upper chip 2 of specified quantity, the described upper chip 2 laying form on described ultra thin substrate 1 can be side by side or side by side or according to array-like or according to cellular or according to latticed etc., the most described upper chip 2 is array-like layout, and such structure is easy to following process and improves working (machining) efficiency.
Further, described ultra thin substrate 1 devises corresponding distribution form and the circuit of quantity according to the distribution form of upper chip 2 and quantity；Then, making each upper chip 2 be connected communication with described ultra thin substrate 1, then the end face entirety plastic packaging of described ultra thin substrate 1 is formed plastic packaging layer 5, concrete, it comprises the steps: again
S11, chip attachment step: the end face at ultra thin substrate 1 carries out a Heraeus according to the determination position of chip 2 on each, and upper chip 2 is fitted at Heraeus, and described upper chip 2 is pasted onto the end face of described ultra thin substrate 1 by Heraeus.
S12, bonding line bonding steps: then, bonding line 3 is made to connect described ultra thin substrate 1 and upper chip 2 and realize communicating of they by reverse bonding technique, detailed, first chopper is placed on the bonding region of upper chip 2, make a call to a gold goal (bonding point), after forming gold goal, being the first solder joint according to the bonding point on ultra thin substrate 1, the order that bonding point is the second solder joint on upper chip 2 is bonded, i.e. first connecting key zygonema 3 and ultra thin substrate 1, then connecting key zygonema 3 and upper chip 2.
S13, cleaning step: will be through S12, the intermediate of bonding line bonding steps is inserted and is carried out decontamination in the plasma cleaning equipment specified.
S14, injection step: the end face integral molded plastic of the ultra thin substrate 1 through over cleaning is formed plastic packaging layer 5, even if plastic packaging layer 5 covers all of upper chip 2 and the bonding point corresponding with each upper chip and bonding line, preferably, described plastic packaging layer 5 is formed with horizontal plane for cutting plane the area of section, shape and the area of described ultra thin substrate, shape are identical.
Now, owing to the contraction situation of plastic packaging layer 5 wants notable relative to ultra thin substrate 1, therefore after plastic packaging layer 5 molding, ultra thin substrate 1 due to limited by the size of plastic packaging layer 5 and consequent pulling force and obvious warpage occurs, and ultra thin substrate 1 cannot realize the change of shape freely.
S2, cutting step: as shown in Figure 4, in order to eliminate the warpage issues of ultra thin substrate 1, by cutting knife, plastic packaging layer 5 is cut to stress release mechanism, and make each upper chip 2 plastic packaging layer region corresponding with it and ultra thin substrate form a semi-finished product monomer, and make to keep between the semi-finished product monomer of arbitrary neighborhood specified gap, preferably, gap between the semi-finished product monomer of arbitrary neighborhood is 0.2-0.3mm, more preferably about 0.25mm, described gap 12 i.e. constitutes stress release mechanism.
Certainly when cutting, the degree of depth thickness not less than described plastic packaging layer 5 of cutting should be controlled, extend on ultra thin substrate 1, but ensure not cut off by ultra thin substrate 1, now, described stress release mechanism is the breach 13 that the end face from plastic packaging layer 5 arranged between the semiconductor device 11 of the described ultra-thin 3D encapsulation of arbitrary neighborhood extends to ultra thin substrate 1.
After described plastic packaging layer 5 has been carried out cutting, described plastic packaging layer 5 is divided into several by the entirety that volume is bigger and is separated from each other and the monomer of small volume, the restriction freely changed the shape of whole ultra thin substrate due to the size of the monomer of each plastic packaging layer is substantially negligible, therefore, whole ultra thin substrate is no longer influenced by size and the restriction of pulling force of the plastic packaging layer 5 before not cutting, it is capable of Free Transform, it is thus possible to eliminate the warpage internal stress of ultra thin substrate 1, return to level, create conditions for follow-up lower flip-chip.
S3, stannum ball making step: make the stannum ball 7 mated with each semi-finished product monomer through the bottom surface of the ultra thin substrate 1 of cutting at plastic packaging layer 5, the quantity of the tin ball 7 and distribution form can be arranged according to actual needs.
S4, lower flip-chip step: the lower chip 6 mated with each semi-finished product monomer is arranged on by reverse installation process the bottom of described ultra thin substrate 1, detailed, on lower chip 6, first make stannum ball (dimpling block 8), then by lower chip upset heating stannum ball, the stannum ball of molten condition is utilized to realize lower chip 6 and the interconnection of ultra thin substrate 1.
Then, between lower chip 6 and ultra thin substrate 1, fill high-heat-conductivity glue body form the Underfill layer 9 covering described dimpling block 8, so that heat is easier to dissipate in encapsulation；The upside-down mounting of all lower chips 6 forms the semi-finished product 10 of the semiconductor device including that several ultra-thin 3D encapsulate after completing, now, the semiconductor device 11 of the described ultra-thin 3D encapsulation in described semi-finished product 10 is connected by common ultra thin substrate 1, and is provided with stress release mechanism between the semiconductor device 11 of the described ultra-thin 3D encapsulation of arbitrary neighborhood.
S5, cutting singulation step: according to the actual size requirement of the semiconductor device 11 of each ultra-thin 3D encapsulation, described semi-finished product 10 are cut into the semiconductor device 11 of the ultra-thin 3D encapsulation of respective amount, thus complete the making of the semiconductor device 11 of above-mentioned ultra-thin 3D encapsulation.
This utility model still has numerous embodiments, such as, in other embodiments, above-mentioned S3, stannum ball making step；S4, the order of lower flip-chip step also can overturn, all employing equivalents or equivalent transformation and all technical schemes of being formed, within all falling within protection domain of the present utility model.
Claims (9)
1. the semiconductor device of a ultra-thin 3D encapsulation, including ultra thin substrate (1), it is characterized in that: the end face of described ultra thin substrate (1) is provided with chip at least one (2), described upper chip (2) is connected and communicates with bonding point (4) with ultra thin substrate (1) by bonding line (3), and the end face of described ultra thin substrate (1) is additionally provided with the described upper chip (2) of parcel, bonding line (3) and the plastic packaging layer (5) of bonding point (4)；The bottom surface upside-down mounting of described ultra thin substrate (1) has lower chip (6), the bottom surface of described lower chip (6) to be positioned at the top of minimum point place plane of the stannum ball (7) that described ultra thin substrate (1) bottom surface is arranged.
The semiconductor device of a kind of ultra-thin 3D the most according to claim 1 encapsulation, it is characterised in that: described ultra thin substrate (1) is resin ultra thin substrate.
The semiconductor device of a kind of ultra-thin 3D the most according to claim 1 encapsulation, it is characterised in that: the camber of described bonding line (3) is less than 60mm.
The semiconductor device of a kind of ultra-thin 3D the most according to claim 1 encapsulation, it is characterised in that: the thickness of described plastic packaging layer (5) is less than 150 microns.
The semiconductor device of a kind of ultra-thin 3D the most according to claim 1 encapsulation, it is characterized in that: described lower chip (6) is connected by some dimpling blocks (8) being positioned at bottom described ultra thin substrate with described ultra thin substrate (1) and communicates, and described dimpling block (8) is coated in the Underfill layer (9) bottom ultra thin substrate and between lower chip.
The semiconductor device of a kind of ultra-thin 3D the most according to claim 5 encapsulation, it is characterised in that: described dimpling block (8) is gold goal or stannum ball.
7. the semi-finished product of the semiconductor device of a ultra-thin 3D encapsulation, it is characterized in that: include the semiconductor device (11) of the arbitrary described ultra-thin 3D encapsulation of several claim 1-6, the semiconductor device (11) of described ultra-thin 3D encapsulation is connected by common ultra thin substrate (1), and is provided with stress release mechanism between the semiconductor device (11) of the described ultra-thin 3D encapsulation of arbitrary neighborhood.
The semi-finished product of the semiconductor device of a kind of ultra-thin 3D the most according to claim 7 encapsulation, it is characterised in that: described stress release mechanism is the breach (13) that the end face from plastic packaging layer (5) arranged between the semiconductor device (11) of the described ultra-thin 3D encapsulation of gap (12) or the arbitrary neighborhood arranged between the plastic packaging layer (5) of the semiconductor device (11) of the described ultra-thin 3D encapsulation of arbitrary neighborhood extends to ultra thin substrate (1).
The semi-finished product of the semiconductor device of a kind of ultra-thin 3D the most according to claim 8 encapsulation, it is characterised in that: described gap (12) or the width of breach (13) they are 0.2-0.3mm.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105932017A (en) * | 2016-05-19 | 2016-09-07 | 苏州捷研芯纳米科技有限公司 | Ultrathin 3D-packaged semiconductor device and processing method thereof and semi-finished product in processing method |
| CN109378702A (en) * | 2018-11-30 | 2019-02-22 | 华天科技（西安）有限公司 | A kind of VCSEL sensor-packaging structure and its packaging method |
-
2016
- 2016-05-19 CN CN201620467787.7U patent/CN205609518U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105932017A (en) * | 2016-05-19 | 2016-09-07 | 苏州捷研芯纳米科技有限公司 | Ultrathin 3D-packaged semiconductor device and processing method thereof and semi-finished product in processing method |
| CN109378702A (en) * | 2018-11-30 | 2019-02-22 | 华天科技（西安）有限公司 | A kind of VCSEL sensor-packaging structure and its packaging method |
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Address after: Room 109C, Floor A4, No. 218, Xinghu Street, Suzhou Industrial Park, Jiangsu Province, 215123 Patentee after: Suzhou jieyanxin Electronic Technology Co.,Ltd. Address before: Room 109C, Floor A4, No. 218, Xinghu Street, Suzhou Industrial Park, Jiangsu Province, 215123 Patentee before: SUZHOU JIEYANXIN NANO TECHNOLOGY Co.,Ltd. |
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