CN205596129U - Chaos circuit of third -order on class lorentzen 4+2 type - Google Patents
Chaos circuit of third -order on class lorentzen 4+2 type Download PDFInfo
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- CN205596129U CN205596129U CN201620184585.1U CN201620184585U CN205596129U CN 205596129 U CN205596129 U CN 205596129U CN 201620184585 U CN201620184585 U CN 201620184585U CN 205596129 U CN205596129 U CN 205596129U
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Abstract
Chaos circuit of third -order on class lorentzen 4+2 type is including an operational amplifier circuit A, the 2nd operational amplifier circuit B and the 3rd operational amplifier circuit C, an operational amplifier circuit A's aX input, a3 input and an operational amplifier circuit A's output is connected with the 2nd operational amplifier circuit B's bX input and b1 input, and an operational amplifier circuit A's aY input and a2 input are connected with the 2nd operational amplifier circuit B's output, second operation amplifier circuit B's bY input and third operation amplifier circuit C's c2 output are connected, and third operation amplifier circuit C's c1 input and first operation amplifier circuit's a1 output are connected. The utility model discloses circuit structure is simple, can show above -mentioned various chaos signals on oscilloscope, through some specific resistance for example resistance R4 or resistance R6 replace the back by adjustable resistance, more than can changing the chaos characteristic of various chaos signals.
Description
Technical field
This utility model relates to chaos circuit optimisation technique field, specifically three rank class Lorentz 4+2
Type chaos circuit.
Background technology
Lorentz equation circuit is a circuit family, referred to as class lorentz equation circuit family, including long-range navigation
Hereby equation circuit, old pass Rong Fangcheng circuit, Lv Jin tiger equation circuit and other circuit large quantities of, its
Feature is to export the phasor of shape such as butterfly's wing shape.Existing can export upright butterfly's wing phase
The circuit of figure is made up of 6 operational amplifiers and 2 analog multipliers, is called for short 6+2 circuit；Other
Class lorentz equation circuit family is all made up of 5 or more than 5 operational amplifiers, and circuit structure is complicated,
Carry out easy circuit connection error during Chaotic Experiment, lose time, and it is unnecessary to add some
Cost, is the deficiency of existing chaos circuit technology.
Utility model content
The purpose of this utility model is to provide a kind of three rank class Lorentz 4+2 type chaos circuits, is used for solving
The problem that certainly existing Lorentz circuit structure is complicated.
The technical scheme in the invention for solving the technical problem is: three rank class Lorentz 4+2
Type chaos circuit, is characterized in that, including the first operational amplification circuit A, the second operational amplification circuit B and
3rd operational amplification circuit C；The aX input of described first operational amplification circuit A, a3 input and
The outfan of the first operational amplification circuit A and the bX input of the second operational amplification circuit B and b1 are defeated
Enter end to connect, the aY input of the first operational amplification circuit A and a2 input and the second operation amplifier
The outfan of circuit B connects；The bY input of the second operational amplification circuit B and the 3rd operation amplifier electricity
The c2 outfan of road C connects, the c1 input of the 3rd operational amplification circuit C and the first operation amplifier
The a1 outfan of circuit connects.
Further, the first described operational amplification circuit A include resistance R1, resistance R2, electric capacity C1,
Operational amplifier A 1 and analog multiplier M1；The inverting input of described operational amplifier A 1 is respectively
One end of connecting resistance R1, one end of resistance R2 and one end of electric capacity C1, operational amplifier A 1 same
Phase input end grounding, electric capacity C1 another termination outfan of operational amplifier A 1, resistance R1 another
The aX input of one end and analog multiplier M1, another termination analog multiplier M1's of resistance R2
AY input, the outfan of operational amplifier A 1 is X1 outfan.
Further, described analog multiplier M1 includes that AD633CN, operational amplifier A 1 include
TL082 or TL084.
Further, the second described operational amplification circuit B include resistance R3, resistance R4, electric capacity C2,
Operational amplifier A 2 and analog multiplier M2；The anti-phase input terminating resistor of described operational amplifier A 2
One end of R3, one end of resistance R4 and one end of electric capacity C2, the in-phase input end of operational amplifier A 2
Ground connection, another termination outfan of operational amplifier A 2, the aY of analog multiplier M1 of electric capacity C2
Input and the other end of resistance R2, the aX input of another termination analog multiplier M1 of resistance R3
End and the bX input of analog multiplier M2, another termination analog multiplier M2's of resistance R4 is defeated
Go out end；The outfan of operational amplifier A 2 is X2 outfan.
Further, described resistance R4 includes that variable resistance, analog multiplier M2 include AD633CN,
Operational amplifier A 2 includes TL082 or TL084.
Further, the 3rd described operational amplification circuit C include resistance R5, resistance R6, resistance R7,
Resistance R8, electric capacity C3, operational amplifier A 3 and operational amplifier A 4；Described operational amplifier A 3
One end of anti-phase input terminating resistor R5, one end of resistance R6 and one end of electric capacity C3, computing is put
The in-phase input end ground connection of big device A3, the outfan of another termination analog multiplier M1 of resistance R6,
The outfan of another termination operational amplifier A 3 of the resistance R5 other end and electric capacity C3, operational amplifier
One end of the anti-phase input terminating resistor R7 of A4 and one end of resistance R8, the homophase of operational amplifier A 4
Input end grounding, the outfan of another termination operational amplifier A 3 of resistance R7, another of resistance R8
The outfan of termination operational amplifier A 4, the output termination analog multiplier M2's of operational amplifier A 4
BY input, the outfan of operational amplifier A 3 is X3 outfan.
Further, described resistance R6 includes variable resistance, operational amplifier A 3 and operation amplifier
Device A4 includes TL082 or TL084.
The beneficial effects of the utility model are: the one three rank deformation Lorentz that this utility model provides
4+2 type chaos circuit, can export X1, X2 by 4 operational amplifiers and two analog multipliers
With tri-chaotic waves signals of X3 and X1-X2, X1-X3 and tri-chaos phasors of X2-X3；Can be
Above-mentioned various chaotic signal is shown on oscillograph；By the resistance of some specific electrical resistance such as resistance R4 or
After resistance R6 is replaced by variable resistance, thus it is possible to vary the chaotic characteristic of the above various chaotic signal,
The various curves of three rank deformation Lorentz 4+2 type chaos circuits can be shown on oscillograph.This practicality
Novel circuit configuration is simple, can export upright butterfly's wing phasor, simplify line connecting relation,
Save hardware cost, it is adaptable to university's chaos education of science, experimental teaching and demonstration, scientific popularization
And experimental demonstration etc..
Accompanying drawing explanation
Fig. 1 is circuit theory diagrams of the present utility model；
Fig. 2 is X1 oscillogram of the present utility model；
Fig. 3 is X2 oscillogram of the present utility model；
Fig. 4 is X3 oscillogram of the present utility model；
Fig. 5 is that X1-X2 of the present utility model exports phasor；
Fig. 6 is that X1-X3 of the present utility model exports phasor；
Fig. 7 is that X2-X3 of the present utility model exports phasor.
Detailed description of the invention
As shown in Figures 1 to 7, this utility model includes that the first operational amplification circuit A, the second computing are put
Big circuit B and the 3rd operational amplification circuit C；The aX input of the first operational amplification circuit A, a3 are defeated
Enter end and the outfan of the first operational amplification circuit A and the bX input of the second operational amplification circuit B and
B1 input connects, the aY input of the first operational amplification circuit A and a2 input and the second computing
The outfan of amplifying circuit B connects；BY input and the 3rd computing of the second operational amplification circuit B are put
The c2 outfan of big circuit C connects, the c1 input of the 3rd operational amplification circuit C and the first computing
The a1 outfan of amplifying circuit connects.
As it is shown in figure 1, the first operational amplification circuit A includes resistance R1, resistance R2, electric capacity C1, TL082
Operational amplifier A 1 and AD633CN analog multiplier M1；TL082 operational amplifier A 1 anti-phase defeated
Enter end one end of connecting resistance R1, one end of resistance R2 and one end of electric capacity C1, TL082 computing respectively
The in-phase input end ground connection of amplifier A1, another termination TL082 operational amplifier A 1 of electric capacity C1
Outfan, the other end of resistance R1 and the aX input of AD633CN analog multiplier M1, resistance R2
Another termination AD633CN analog multiplier M1 aY input, TL082 operational amplifier A 1
Outfan is X1 outfan.
Second operational amplification circuit B includes resistance R3, resistance R4, electric capacity C2, TL082 operation amplifier
Device A2 and AD633CN analog multiplier M2；The anti-phase input termination electricity of TL082 operational amplifier A 2
Resistance one end of R3, one end of resistance R4 and one end of electric capacity C2, TL082 operational amplifier A 2 same
Phase input end grounding, another termination outfan of TL082 operational amplifier A 2, the AD633CN of electric capacity C2
The aY input of analog multiplier M1 and the other end of resistance R2, another termination AD633CN of resistance R3
The aX input of analog multiplier M1 and the bX input of AD633CN analog multiplier M2, resistance
The outfan of another termination AD633CN analog multiplier M2 of R4；TL082 operational amplifier A 2
Outfan is X2 outfan.
3rd operational amplification circuit C includes resistance R5, resistance R6, resistance R7, resistance R8, electric capacity
C3, TL082 operational amplifier A 3 and TL082 operational amplifier A 4；TL082 operational amplifier A 3
One end of anti-phase input terminating resistor R5, one end of resistance R6 and one end of electric capacity C3, TL082 transports
Calculate the in-phase input end ground connection of amplifier A3, another termination AD633CN analog multiplier of resistance R6
The outfan of M1, another termination TL082 operational amplifier A 3 of the resistance R5 other end and electric capacity C3
Outfan, one end of the anti-phase input terminating resistor R7 of TL082 operational amplifier A 4 and resistance R8's
One end, the in-phase input end ground connection of TL082 operational amplifier A 4, another termination TL082 of resistance R7
The outfan of operational amplifier A 3, the output of another termination TL082 operational amplifier A 4 of resistance R8
End, the bY input of the output termination AD633CN analog multiplier M2 of TL082 operational amplifier A 4,
The outfan of TL082 operational amplifier A 3 is X3 outfan.
Operational amplifier of the present utility model may be used without TL084 operational amplifier, it is possible to realize with
The effect that TL082 operational amplifier is identical.
Make C1=C2=C3=0.01uF, R1=R2=R7=R8=10K Ω, R3=2.2K Ω, R5=27K Ω,
Resistance R4 and resistance R6 is variable resistance, and debugging is 510 Ω to R4, and R6 is 2K Ω, and X1 is defeated
Go out end and connect oscillograph, export the oscillogram of X1 as in figure 2 it is shown, X2 outfan is connected oscillograph,
The oscillogram of output X2 as it is shown on figure 3, connect oscillograph, the oscillogram of output X3 by X3 outfan
As shown in Figure 4, X1 and X2 outfan is connected oscillograph, phasor such as Fig. 5 institute of output X1-X2
Show, X1 and X3 outfan is connected oscillograph, export the phasor of X1-X3 as shown in Figure 6, by X2
Connecting oscillograph with X3 outfan, the phasor of output X2-X3 is as shown in Figure 7.
Although detailed description of the invention of the present utility model is described by the above-mentioned accompanying drawing that combines, but not
Restriction to this utility model protection domain, on the basis of the technical solution of the utility model, ability
Field technique personnel need not to pay various amendments or deformation that creative work can make still in this practicality
Within novel protection domain.
Claims (7)
1. three rank class Lorentz 4+2 type chaos circuits, is characterized in that, including the first operational amplification circuit
A, the second operational amplification circuit B and the 3rd operational amplification circuit C；Described first operational amplification circuit A
AX input, a3 input and the outfan of the first operational amplification circuit A and the second operation amplifier electricity
The bX input of road B and b1 input connect, the aY input of the first operational amplification circuit A and a2
The outfan of input and the second operational amplification circuit B connects；The bY of the second operational amplification circuit B is defeated
Enter end to be connected with the c2 outfan of the 3rd operational amplification circuit C, the c1 of the 3rd operational amplification circuit C
The a1 outfan of input and the first operational amplification circuit connects.
Three rank class Lorentz 4+2 type chaos circuits the most according to claim 1, is characterized in that,
The first described operational amplification circuit A includes resistance R1, resistance R2, electric capacity C1, operational amplifier
A1 and analog multiplier M1；The inverting input of described operational amplifier A 1 connecting resistance R1's respectively
One end, one end of resistance R2 and one end of electric capacity C1, the in-phase input end ground connection of operational amplifier A 1,
Another termination outfan of operational amplifier A 1, the other end of resistance R1 and the analogue multiplication of electric capacity C1
The aX input of device M1, the aY input of another termination analog multiplier M1 of resistance R2, computing
The outfan of amplifier A1 is X1 outfan.
Three rank deformation Lorentz 4+2 type chaos circuits the most according to claim 2, is characterized in that,
Described analog multiplier M1 includes that AD633CN, operational amplifier A 1 include TL082 or TL084.
Three rank deformation Lorentz 4+2 type chaos circuits the most according to claim 2, is characterized in that,
The second described operational amplification circuit B includes resistance R3, resistance R4, electric capacity C2, operational amplifier
A2 and analog multiplier M2；One end of the anti-phase input terminating resistor R3 of described operational amplifier A 2,
One end of resistance R4 and one end of electric capacity C2, the in-phase input end ground connection of operational amplifier A 2, electric capacity
Another termination outfan of operational amplifier A 2, the aY input of analog multiplier M1 and the resistance of C2
The other end of R2, the aX input of another termination analog multiplier M1 of resistance R3 and analog multiplier
The bX input of M2, the outfan of another termination analog multiplier M2 of resistance R4；Operational amplifier
The outfan of A2 is X2 outfan.
Three rank deformation Lorentz 4+2 type chaos circuits the most according to claim 4, is characterized in that,
Described resistance R4 includes that variable resistance, analog multiplier M2 include AD633CN, operational amplifier
A2 includes TL082 or TL084.
Three rank deformation Lorentz 4+2 type chaos circuits the most according to claim 4, is characterized in that,
The 3rd described operational amplification circuit C includes resistance R5, resistance R6, resistance R7, resistance R8, electricity
Hold C3, operational amplifier A 3 and operational amplifier A 4；The anti-phase input of described operational amplifier A 3
One end of terminating resistor R5, one end of resistance R6 and one end of electric capacity C3, operational amplifier A 3
In-phase input end ground connection, the outfan of another termination analog multiplier M1 of resistance R6, resistance R5 is another
The outfan of another termination operational amplifier A 3 of one end and electric capacity C3, operational amplifier A 4 anti-phase
One end of input connecting resistance R7 and one end of resistance R8, the in-phase input end of operational amplifier A 4 connects
Ground, the outfan of another termination operational amplifier A 3 of resistance R7, another termination computing of resistance R8
The outfan of amplifier A4, the bY input of the output termination analog multiplier M2 of operational amplifier A 4
End, the outfan of operational amplifier A 3 is X3 outfan.
Three rank deformation Lorentz 4+2 type chaos circuits the most according to claim 6, is characterized in that,
Described resistance R6 includes that variable resistance, operational amplifier A 3 and operational amplifier A 4 include TL082
Or TL084.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620184585.1U CN205596129U (en) | 2016-03-10 | 2016-03-10 | Chaos circuit of third -order on class lorentzen 4+2 type |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620184585.1U CN205596129U (en) | 2016-03-10 | 2016-03-10 | Chaos circuit of third -order on class lorentzen 4+2 type |
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| Publication Number | Publication Date |
|---|---|
| CN205596129U true CN205596129U (en) | 2016-09-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620184585.1U Expired - Fee Related CN205596129U (en) | 2016-03-10 | 2016-03-10 | Chaos circuit of third -order on class lorentzen 4+2 type |
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| Country | Link |
|---|---|
| CN (1) | CN205596129U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634726A (en) * | 2016-03-10 | 2016-06-01 | 河西学院 | Three-order Lorenz 4 + 2 type chaotic circuit |
-
2016
- 2016-03-10 CN CN201620184585.1U patent/CN205596129U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634726A (en) * | 2016-03-10 | 2016-06-01 | 河西学院 | Three-order Lorenz 4 + 2 type chaotic circuit |
| CN105634726B (en) * | 2016-03-10 | 2018-09-14 | 河西学院 | Three rank class Lorentz 4+2 type chaos circuits |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160921 Termination date: 20170310 |