CN105591735B - Quadravalence class Lorentz 5+2 type hyperchaotic circuits - Google Patents
Quadravalence class Lorentz 5+2 type hyperchaotic circuits Download PDFInfo
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- CN105591735B CN105591735B CN201610136078.5A CN201610136078A CN105591735B CN 105591735 B CN105591735 B CN 105591735B CN 201610136078 A CN201610136078 A CN 201610136078A CN 105591735 B CN105591735 B CN 105591735B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
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Abstract
Quadravalence class Lorentz 5+2 type hyperchaotic circuits, including the first operational amplification circuit A, the second operational amplification circuit B, third operational amplification circuit C and the 4th operational amplification circuit D；The a1 input terminals of first operational amplification circuit A are connect with the output end of the 4th operational amplification circuit D, the output end of the aX input terminals of first operational amplification circuit A, a4 input terminals and the first operational amplification circuit A is connect with the bX input terminals of the second operational amplification circuit B and b1 input terminals respectively, and the output end of the aY input terminals of the first operational amplification circuit A, a3 input terminals and the second operational amplification circuit B is connect with the d1 input terminals of the 4th operational amplification circuit D；The bY input terminals of second operational amplification circuit B are connect with the c2 output ends of third operational amplification circuit C, and the c1 input terminals of third operational amplification circuit C are connect with the a2 output ends of the first operational amplification circuit A.The configuration of the present invention is simple can export 6 phasors and the double vortex chaotic signals of quadravalence.
Description
Technical field
The present invention relates to chaos circuit technical field, specifically a kind of quadravalence class Lorentz 5+2 type hyperchaotic circuits.
Background technology
Class lorentz equation circuit is chaos circuit, can export upright butterfly's wing shape phasor；Existing simulation electricity
Road is usually made of 5 operational amplifiers and 2 analog multipliers, but can only export 3 chaotic waves figures and 3 chaos phases
Figure, for circuit structure in the case of same complicated, the advantageous effect of realization is relatively backward, can not meet and need output six two
The case where tieing up chaos phasor, such as certain butterfly's wing phasors to skew can not export, if the prior art will export six two
Chaos phasor is tieed up, be bound to circuit structure to be increased, and can so that circuit is more complicated, and wiring mistake is susceptible in Experiment of Electrical Circuits
Accidentally, it is the deficiency of existing chaos circuit technology.
Invention content
The purpose of the present invention is to provide a kind of quadravalence class Lorentz 5+2 type hyperchaotic circuits, for solving existing chaos
Circuit cannot steadily export the problem of quadravalence pair vortex chaotic signal.
The technical scheme adopted by the invention to solve the technical problem is that：Quadravalence class Lorentz 5+2 type hyperchaotic circuits,
It is characterized in, including the first operational amplification circuit A, the second operational amplification circuit B, third operational amplification circuit C and the 4th operation are put
Big circuit D；The a1 input terminals of the first operational amplification circuit A are connect with the output end of the 4th operational amplification circuit D, and first
The output of the aX input terminals of operational amplification circuit A, the a4 input terminals of the first operational amplification circuit A and the first operational amplification circuit A
End is connect with the bX input terminals of the second operational amplification circuit B and b1 input terminals respectively, the aY inputs of the first operational amplification circuit A
It holds, the output end and the 4th operational amplification circuit D of the a3 input terminals of the first operational amplification circuit A and the second operational amplification circuit B
D1 input terminals connection；The bY input terminals of second operational amplification circuit B are connect with the c2 output ends of third operational amplification circuit C,
The c1 input terminals of third operational amplification circuit C are connect with the a2 output ends of the first operational amplification circuit A.
Further, the first operational amplification circuit A include operational amplifier A 1, analog multiplier M1, resistance R1,
Resistance R2, resistance R11 and capacitance C1；The inverting input of the operational amplifier A 1 respectively with one end of resistance R1, resistance
One end of R2, one end of resistance R11 are connected with one end of capacitance C1, the other end of resistance R1, the other end of capacitance C1 and simulation
The aX input terminals of multiplier M1 are connected with the output end of operational amplifier A 1, and the output end of operational amplifier A 1 is that the first operation is put
The X1 output ends of big circuit A.
Further, the operational amplifier A 1 includes TL082, and analog multiplier M1 includes M1AD633CN.
Further, the second operational amplification circuit B include operational amplifier A 2, analog multiplier M2, resistance R3,
Resistance R4 and capacitance C2；The inverting input of the operational amplifier A 2 respectively with one end of resistance R3, resistance R4 one end and
One end of capacitance C2 is connected, the other end of the resistance R3 aX with the bX input terminals and analog multiplier M1 of analog multiplier M2 respectively
Input terminal is connected, the output end of another termination analog multiplier M2 of resistance R4, the other end and operational amplifier A 2 of capacitance C2
Output end distinguish the first operational amplification circuit A a3 input terminals and the first operational amplification circuit A aY input terminals be connected, it is described
The output end of operational amplifier A 2 is the output end of the second operational amplification circuit B.
Further, the operational amplifier A 2 includes TL082, and analog multiplier M2 includes M1AD633CN.
Further, the third operational amplification circuit C include operational amplifier A 3, operational amplifier A 4, resistance R7,
Resistance R8, resistance R5, resistance R6 and capacitance C3；The inverting input of the operational amplifier A 4 respectively with one end of resistance R7 and
One end of resistance R8 is connected, the bY input terminals of the other end of resistance R8 and the output end of operational amplifier A 4 and analog multiplier M2
It is connected, the other end of resistance R7 is connected with the output end of one end of resistance R5, one end of capacitance C3 and operational amplifier A 3 respectively,
One end of the other end of resistance R5, the other end of capacitance C3 and resistance R6 respectively with the inverting input phase of operational amplifier A 3
Even, the other end of resistance R6 is connected with the a2 output ends of the first operational amplification circuit A, and the output end of the operational amplifier A 3 is
The X3 output ends of third operational amplification circuit C.
Further, the operational amplifier A 3 and operational amplifier A 4 include TL082.
Further, the 4th operational amplification circuit D includes operational amplifier A 5, resistance R10, resistance R9 and capacitance
C4；The inverting input of the operational amplifier A 5 respectively with one end of resistance R10, one end of one end of resistance R9 and capacitance C4
It is connected, the other end of resistance R10 and the other end of capacitance C4 are connected with the output end of operational amplifier A 5, the other end of resistance R9
It is connected respectively with the a3 input terminals of the first operational amplification circuit A and aY input terminals, the output end of operational amplifier A 5 and the first fortune
The a1 input terminals for calculating amplifying circuit A are connected, and the X4 that the output end of the operational amplifier A 5 is the 4th operational amplification circuit D is exported
End.
Further, the operational amplifier A 5 includes TL082.
The beneficial effects of the invention are as follows：A kind of quadravalence class Lorentz 5+2 types hyperchaotic circuit provided by the invention can be defeated
Go out six chaos phasors of X1-X2, X1-X3, X1-X4, X2-X3, X2-X4 and X3-X4；It can be shown on oscillograph above-mentioned various
Chaotic signal；It, can be with by certain specific electrical resistances after for example the 4th resistance (R4) or the 6th resistance (R6) are replaced by variable resistance
The chaotic characteristic for changing various chaotic signals described above, can show quadravalence class Lorentz 5+2 type hyperchaos on oscillograph
The various curves of circuit can also carry out various other experiments of quadravalence class Lorentz 5+2 type hyperchaotic circuits, with the prior art
It compares, under identical circuit structure, the prior art can only export 3 oscillograms and 3 two-dimentional phasors, and this patent can be defeated
Go out six two-dimentional phasors, upright butterfly's wing phasor can not only be exported, other phasors can also be exported, enrich technology at
Fruit simplifies circuit, the problem of being easy to happen wiring error when avoiding wiring connection, be suitable for university's chaos education of science,
Experimental teaching and demonstration, scientific popularization experimental demonstration etc..
Description of the drawings
Fig. 1 is the circuit diagram of the present invention；
Fig. 2 is that the X1-X2 of the present invention exports phasor；
Fig. 3 is that the X1-X3 of the present invention exports phasor；
Fig. 4 is that the X1-X4 of the present invention exports phasor；
Fig. 5 is that the X2-X3 of the present invention exports phasor；
Fig. 6 is that the X2-X4 of the present invention exports phasor；
Fig. 7 is that the X3-X4 of the present invention exports phasor.
Specific implementation mode
As shown in Figures 1 to 7, the present invention includes the first operational amplification circuit A, the second operational amplification circuit B, third operation
Amplifying circuit C and the 4th operational amplification circuit D.
As shown in Figure 1, the a1 input terminals of the first operational amplification circuit A are connect with the output end of the 4th operational amplification circuit D,
The aX input terminals of first operational amplification circuit A, the a4 input terminals of the first operational amplification circuit A and the first operational amplification circuit A
Output end is connect with the bX input terminals of the second operational amplification circuit B and b1 input terminals respectively, and the aY of the first operational amplification circuit A is defeated
Enter to hold, the output end and the 4th operational amplification circuit of the a3 input terminals of the first operational amplification circuit A and the second operational amplification circuit B
The d1 input terminals of D connect；The bY input terminals of second operational amplification circuit B are connect with the c2 output ends of third operational amplification circuit C,
The c1 input terminals of third operational amplification circuit C are connect with the a2 output ends of the first operational amplification circuit A.
First operational amplification circuit A include TL082 operational amplifier As 1, M1AD633CN analog multipliers M1, resistance R1,
Resistance R2, resistance R11 and capacitance C1；The inverting input of the TL082 operational amplifier As 1 respectively with one end of resistance R1,
One end of resistance R2, one end of resistance R11 are connected with one end of capacitance C1, the other end of resistance R1, the other end of capacitance C1 and
The aX input terminals of M1AD633CN analog multipliers M1 are connected with the output end of TL082 operational amplifier As 1, TL082 operation amplifiers
The output end of device A1 is the X1 output ends of the first operational amplification circuit A.
Second operational amplification circuit B include TL082 operational amplifier As 2, M1AD633CN analog multipliers M2, resistance R3,
Resistance R4 and capacitance C2；The inverting input of TL082 operational amplifier As 2 respectively with one end of resistance R3, resistance R4 one end and
One end of capacitance C2 is connected, the other end of resistance R3 respectively with the bX input terminals of M1AD633CN analog multipliers M2 and
The aX input terminals of M1AD633CN analog multipliers M1 are connected, and another termination M1AD633CN analog multipliers M2's of resistance R4 is defeated
Outlet, the other end of capacitance C2 and the output end of TL082 operational amplifier As 2 distinguish the a3 input terminals of the first operational amplification circuit A
It is connected with the aY input terminals of the first operational amplification circuit A, the output end of TL082 operational amplifier As 2 is the second operational amplification circuit
The output end of B.
Third operational amplification circuit C includes TL082 operational amplifier As 3, TL082 operational amplifier As 4, resistance R7, resistance
R8, resistance R5, resistance R6 and capacitance C3；The inverting input of the TL082 operational amplifier As 4 one end with resistance R7 respectively
It is connected with one end of resistance R8, the other end of resistance R8 and the output end of TL082 operational amplifier As 4 multiply with M1AD633CN simulations
The bY input terminals of musical instruments used in a Buddhist or Taoist mass M2 are connected, the other end of resistance R7 respectively with one end of resistance R5, one end of capacitance C3 and TL082 operations
The output end of amplifier A3 is connected, and one end of the other end of resistance R5, the other end of capacitance C3 and resistance R6 is transported with TL082 respectively
The inverting input for calculating amplifier A3 is connected, and the other end of resistance R6 is connected with the a2 output ends of the first operational amplification circuit A,
The output end of TL082 operational amplifier As 3 is the X3 output ends of third operational amplification circuit C.
4th operational amplification circuit D includes operational amplifier A 5, resistance R10, resistance R9 and capacitance C4；TL082 operations are put
The inverting input of big device A5 is connected with one end of one end of resistance R10, one end of resistance R9 and capacitance C4 respectively, resistance R10
The other end and the other end of capacitance C4 be connected with the output end of TL082 operational amplifier As 5, the other end of resistance R9 respectively with
The a3 input terminals of first operational amplification circuit A are connected with aY input terminals, the output end of TL082 operational amplifier As 5 and the first operation
The a1 input terminals of amplifying circuit A are connected, and the X4 that the output end of TL082 operational amplifier As 5 is the 4th operational amplification circuit D is exported
End.
It is observed using the phasor mode of oscillograph, X1-X2 output end phasor signals are as shown in Fig. 2, X1-X3 output end phasors
Signal as shown in figure 3, X1-X4 output end phasor signals as shown in figure 4, X2-X3 output end phasor signals as shown in figure 5, X2-X4
Output end phasor signal is as shown in fig. 6, X3-X4 output end phasor signals are as shown in Figure 7.By Fig. 2 to Fig. 7, it was demonstrated that the present invention
Validity.
When resistance R4 and resistance R6 are changed to variable resistance, change the resistance value of resistance R4 and resistance R6, can observe
The various curves that chaos develops.
The operational amplifier of the present invention can also use TL084 operational amplifiers, may be implemented and TL082 operational amplifiers
Identical effect.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, based on the technical solutions of the present invention, those skilled in the art, which need not make the creative labor, to be done
The various modifications or changes gone out are still within protection scope of the present invention.
Claims (5)
1. quadravalence class Lorentz 5+2 type hyperchaotic circuits, characterized in that including the first operational amplification circuit A, the second operation amplifier
Circuit B, third operational amplification circuit C and the 4th operational amplification circuit D；The a1 input terminals of the first operational amplification circuit A
It is connect with the output end of the 4th operational amplification circuit D, the aX input terminals of the first operational amplification circuit A, the first operational amplification circuit A
A4 input terminals and the first operational amplification circuit A output end it is defeated with the bX input terminals of the second operational amplification circuit B and b1 respectively
Enter end connection, the aY input terminals of the first operational amplification circuit A, the a3 input terminals of the first operational amplification circuit A and the second operation are put
The output end of big circuit B is connect with the d1 input terminals of the 4th operational amplification circuit D；The bY input terminals of second operational amplification circuit B
It is connect with the c2 output ends of third operational amplification circuit C, the c1 input terminals of third operational amplification circuit C and the first operation amplifier electricity
The a2 output ends of road A connect；
The first operational amplification circuit A includes operational amplifier A 1, analog multiplier M1, resistance R1, resistance R2, resistance
R11 and capacitance C1；The inverting input of the operational amplifier A 1 respectively with one end of resistance R1, one end of resistance R2, electricity
Resistance R11 one end be connected with one end of capacitance C1, the other end of resistance R1, the other end and analog multiplier M1 of capacitance C1 aX
Input terminal is connected with the output end of operational amplifier A 1, and the output end of operational amplifier A 1 is the X1 of the first operational amplification circuit A
Output end；
The second operational amplification circuit B includes operational amplifier A 2, analog multiplier M2, resistance R3, resistance R4 and capacitance
C2；The inverting input of the operational amplifier A 2 respectively with one end of resistance R3, one end of one end of resistance R4 and capacitance C2
It is connected, the other end of resistance R3 is connected with the aX input terminals of the bX input terminals of analog multiplier 2 and analog multiplier M1 respectively, electricity
Hinder the output end of another termination analog multiplier M2 of R4, the output end difference of the other end of capacitance C2 and operational amplifier A 2 the
The aY input terminals of the a3 input terminals of one operational amplification circuit A and the first operational amplification circuit A are connected, the operational amplifier A 2
Output end is the output end of the second operational amplification circuit B；
The third operational amplification circuit C includes operational amplifier A 3, operational amplifier A 4, resistance R7, resistance R8, resistance
R5, resistance R6 and capacitance C3；The inverting input of the operational amplifier A 4 respectively with one end of resistance R7 and resistance R8 one
End is connected, and the other end of resistance R8 and the output end of operational amplifier A 4 are connected with the bY input terminals of analog multiplier M2, resistance
The other end of R7 is connected with the output end of one end of resistance R5, one end of capacitance C3 and operational amplifier A 3 respectively, resistance R5's
One end of the other end, the other end of capacitance C3 and resistance R6 is connected with the inverting input of operational amplifier A 3 respectively, resistance R6
The other end be connected with the a2 output ends of the first operational amplification circuit A, the output end of the operational amplifier A 3 is third operation
The X3 output ends of amplifying circuit C；
The 4th operational amplification circuit D includes operational amplifier A 5, resistance R10, resistance R9 and capacitance C4；The operation is put
The inverting input of big device A5 is connected with one end of one end of resistance R10, one end of resistance R9 and capacitance C4 respectively, resistance R10
The other end and the other end of capacitance C4 be connected with the output end of operational amplifier A 5, the other end of resistance R9 respectively with the first fortune
The a3 input terminals for calculating amplifying circuit A are connected with aY input terminals, the output end of operational amplifier A 5 and the first operational amplification circuit A's
A1 input terminals are connected, and the output end of the operational amplifier A 5 is the X4 output ends of the 4th operational amplification circuit D.
2. quadravalence class Lorentz 5+2 type hyperchaotic circuits according to claim 1, characterized in that the operation amplifier
Device A1 includes TL082, and analog multiplier M1 includes M1AD633CN.
3. quadravalence class Lorentz 5+2 type hyperchaotic circuits according to claim 1, characterized in that the operation amplifier
Device A2 includes TL082, and analog multiplier M2 includes M1AD633CN.
4. quadravalence class Lorentz 5+2 type hyperchaotic circuits according to claim 1, characterized in that the operation amplifier
Device A3 and operational amplifier A 4 include TL082.
5. quadravalence class Lorentz 5+2 type hyperchaotic circuits according to claim 1, characterized in that the operation amplifier
Device A5 includes TL082.
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| CN201610136078.5A CN105591735B (en) | 2016-03-10 | 2016-03-10 | Quadravalence class Lorentz 5+2 type hyperchaotic circuits |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108667597B (en) * | 2018-04-28 | 2020-09-29 | 河西学院 | Third-order Lorentz 3+ 2-like circuit |
| CN109167659A (en) * | 2018-10-31 | 2019-01-08 | 张剑锋 | One type Lorentz 8+4 type chaotic secret communication circuit |
| CN109215458A (en) * | 2018-10-31 | 2019-01-15 | 张剑锋 | A kind of three rank class Lorentz 3+2 type chaos circuits |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373563A (en) * | 2008-08-01 | 2009-02-25 | 张新国 | Lorentz chaos circuit |
| CN102663496A (en) * | 2012-03-23 | 2012-09-12 | 山东外国语职业学院 | Four-order neural-network hyper-chaotic circuit |
| CN103021239A (en) * | 2012-12-07 | 2013-04-03 | 山东外国语职业学院 | Fifth-order tsai hyperchaotic circuit |
| CN103036673A (en) * | 2012-12-07 | 2013-04-10 | 山东外国语职业学院 | Eight-operational amplifier five-order hyper chaotic circuit |
| CN103049790A (en) * | 2012-12-07 | 2013-04-17 | 山东外国语职业学院 | Novel four-order neural network hyperchaotic circuit |
| CN104468088A (en) * | 2014-12-17 | 2015-03-25 | 山东外国语职业学院 | Fourth-order eight-wing six plus three type hyperchaotic circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205596127U (en) * | 2016-03-10 | 2016-09-21 | 熊丽 | Super chaos circuit of quadravalence class lorentzen 5+2 type |
-
2016
- 2016-03-10 CN CN201610136078.5A patent/CN105591735B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373563A (en) * | 2008-08-01 | 2009-02-25 | 张新国 | Lorentz chaos circuit |
| CN102663496A (en) * | 2012-03-23 | 2012-09-12 | 山东外国语职业学院 | Four-order neural-network hyper-chaotic circuit |
| CN103021239A (en) * | 2012-12-07 | 2013-04-03 | 山东外国语职业学院 | Fifth-order tsai hyperchaotic circuit |
| CN103036673A (en) * | 2012-12-07 | 2013-04-10 | 山东外国语职业学院 | Eight-operational amplifier five-order hyper chaotic circuit |
| CN103049790A (en) * | 2012-12-07 | 2013-04-17 | 山东外国语职业学院 | Novel four-order neural network hyperchaotic circuit |
| CN104468088A (en) * | 2014-12-17 | 2015-03-25 | 山东外国语职业学院 | Fourth-order eight-wing six plus three type hyperchaotic circuit |
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Effective date of registration: 20180926 Address after: No. 846 North Ring Road, Zhangye, Gansu Province Applicant after: Hexi University, Gansu, China Address before: 734000 School of physics and mechatronics, He Xi University, Zhangye, Gansu Applicant before: Xiong Li |
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