CN205584194U - DMR data signal transfer circuit - Google Patents
DMR data signal transfer circuit Download PDFInfo
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- CN205584194U CN205584194U CN201620306429.8U CN201620306429U CN205584194U CN 205584194 U CN205584194 U CN 205584194U CN 201620306429 U CN201620306429 U CN 201620306429U CN 205584194 U CN205584194 U CN 205584194U
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- 238000012546 transfer Methods 0.000 title abstract description 6
- 230000005540 biological transmission Effects 0.000 claims abstract description 9
- 238000012545 processing Methods 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000004891 communication Methods 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 238000003786 synthesis reaction Methods 0.000 abstract 2
- 238000011161 development Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
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Abstract
The utility model relates to the field of communication technology, concretely relates to DMR data signal transfer circuit, a DMR data signal transfer circuit, it handles to receive the phase locking of PLL frequency synthesis circuit receive frequency, it provides a stable frequency for receiving circuit to receive the VCO circuit, the signal that receiving circuit receiving antenna comes in carries out the mixing with the frequency signal that receipt VCO circuit provided, it carries out signal processing for the DMR circuit to export a mixing signal, stable frequency of transmission PLL frequency synthesis circuit control transmission VCO circuit output, transmission VCO circuit is exported a carrier signal through frequency modulation and is given the transmitting circuit make high frequency carrier signal for the data signal who sends the DMR circuit here on, the carrier signal that transmission VCO circuit was sent here to the transmitting circuit launches through the antenna after amplifying, and MCU control circuit coordinates whole circuit. The utility model discloses can improve radio resource management's utilization ratio.
Description
Technical field
This utility model relates to communication technical field, is specifically related to shifting circuit in a kind of DMR digital signal.
Background technology
Development along with radio communication technology, people have had higher requirement to the quality of radio communication, but Radio Spectrum Resource lacks the most day by day, the appearance of digital handset, provide more rich, open, powerful use type and user's request, such as DMR trunked communication system uses TDMA technology based on 2 time slots, each road wireless carrier arranges 2 time slots on uplink and downlink link, every time slot 30ms, each time slot can be as independent communication channel, there is the bandwidth (6.25kHz) of equivalent, former channel still can maintain the configuration identical with simulating 12.5kHz signal.
In multi-channel operation mode, DMR standard also specify three kinds: (1) time division duplex I, two logic channel transmission of one line business respectively；(2) very half-duplex, single logic channel is used for transmitting business
；(3) time division duplex II, a logic channel is used for transmitting business, and another logic channel is used for transmitting backward channel burst, but realizes language with frequency transfer and launch and receive, due to its complex circuit designs, it is difficult to promote and use.
Summary of the invention
The purpose of this utility model is contemplated to solve above-mentioned technical problem, it is provided that shifting circuit in a kind of DMR digital signal, uses the 1st slot transmission voice or uses the 2nd time slot to can be used for receiving voice, using two time slots to realize with frequency transfer.
In order to achieve the above object, this utility model be employed technical scheme comprise that,
Shifting circuit in a kind of DMR digital signal, including receiving PLL frequency synthesizer circuit, receive VCO circuit, receive circuit, MCU control circuit, launch PLL frequency synthesizer circuit, launch VCO circuit, radiating circuit and DMR circuit, described reception PLL frequency synthesizer circuit receives the phase-locked process of frequency, control to receive VCO circuit one stable frequency of output, described reception VCO circuit provides a stable frequency to receiving circuit, signal that described reception circuit reception antenna is come in and and the frequency signal that receives VCO circuit and provide be mixed, export a mixed frequency signal and carry out signal processing to DMR circuit, launch the phase-locked process that PLL frequency synthesizer circuit is tranmitting frequency, control to launch VCO circuit one stable frequency of output；Launching VCO circuit is by voltage-controlled frequency oscillator, on the digital signal modulated that DMR circuit is sent here to high-frequency carrier signal, exports a carrier signal through frequency modulation to radiating circuit；The carrier signal that transmitting VCO circuit sent here by radiating circuit is launched through antenna after amplifying, described MCU control circuit is coordinated to receive PLL frequency synthesizer circuit one stable frequency of output, coordinates transmission PLL frequency synthesizer circuit one stable frequency of output, coordinate DMR circuit and carry out Frequency mixing processing to receiving circuit, and coordinate DMR circuit to radiating circuit generation radio frequency model.
Further, described reception VCO circuit 2 is by voltage-controlled frequency oscillator.
Further, described radiating circuit 7 is high-frequency power amplifying circuit.
Further, described MCU control circuit is single chip machine controlling circuit.
This utility model is by using technique scheme, compared with prior art, have the advantage that one is that realize under same frequency can the DMR digital signaling system of transfer, two is the utilization rate improving Radio Resource, and the frequency that receive and launch can be adjusted flexibly in the frequency range that Ministry of Industry and Information allows.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of embodiment of this utility model.
Detailed description of the invention
In conjunction with the drawings and specific embodiments, this utility model is further illustrated.
nullAs a specific embodiment，As shown in Figure 1，Shifting circuit in a kind of DMR digital signal of the present utility model，Including receiving PLL frequency synthesizer circuit 1、Receive VCO circuit 2、Receive circuit 3、MCU control circuit 4、Launch PLL frequency synthesizer circuit 5、Launch VCO circuit 6、Radiating circuit 7 and DMR circuit 8，Described reception PLL frequency synthesizer circuit 1 receives the phase-locked process of frequency,Control to receive VCO circuit 2 and export a stable frequency，Receiving VCO circuit 2 described in described reception VCO circuit 2 is by voltage-controlled frequency oscillator，It provides a stable frequency to receiving circuit 3，Signal that described reception circuit 3 reception antenna is come in and and the frequency signal that receives VCO circuit 2 and provide be mixed，Export a mixed frequency signal and carry out signal processing to DMR circuit 8，Launch the phase-locked process that PLL frequency synthesizer circuit 5 is tranmitting frequency,Control to launch VCO circuit 6 and export a stable frequency；Launching VCO circuit 6 is by voltage-controlled frequency oscillator, on the digital signal modulated that DMR circuit 8 is sent here to high-frequency carrier signal, exports a carrier signal through frequency modulation to radiating circuit 7；Described radiating circuit 7 is high-frequency power amplifying circuit, and the carrier signal that radiating circuit 7 transmitting VCO circuit 6 is sent here is launched through antenna after amplifying.Described MCU control circuit is single chip machine controlling circuit, described MCU control circuit is coordinated to receive PLL frequency synthesizer circuit 1 and is exported a stable frequency, coordinates transmission PLL frequency synthesizer circuit 5 exports a stable frequency, coordinate DMR circuit 8 and carry out Frequency mixing processing to receiving circuit 3, and coordinate DMR circuit 8 to radiating circuit generation radio frequency model.
Although specifically showing in conjunction with preferred embodiment and describing this utility model; but those skilled in the art should be understood that; in the spirit and scope of the present utility model limited without departing from appended claims; this utility model can be made a variety of changes in the form and details, be protection domain of the present utility model.
Claims (4)
1. shifting circuit in a DMR digital signal, it is characterized in that: include receiving PLL frequency synthesizer circuit, receive VCO circuit, receive circuit, MCU control circuit, launch PLL frequency synthesizer circuit, launch VCO circuit, radiating circuit and DMR circuit, described reception PLL frequency synthesizer circuit receives the phase-locked process of frequency, control to receive VCO circuit one stable frequency of output, described reception VCO circuit provides a stable frequency to receiving circuit, signal that described reception circuit reception antenna is come in and and the frequency signal that receives VCO circuit and provide be mixed, export a mixed frequency signal and carry out signal processing to DMR circuit, launch the phase-locked process that PLL frequency synthesizer circuit is tranmitting frequency, control to launch VCO circuit one stable frequency of output；Launching VCO circuit is by voltage-controlled frequency oscillator, on the digital signal modulated that DMR circuit is sent here to high-frequency carrier signal, exports a carrier signal through frequency modulation to radiating circuit；The carrier signal that transmitting VCO circuit sent here by radiating circuit is launched through antenna after amplifying, described MCU control circuit is coordinated to receive PLL frequency synthesizer circuit one stable frequency of output, coordinates transmission PLL frequency synthesizer circuit one stable frequency of output, coordinate DMR circuit and carry out Frequency mixing processing to receiving circuit, and coordinate DMR circuit to radiating circuit generation radio frequency model.
Shifting circuit in a kind of DMR digital signal the most according to claim 1, it is characterised in that: described reception VCO circuit 2 is by voltage-controlled frequency oscillator.
Shifting circuit in a kind of DMR digital signal the most according to claim 1, it is characterised in that: described radiating circuit 7 is high-frequency power amplifying circuit.
Shifting circuit in a kind of DMR digital signal the most according to claim 1, it is characterised in that: described MCU control circuit is single chip machine controlling circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620306429.8U CN205584194U (en) | 2016-04-13 | 2016-04-13 | DMR data signal transfer circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620306429.8U CN205584194U (en) | 2016-04-13 | 2016-04-13 | DMR data signal transfer circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205584194U true CN205584194U (en) | 2016-09-14 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620306429.8U Expired - Fee Related CN205584194U (en) | 2016-04-13 | 2016-04-13 | DMR data signal transfer circuit |
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| Country | Link |
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| CN (1) | CN205584194U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105763218A (en) * | 2016-04-13 | 2016-07-13 | 国家电网公司 | DMR data signal transfer circuit |
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2016
- 2016-04-13 CN CN201620306429.8U patent/CN205584194U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105763218A (en) * | 2016-04-13 | 2016-07-13 | 国家电网公司 | DMR data signal transfer circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160914 Termination date: 20190413 |