CN103209004B - A kind of multi-time slot transceiver - Google Patents
A kind of multi-time slot transceiver Download PDFInfo
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- CN103209004B CN103209004B CN201310117726.9A CN201310117726A CN103209004B CN 103209004 B CN103209004 B CN 103209004B CN 201310117726 A CN201310117726 A CN 201310117726A CN 103209004 B CN103209004 B CN 103209004B
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Abstract
The invention discloses a kind of multi-time slot transceiver, comprise frequency generating units, this frequency generating units comprises control unit; First frequency synthesis unit, for exporting the first high-frequency local oscillation; Second frequency synthesis unit, for exporting the second high-frequency local oscillation; 3rd frequency synthesis unit, for exporting intermediate frequency local oscillator; Frequency processing unit, for at receiving slot using the first high-frequency local oscillation, intermediate frequency local oscillator as two local oscillators of superheterodyne receiver, at transmission time slot, the first high-frequency local oscillation and intermediate frequency local oscillator are processed, using the signal after process as transmitting local oscillator, the second high-frequency local oscillation is received or the preparation local oscillator of transmission time slot frequency hopping as next.Implement technical scheme of the present invention, space, cost and power consumption are less, the SPI resource taken is less, in adjacent time-slots with under the mode of operation frequently receiving forwarding, can avoid launching co-channel interference to receive, under the mode of operation of adjacent time-slots iso-prone forwards, the noise signal being leaked to modulators modulate generation is easy to filtering.
Description
Technical field
The present invention relates to the communications field, especially relate to a kind of multi-time slot transceiver.
Background technology
Along with science and technology is growing, radio communication develop rapidly, Opportunity coexists with challenge in the development and application of TDMA (Time Division MultipleAddress, time division multiple access) system.The performance stablizing tdma system application product can be tdma system value maximization provides a helping hand.For the tdma system of multi-slot transmitting-receiving, such as TETRA (land trunked communication system) Gateway (gateway) and repeater (repeater) system,, the receipts forwarding of continuous slot rate, a forwarding may be there is, send out turn receipts, receipts turn knock off operation mode in its working time slot complexity.
Because the restriction relation of locking time only can not realize this multi-slot transmitting-receiving translation function with single phase-locked loop, need to adopt many phase-locked loop systems in advance by the receipts in next a time slot/Frequency Locking, then utilize radio-frequency (RF) switch at a high speed to carry out switching to realize.Its operation principle is as follows: launch when adjacent two time slots are all in or receive, due to the restriction of single phase-locked loop locking time, another one phase-locked loop circuit needs the front opening in next time slot arrival and is in the lock state.Such as, as shown in Figure 1, the second time slot is in accepting state, and the 3rd time slot is in emission state, the t before the 3rd time slot arrives
0in the moment, need the phase-locked loop circuit opening transmitter, guarantee that it was in the lock state before the 3rd time slot arrives, and the t before the 3rd time slot
1moment is the initialization time that transmitter shifts to an earlier date opened portion subchannel (modulator).
Existing multi-time slot transceiver needs to adopt many phase-locked loop systems in advance by the receipts in next a time slot/Frequency Locking usually, then radio-frequency (RF) switch is at a high speed utilized to carry out switching to realize, such as, as shown in Figure 2, but this multi-time slot transceiver has following defect:
1. adopt 5 frequency synthesis unit, each frequency synthesis unit comprises phase-locked loop chip and voltage controlled oscillator, phase-locked loop chip is such as PLL (Phase loop locked, phase-locked loop) 1, PLL2, PLL3, PLL4 (PLL4 shown in figure is two phase-locked loop), voltage controlled oscillator is such as TXVCO (VoltageControl Oscillator, voltage controlled oscillator) 1, TXVCO2, RXVCO1, RXVCO2, IFVCO, therefore, take that PCB surface is long-pending, cost and power consumption comparatively large, and need the SPI resource that takies too much;
2. when adjacent time-slots receives forwarding mode of operation with frequency, owing to needing the t before receiving slot terminates
0moment opens the frequency synthesis unit of transmitter, such as, opens phase-locked loop chip PLL1 and voltage controlled oscillator TXVCO1, and needs the t before receiving slot terminates
1moment carries out the initialization of modulator, so, receiving slot also not at the end of, the frequency signal that frequency synthesis unit produces can be sent to radio frequency unit after modulator, therefore easily occurs that launching co-channel interference receives;
3. when adjacent time-slots iso-prone forwards mode of operation, suppose that last transmission time slot is that phase-locked loop chip PLL1 and voltage controlled oscillator TXVCO1 is in work, a rear transmission time slot is phase-locked loop chip PLL2 and voltage controlled oscillator TXVCO2 in work, then need the t before last transmission time slot terminates
0moment opens phase-locked loop chip PLL2 and voltage controlled oscillator TXVCO2, then easily occur that pre-locked local-oscillator leakage produces neighboring trace or broadband noise to modulators modulate, and, be leaked to modulators modulate and produce noise signal from transmitting very, be not easy to filtering.
Summary of the invention
The technical problem to be solved in the present invention is, for the above-mentioned defect of prior art, provides a kind of multi-time slot transceiver, volume/cost/power consumption is little, take SPI resource few, and there will not be launch co-channel interference receive, produce neighboring trace or the easy filtering of broadband noise.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of multi-time slot transceiver, and comprise the frequency generating units for generation of two local oscillators of launching local oscillator and superheterodyne receiver, described frequency generating units comprises:
Control unit;
First frequency synthesis unit, for exporting the first high-frequency local oscillation under the control of described control unit;
Second frequency synthesis unit, for exporting the second high-frequency local oscillation under the control of described control unit;
3rd frequency synthesis unit, for exporting intermediate frequency local oscillator under the control of described control unit;
Frequency processing unit, for under the control of described control unit, at receiving slot using the first high-frequency local oscillation, intermediate frequency local oscillator as two local oscillators of superheterodyne receiver, at transmission time slot, the first high-frequency local oscillation and intermediate frequency local oscillator are processed, using the signal after process as transmitting local oscillator, and this transmitting local oscillator is not equal to the first high-frequency local oscillation or intermediate frequency local oscillator; And, the second high-frequency local oscillation is received or the preparation local oscillator of transmission time slot frequency hopping as next.
In multi-time slot transceiver of the present invention, described frequency processing unit comprises diverter switch, first frequency mixer, band pass filter and the second frequency mixer, wherein, described first frequency synthesis unit and the output of second frequency synthesis unit are connected two selecting sides of described diverter switch respectively, the stiff end of described diverter switch connects the first input end of described first frequency mixer, second input of described first frequency mixer connects the output of described 3rd frequency synthesis unit, the output of described first frequency mixer connects the input of described band pass filter, described band pass filter exports launches local oscillator, the stiff end of described diverter switch also connects the first input end of described second frequency mixer, second input input Received signal strength of described second frequency mixer, and, the stiff end of described diverter switch exports the first local oscillator of superheterodyne receiver, and described 3rd frequency synthesis unit exports the second local oscillator of superheterodyne receiver.
In multi-time slot transceiver of the present invention, described frequency processing unit also comprises the frequency multiplier that Clock Multiplier Factor is even number, and the input of described frequency multiplier connects the stiff end of described diverter switch, the output of described frequency multiplier connects the first input end of described first frequency mixer;
Described multi-time slot transceiver also comprises:
Be connected to the modulator of described band pass filter, for modulating and scaling down processing transmitting;
Being connected to the demodulator of described 3rd frequency synthesis unit and described second frequency mixer, for carrying out frequency division to intermediate frequency local oscillator, and carrying out demodulation process to received signal; And,
The divide ratio of described modulator and described demodulator is reciprocal each other with the Clock Multiplier Factor of described frequency multiplier respectively.
In multi-time slot transceiver of the present invention, described control unit, for controlling described frequency multiplier and the first frequency mixer in transmission time slot work and control the second frequency mixer in receiving slot work; Control described diverter switch to carry out switching and control first moment of described second frequency synthesis unit before previous time slot terminates when adjacent time-slots frequency hopping and start working; When receiving slot turns transmission time slot, controlling second moment of described modulator before receiving slot terminates starts initialization; When transmission time slot turns receiving slot, controlling second moment of described demodulator before transmission time slot terminates starts initialization, and wherein, the second moment was less than for the first moment.
In multi-time slot transceiver of the present invention, described frequency processing unit also comprise following at least one:
First buffer, and the input of described first buffer connects the output of described first frequency synthesis unit, and the output of described first buffer connects the first selecting side of described diverter switch;
Second buffer, and the input of described second buffer connects the output of described second frequency synthesis unit, and the output of described second buffer connects the second selecting side of described diverter switch;
3rd buffer, and the input of described 3rd buffer connects the output of described 3rd frequency synthesis unit, and the output of described 3rd buffer connects the second input of described demodulator.
In multi-time slot transceiver of the present invention, described frequency processing unit also comprises the 4th buffer, the input of described 4th buffer connects the output of described first frequency mixer, and the output of described 4th buffer connects the input of described band pass filter.
In multi-time slot transceiver of the present invention, described frequency processing unit also comprises the 5th buffer, the input of described 5th buffer connects the output of described second frequency mixer, and the output of described 5th buffer connects the first input end of described demodulator.
In multi-time slot transceiver of the present invention, described frequency processing unit also comprises the first switch between stiff end and the input of described frequency multiplier being connected to described diverter switch and the second switch between the output being connected to described 3rd frequency synthesis unit and the second input of described first frequency mixer, and described first switch, second switch close at transmission time slot under the control of described control unit, disconnect at receiving slot or free timeslot.
In multi-time slot transceiver of the present invention, described first frequency synthesis unit comprises the first phase-locked loop chip and the first voltage controlled oscillator that connect successively; Described second frequency synthesis unit comprises the second phase-locked loop chip and the second voltage controlled oscillator that connect successively; Described 3rd frequency synthesis unit comprises the 3rd phase-locked loop chip and the 3rd voltage controlled oscillator that connect successively; Or,
Described first frequency synthesis unit, described second frequency synthesis unit and described 3rd frequency synthesis unit are digital frequency synthesizer.
In multi-time slot transceiver of the present invention, described multi-time slot transceiver also comprises radio frequency unit, power amplifier and low noise amplifier, and, the input of described power amplifier connects the output of described modulator, the output of described power amplifier connects described radio frequency unit, the input of described low noise amplifier connects described radio frequency unit, and the output of described low noise amplifier connects the second input of described second frequency mixer.
Implement technical scheme of the present invention, there is following beneficial effect:
1. for the mode of operation of adjacent time-slots with receipts forwarding frequently, the t before receiving slot terminates
1when moment, (composition graphs 1) carried out the initialization of modulator, due to before receiving slot terminates, frequency processing unit does not process to produce transmitting local oscillator to the first high-frequency local oscillation and intermediate frequency local oscillator, even if this first high-frequency local oscillation and intermediate frequency local oscillator through space radiation or circuit conduct to modulator place, then after modulators modulate, be sent to radio frequency unit frequency signal and receive frequency are still incoherent signals, therefore, in adjacent time-slots with under the mode of operation frequently receiving forwarding, can avoid launching co-channel interference and receive.And, because two adjacent receiving slots are identical with the frequency synthesis unit that transmission time slot uses, therefore without the need to the t before receiving slot terminates
0moment relocks frequency;
2. for adjacent time-slots iso-prone forwards mode of operation, if last transmission time slot is that first frequency synthesis unit is in work, as launching local oscillator after its first high-frequency local oscillation exported and intermediate frequency local oscillator process, be such as A, a rear transmission time slot is that second frequency synthesis unit is in work, as launching local oscillator after its second high-frequency local oscillation exported and intermediate frequency local oscillator process, such as, be B.If the t before last transmission time slot terminates
0moment (composition graphs 1) opens second frequency synthesis unit, the second high-frequency local oscillation that then the second transmission time slot is pre-locked is a frequency relevant with intermediate frequency local oscillator to launching local oscillator B, and the transmitting local oscillator A of this second pre-locked high-frequency local oscillation and the first transmission time slot is apart from each other, be leaked to current demodulator modulation and produce noise signal from away from transmitting, be easy to filtering;
3. in tdma systems, this multi-time slot transceiver only needs three frequency synthesis unit and frequency processing unit just can produce two local oscillators of superheterodyne receiver, launch the preparation local oscillator of local oscillator and frequency hopping, meet the needs of multi-time slot transceiver multiple-working mode in tdma system, and, take the area of PCB, cost and power consumption less, in addition, need the SPI resource taking control unit also less.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described, in accompanying drawing:
Fig. 1 is the working timing figure of tdma system;
Fig. 2 is the logic diagram of a kind of multi-time slot transceiver of prior art;
Fig. 3 is the logic diagram of multi-time slot transceiver medium frequency generation unit embodiment one of the present invention;
Fig. 4 is the logic diagram of multi-time slot transceiver embodiment one of the present invention;
Fig. 5 is the working timing figure of tdma system with guard time;
The analogous diagram of response time when Fig. 6 is multi-time slot transceiver work.
Embodiment
The logic diagram of the embodiment one of multi-time slot transceiver medium frequency generation unit of the present invention as shown in Figure 3, the frequency generating units of this multi-time slot transceiver comprises control unit 500, first frequency synthesis unit 200, second frequency synthesis unit 300, the 3rd frequency synthesis unit 400 and frequency processing unit 100, wherein, first frequency synthesis unit 200 for exporting the first high-frequency local oscillation under the control of control unit 500, such as, the frequency range of the first high-frequency local oscillation is 453.35 ~ 503.35MHz; Second frequency synthesis unit 300 for exporting the second high-frequency local oscillation under the control of control unit 500, and such as, the frequency range of the second high-frequency local oscillation is 453.35 ~ 503.35MHz; 3rd frequency synthesis unit 400 for exporting intermediate frequency local oscillator under the control of control unit 500, and such as, the frequency of intermediate frequency local oscillator is 146.7MHz; Frequency processing unit 100 is under the control of control unit 500, at receiving slot using the first high-frequency local oscillation, intermediate frequency local oscillator as two local oscillators of superheterodyne receiver, at transmission time slot, the first high-frequency local oscillation and intermediate frequency local oscillator are processed, using the signal after process as transmitting local oscillator, and, the second high-frequency local oscillation is received or the preparation local oscillator of transmission time slot frequency hopping as next.It should be noted that at this, the present invention does not limit the mode that frequency processing unit 100 processes the first high-frequency local oscillation and intermediate frequency local oscillator at transmission time slot, and this processing mode can be such as: these two local oscillators (the first high-frequency local oscillation and intermediate frequency local oscillator) first carried out adding and subtracting the computing that (passing through frequency mixer) carries out multiplication and division (by frequency multiplier or frequency divider) again; This processing mode can also be such as: these two local oscillators (the first high-frequency local oscillation and intermediate frequency local oscillator) are first carried out the computing that multiplication and division (by frequency multiplier or frequency divider) carry out adding and subtracting (passing through frequency mixer) more respectively.As long as ensure that the frequency produced after this processing mode process is for launching local oscillator, and this transmitting local oscillator is not equal to the first high-frequency local oscillation or intermediate frequency local oscillator.
Implement technical scheme of the present invention, in tdma systems, this multi-time slot transceiver only needs three frequency synthesis unit, takies the area of PCB, cost and power consumption less, and, need the SPI resource taking control unit less.
In addition, for adjacent time-slots with the mode of operation frequently receiving forwarding, the t before receiving slot terminates
1moment (composition graphs 1) carries out the initialization of modulator, due to before reception gap terminates, frequency processing unit does not process to produce transmitting local oscillator to the first high-frequency local oscillation and intermediate frequency local oscillator, even if this first high-frequency local oscillation and intermediate frequency local oscillator through space radiation or circuit conduct to modulator place, then after modulators modulate, be sent to radio frequency unit frequency signal and receive frequency are still incoherent signals, therefore, in adjacent time-slots with under the mode of operation frequently receiving forwarding, can avoid launching co-channel interference and receive.And, because two adjacent receiving slots are identical with the frequency synthesis unit that transmission time slot uses, therefore without the need to the t before receiving slot terminates
0moment relocks frequency.
For adjacent time-slots iso-prone forwards mode of operation, if last transmission time slot is that first frequency synthesis unit is in work, as launching local oscillator after its first high-frequency local oscillation exported and intermediate frequency local oscillator process, be such as A, a rear transmission time slot is that second frequency synthesis unit is in work, as launching local oscillator after its second high-frequency local oscillation exported and intermediate frequency local oscillator process, such as, be B.If the t before last transmission time slot terminates
0moment (composition graphs 1) opens second frequency synthesis unit, the second high-frequency local oscillation that then the second transmission time slot is pre-locked is a frequency relevant with intermediate frequency local oscillator to launching local oscillator B, and the transmitting local oscillator A of this second pre-locked high-frequency local oscillation and the first transmission time slot is apart from each other, be leaked to current demodulator modulation and produce noise signal from away from transmitting, be easy to filtering.
Fig. 4 is the logic diagram of multi-time slot transceiver embodiment one of the present invention, and this multi-time slot transceiver comprises frequency generating units, modulator 04, demodulator 06, power amplifier PA, low noise amplifier LNA and radio frequency unit.And, frequency generating units comprises control unit (not shown), first frequency synthesis unit, second frequency synthesis unit, the 3rd frequency synthesis unit and frequency processing unit, wherein, first frequency synthesis unit comprises the phase-locked loop chip PLL_A and voltage controlled oscillator RXVCO1 that connect successively, and this first frequency synthesis unit is used for exporting the first high-frequency local oscillation under the control of the control unit; Second frequency synthesis unit comprises the phase-locked loop chip PLL_B and voltage controlled oscillator RXVCO2 that connect successively, and this second frequency synthesis unit is used for exporting the second high-frequency local oscillation under the control of the control unit; 3rd frequency synthesis unit comprises the phase-locked loop chip PLL_IF and voltage controlled oscillator IFVCO that connect successively, and the 3rd frequency synthesis unit is used for exporting intermediate frequency high-frequency local oscillation under the control of the control unit.In frequency processing unit, the output of voltage controlled oscillator RXVCO1 connects first selecting side (1) of diverter switch K1 by buffer 07, the output of voltage controlled oscillator RXVCO2 connects second selecting side (2) of diverter switch K1 by buffer 08, the output of voltage controlled oscillator IFVCO connects the input of buffer 09.The stiff end (3) of diverter switch K1 connects the input of frequency multiplier 01 by K switch 2, the output of frequency multiplier 01 connects the first input end of frequency mixer 02, second input of frequency mixer 02 connects the output of buffer 09 by switch 03, the output of frequency mixer 02 passes through the input of buffer 10 connecting band bandpass filter 03, the output of band pass filter 03 connects the input of modulator 04, the output of modulator 04 connects the input of power amplifier PA, and the output of power amplifier PA connects radio frequency unit TX/RX.The input of low noise amplifier LNA connects radio frequency unit TX/RX, the output of low noise amplifier LNA connects the second input of frequency mixer 05, the first input end of frequency mixer 05 connects the stiff end of diverter switch K1, the output of frequency mixer 05 connects the input of buffer 11, the first input end of the output interface-demodulator 06 of buffer 11, the output of the second input termination buffer 09 of demodulator 06.It should be noted that at this, the divide ratio of modulator 04 and demodulator 06 is reciprocal each other with the Clock Multiplier Factor of frequency multiplier 01 respectively, and the Clock Multiplier Factor of frequency multiplier is even number.In addition, also it should be noted that, control unit carries out following control: respectively by enable signal PLL_A_ON, PLL_B_ON, PLL_IF_ON to control phase-locked loop chip PLL_A, PLL_B, PLL_IF and voltage controlled oscillator RXVCO1, RXVCO2, IFVCO; Frequency multiplier 01, K switch 2, frequency mixer 02, K switch 3, buffer 10, power amplifier PA is controlled in transmission time slot work by enable signal TX_ON; Frequency mixer 05, buffer 11, low noise amplifier LNA is controlled in receiving slot work by enable signal RX_ON; Control diverter switch K1 when adjacent time-slots frequency hopping by enable signal SW_ON to switch; When receiving slot turns transmission time slot, control the second moment (t namely in Fig. 1 of modulator 04 before receiving slot terminates by enable signal MOD_ON
1moment) start initialization; When transmission time slot turns receiving slot, control the second moment (t namely in Fig. 1 of demodulator 06 before transmission time slot terminates by enable signal DEMOD_ON
1moment) start initialization.And in this embodiment, band pass filter 03 exports launches local oscillator, and the stiff end of diverter switch K1 and the output of buffer 09 export two local oscillators of superheterodyne receiver.
The following describes the course of work of this multi-time slot transceiver, first suppose that frequency multiplier 01 is 2 frequency multiplier devices, modulator 04 and demodulator 06 can carry out 1/2 frequency division respectively.In addition, suppose that the frequency that voltage controlled oscillator RXVCO1, RXVCO2, IFVCO export is respectively F
1, F
2, F
3.
Be in adjacent time-slots if current with when frequently receiving forwarding mode of operation, and the stiff end of diverter switch (3) connects the first selecting side (1), in addition, supposes that tranmitting frequency and receive frequency are F.In receiving slot, two local oscillators of superheterodyne receiver are respectively F
1, F
3, now have following relation: F
1-F=F
3/ 2.When receiving slot turns transmission time slot, because it is identical with two frequency synthesis unit that receiving slot produces two local oscillators of superheterodyne receiver that transmission time slot produces two the frequency synthesis unit launching local oscillator, therefore without the need to relocking frequency, only need the second moment (t namely in Fig. 1 before receiving slot terminates
1moment) open modulator 04 and carry out initialization, and, carry out during this period of time initialized at modulator 04, the frequency F that voltage controlled oscillator RXVCO1 exports
1and the frequency F that voltage controlled oscillator IFVCO exports
3even if because the effect of space radiation and circuit conduct is sent to modulator 04, but due to K switch 2, frequency multiplier 01, K switch 3, frequency mixer 02 at receiving slot all without starting working, so, these two frequency signal F
1, F
3after modulator 1/2 frequency division, two signals produced and receive frequency F are incoherent signals, therefore there will not be and launch co-channel interference reception.And gap terminates when 330 receiving, transmission time slot starts instantly, K switch 2, frequency multiplier 01, K switch 3, frequency mixer 02, buffer 10 are all started working, the frequency F that voltage controlled oscillator RXVCO1 exports
1and the frequency F that voltage controlled oscillator IFVCO exports
3after treatment, following relation is had: (2F
1-F
3)/2=F, the signal F then after process is sent to radio frequency unit after power amplifier PA amplifies, and successfully can send, and ensure that tranmitting frequency is identical with receive frequency.
Be in adjacent time-slots iso-prone forwards mode of operation if current, suppose that the stiff end (3) of last transmission time slot diverter switch connects the first selecting side (1), in addition, suppose that the tranmitting frequency of last transmission time slot is F
a, the tranmitting frequency of a rear transmission time slot is F
b.Then at last transmission time slot, there is following relation: (2F
1-F
3)/2=F
a; At a rear time slot, there is following relation: (2F
2-F
3)/2=F
b.Then, the first moment (t namely in Fig. 1 before last transmission time slot terminates
0moment) open phase-locked loop chip PLL_B and voltage controlled oscillator RXVCO2, the frequency F that the voltage controlled oscillator RXVCO2 of pre-locked state locks
2=F
b+ F
3/ 2, so, in last transmission time slot unclosed a period of time, namely open a period of time after phase-locked loop chip PLL_B and voltage controlled oscillator RXVCO2, even if pre-locked local oscillator F
2be leaked to modulator 04, the noise signal produced is from the frequency F of the tranmitting frequency of previous time slot
afar, be easy to filtering.And when last transmission time slot terminate, after a transmission time slot start instantly, the stiff end of diverter switch is made to be connected to the second selecting side by enable signal SW_ON, now, second high-frequency local oscillation F2 and intermediate frequency local oscillator F3 is after frequency multiplier 01, frequency mixer 02, band pass filter 03, modulator 04, power amplifier PA process, send into radio frequency unit, can successfully send.
In addition, it should be noted that, be more than one embodiment of the present of invention, certainly, in certain embodiments of the present invention, frequency multiplier can save, now, the stiff end of diverter switch K1 directly connects the first input end of frequency mixer 02 by K switch 2, correspondingly, modulator 04 and demodulator 06 are not all with division function.In some other embodiment of the present invention, buffer 07,08,09,10,11 can save one or more.In other other embodiments of the present invention, K switch 2, K3 also can save, as long as ensure that frequency multiplier 01 and frequency mixer 02 are only in transmission time slot work.
According to Tetra (Terrestrial Trunked radio, land trunked communication system) agreement regulation, there is a guard time after each time slot starts, t as shown in Figure 5
2, this guard time t
2≈ 0.94mS.Use oscilloscope that the signal that three probes meet enable signal TX_ON in multi-slot transceiver in the above-described embodiments is respectively produced end, the output of SW_ON and the output of frequency mixer 02 below; detect and be opened to the response time of launching local oscillator (TXLO) from enable signal TX_ON, SW_ON; test result as shown in Figure 6; response time Δ X=20.1uS, much smaller than guard time 0.94mS.So this programme is practicable.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various change, combination and change.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within right of the present invention.
Claims (10)
1. a multi-time slot transceiver, comprise the frequency generating units for generation of two local oscillators of launching local oscillator and superheterodyne receiver, it is characterized in that, described frequency generating units comprises:
Control unit;
First frequency synthesis unit, for exporting the first high-frequency local oscillation under the control of described control unit;
Second frequency synthesis unit, for exporting the second high-frequency local oscillation under the control of described control unit;
3rd frequency synthesis unit, for exporting intermediate frequency local oscillator under the control of described control unit;
Frequency processing unit, for under the control of described control unit, at receiving slot using the first high-frequency local oscillation, intermediate frequency local oscillator as two local oscillators of superheterodyne receiver, at transmission time slot, the first high-frequency local oscillation and intermediate frequency local oscillator are processed, using the signal after process as transmitting local oscillator, and this transmitting local oscillator is not equal to the first high-frequency local oscillation or intermediate frequency local oscillator; And, the second high-frequency local oscillation is received or the preparation local oscillator of transmission time slot frequency hopping as next.
2. multi-time slot transceiver according to claim 1, it is characterized in that, described frequency processing unit comprises diverter switch, first frequency mixer, band pass filter and the second frequency mixer, wherein, described first frequency synthesis unit and the output of second frequency synthesis unit are connected two selecting sides of described diverter switch respectively, the stiff end of described diverter switch connects the first input end of described first frequency mixer, second input of described first frequency mixer connects the output of described 3rd frequency synthesis unit, the output of described first frequency mixer connects the input of described band pass filter, described band pass filter exports launches local oscillator, the stiff end of described diverter switch also connects the first input end of described second frequency mixer, second input input Received signal strength of described second frequency mixer, and, the stiff end of described diverter switch exports the first local oscillator of superheterodyne receiver, and described 3rd frequency synthesis unit exports the second local oscillator of superheterodyne receiver.
3. multi-time slot transceiver according to claim 2, is characterized in that,
Described frequency processing unit also comprises the frequency multiplier that Clock Multiplier Factor is even number, and the input of described frequency multiplier connects the stiff end of described diverter switch, and the output of described frequency multiplier connects the first input end of described first frequency mixer;
Described multi-time slot transceiver also comprises:
Be connected to the modulator of described band pass filter, for modulating and scaling down processing transmitting;
Being connected to the demodulator of described 3rd frequency synthesis unit and described second frequency mixer, for carrying out frequency division to intermediate frequency local oscillator, and carrying out demodulation process to received signal; And,
The divide ratio of described modulator and described demodulator is reciprocal each other with the Clock Multiplier Factor of described frequency multiplier respectively.
4. multi-time slot transceiver according to claim 3, is characterized in that, described control unit, for controlling described frequency multiplier and the first frequency mixer in transmission time slot work and control the second frequency mixer in receiving slot work; Control described diverter switch to carry out switching and control first moment of described second frequency synthesis unit before previous time slot terminates when adjacent time-slots frequency hopping and start working; When receiving slot turns transmission time slot, controlling second moment of described modulator before receiving slot terminates starts initialization; When transmission time slot turns receiving slot, controlling second moment of described demodulator before transmission time slot terminates starts initialization, and wherein, the second moment was less than for the first moment.
5. multi-time slot transceiver according to claim 3, is characterized in that, described frequency processing unit also comprise following at least one:
First buffer, and the input of described first buffer connects the output of described first frequency synthesis unit, and the output of described first buffer connects the first selecting side of described diverter switch;
Second buffer, and the input of described second buffer connects the output of described second frequency synthesis unit, and the output of described second buffer connects the second selecting side of described diverter switch;
3rd buffer, and the input of described 3rd buffer connects the output of described 3rd frequency synthesis unit, and the output of described 3rd buffer connects the second input of described demodulator.
6. multi-time slot transceiver according to claim 2, it is characterized in that, described frequency processing unit also comprises the 4th buffer, and the input of described 4th buffer connects the output of described first frequency mixer, and the output of described 4th buffer connects the input of described band pass filter.
7. multi-time slot transceiver according to claim 3, it is characterized in that, described frequency processing unit also comprises the 5th buffer, and the input of described 5th buffer connects the output of described second frequency mixer, and the output of described 5th buffer connects the first input end of described demodulator.
8. multi-time slot transceiver according to claim 3, it is characterized in that, described frequency processing unit also comprises the first switch between stiff end and the input of described frequency multiplier being connected to described diverter switch and the second switch between the output being connected to described 3rd frequency synthesis unit and the second input of described first frequency mixer, and described first switch, second switch close at transmission time slot under the control of described control unit, disconnect at receiving slot or free timeslot.
9. multi-time slot transceiver according to claim 1, is characterized in that, described first frequency synthesis unit comprises the first phase-locked loop chip and the first voltage controlled oscillator that connect successively; Described second frequency synthesis unit comprises the second phase-locked loop chip and the second voltage controlled oscillator that connect successively; Described 3rd frequency synthesis unit comprises the 3rd phase-locked loop chip and the 3rd voltage controlled oscillator that connect successively; Or,
Described first frequency synthesis unit, described second frequency synthesis unit and described 3rd frequency synthesis unit are digital frequency synthesizer.
10. multi-time slot transceiver according to claim 1, it is characterized in that, described multi-time slot transceiver also comprises radio frequency unit, power amplifier and low noise amplifier, and, the input of described power amplifier connects the output of described modulator, the output of described power amplifier connects described radio frequency unit, and the input of described low noise amplifier connects described radio frequency unit, and the output of described low noise amplifier connects the second input of described second frequency mixer.
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| CN103888166B (en) * | 2013-11-20 | 2015-11-11 | 中国电子科技集团公司第五十四研究所 | Transmission modulation-demodulation device is composed in scatter communication altogether |
| CN103746690A (en) * | 2013-12-16 | 2014-04-23 | 天津七六四通信导航技术有限公司 | Frequency synthesis circuit for realizing satellite navigation anti-interference antenna |
| CN106067810A (en) * | 2016-07-21 | 2016-11-02 | 中兵通信科技股份有限公司 | A kind of control system of restructural frequency synthesizer platform |
| CN115473558B (en) * | 2021-06-11 | 2023-07-18 | 海能达通信股份有限公司 | Signal transfer circuit, signal transfer method and electronic equipment |
| CN115065373B (en) * | 2022-04-21 | 2023-12-12 | 海能达通信股份有限公司 | Multi-slot transceiver and multi-slot communication method |
| WO2023201649A1 (en) * | 2022-04-21 | 2023-10-26 | 海能达通信股份有限公司 | Multi-slot transceiver and multi-slot communication method |
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