CN205563555U - Implementation system of self -defined variable bit wide SPI bus agreement based on FPGA - Google Patents
Implementation system of self -defined variable bit wide SPI bus agreement based on FPGA Download PDFInfo
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Abstract
The utility model relates to a signal processing technique field provides an implementation system of self -defined variable bit wide SPI bus agreement based on FPGA, and this system includes clock frequency module, address count module, mode -selection module, control state machine, parallel serial conversion module, chip selection distribution module, data count module. The utility model provides a technical scheme passes through the SPI bus agreement that FPGA realized self -defined variable bit wide, and plug -to -plug compatibility in standard SPI agreement chronogenesis, this system provides the extension of address / control bit wide, data bit wide and chip selection quantity simultaneously, takies that the resource is few, frequency of operation is high.
Description
Technical field
This utility model belongs to signal processing technology field, particularly to a kind of based on FPGA self-defined can
Conjugate wide spi bus agreement realizes system.
Background technology
SPI (Serial Peripheral Interface, Serial Peripheral Interface) is by motorola inc
A kind of high speed first proposed, full duplex, the communication bus of synchronization, and only take up on the pin of chip
Four lines, have saved the pin of chip, are saving space in the layout of PCB, it is provided that convenient, just simultaneously
For this characteristic easy to use, now this communication protocol of increasing integrated chip.
In frequency spectrum monitoring field, almost all of radio-frequency module all use spi bus as control bus,
And domestic radio-frequency module manufacturer is usually and carries out self-defined amendment on the basis of spi bus, to using
Many 16bit addresses and the bit wide of 8bit data are increased and decreased, and create a series of self-defined example standard,
Such as address bit wide becomes 20, and data bit width becomes 3, and Fig. 1 is a kind of SPI protocol of ADI company
Sequential chart, as it is shown in figure 1, this SPI protocol employs 3 line transmission modes, SDIO signal represents data
Input/output line, wherein R/W, W1, W0 and A12～A0 constitute the address/control bit wide of 16bit,
D7-D0 constitutes the data bit width of 8bit.
Traditional microcontroller or processor are at the radio-frequency module of the SPI protocol possessing self-defined bit wide to these
When being controlled, the unmatched problem of bit wide can be run into, for example, it is assumed that the SPI unit of a MCU is
Big bit wide is 32bit, and radio-frequency module demand is 40bit, and now the SPI unit of MCU cannot meet and penetrates
The transmission requirement of frequency module SPI protocol.MCU to solve self-defining SPI bit wide coupling problem, one
General way simulates the sequential of self-defined spi bus with GPIO (universal input/output) pin exactly,
This method can more conveniently solve the unmatched problem of bit wide, but simulated timing diagrams can exist bus frequency relatively
Low, issue and postpone big problem.
Utility model content
[solving the technical problem that]
The purpose of this utility model is to provide a kind of self-defined variable bit width spi bus agreement based on FPGA
Realize system, realized the spi bus agreement of self-defined variable bit width by FPGA.
[technical scheme]
This utility model is achieved through the following technical solutions.
This utility model relates to the realization system of a kind of self-defined variable bit width spi bus agreement based on FPGA
System, turns including clock frequency division module, Address count module, mode selection module, controlled state machine string
Die change block, sheet choosing distribution module, data count module, when the input of described clock frequency division module and this locality
Clock connects, and an outfan of described clock frequency division module is connected with Address count module, described Address count
The input of module receives the bit wide configuration parameter of address/control information, the input of described data count module
Receiving the bit wide configuration parameter of input data, the input of described mode selection module receives pattern configurations parameter,
The input of described parallel serial conversion module receives address/control information and input data, described parallel serial conversion module
Outfan be connected with SPI data wire, another outfan of described Address count module, model selection mould
The outfan of block, the control end of parallel serial conversion module, the outfan of data count module, sheet choosing distribution module
Input be all connected with controlled state machine.
As one preferred embodiment, described mode selection module is configured to: join according to pattern configurations
Number selects mode of operation and the operational module of selection is passed to controlled state machine.
As another preferred embodiment, described controlled state machine is configured to: according to address count module
The parameter of block, data count module, mode selection module output controls the work schedule of parallel serial conversion module,
According to sheet arrangement information, the output signal of sheet choosing distribution module is allocated.
As another preferred embodiment, described parallel serial conversion module is configured to: according to controlled state
The indication signal of machine, merges the address of input/control information and input data, after then merging
The clock that data export according to clock frequency division module carries out serioparallel exchange, serial data is exported while conversion
On SPI data wire.
[beneficial effect]
The technical scheme that the utility model proposes has the advantages that
(1) spi bus that the system that this utility model provides realizes self-defined variable bit width by FPGA is assisted
View, is fully compatible with standard SPI protocol sequential, and this system provides address/control bit wide, data bit simultaneously
Wide and sheet selects the extension of quantity, takies that resource is few, operating frequency is high.
(2) this system controls have preferable versatility for domestic multiple radio-frequency module, can be various
Fpga chip is transplanted easily, there is the highest reusability.
Accompanying drawing explanation
Based on FPGA the self-defined variable bit width SPI that Fig. 1 provides for embodiment one of the present utility model is total
The theory diagram of the system that realizes of wire protocol.
Detailed description of the invention
For making the purpose of this utility model, technical scheme and advantage clearer, below will be to this utility model
Detailed description of the invention carry out clear, complete description.
Based on FPGA the self-defined variable bit width spi bus that Fig. 1 provides for this utility model embodiment one
The theory diagram of the system that realizes of agreement.As it is shown in figure 1, this system 1 include clock frequency division module 11,
The choosing point of location counting module 12, mode selection module 13, controlled state machine 14, parallel serial conversion module 15, sheet
Join module 16, data count module 17.The input of clock frequency division module 11 is connected with local clock, time
One outfan of clock frequency division module 11 is connected with Address count module 12, the input of Address count module 12
End receives the bit wide configuration parameter of address/control information, and the input of data count module 17 receives input data
Bit wide configuration parameter, the input of mode selection module 13 receives pattern configurations parameter, parallel serial conversion module
The input of 15 receives address/control information and input data, the outfan of parallel serial conversion module 15 and SPI
Data wire connect, another outfan of Address count module 12, the outfan of mode selection module 13,
The control end of parallel serial conversion module 15, the outfan of data count module 17, sheet choosing distribute the defeated of module 16
Enter end to be all connected with controlled state machine 14.
In the present embodiment, clock frequency division module 11 is by dividing input local clock and by after frequency dividing
Frequency is as SPI working clock frequency, and wherein frequency dividing ratio is local clock and the ratio of SPI work clock, example
If SPI working clock frequency is 50MHz, when local clock is 200MHz, frequency dividing ratio is
200MHz/50MHz=4.
In the present embodiment, mode selection module 13 selects mode of operation and by selection according to pattern configurations parameter
Operational module passes to controlled state machine 14, after the result of model selection passes to controlled state machine 14, controls
The state of SPI output pin is configured by state machine 14 according to delivery value.Wherein, pattern configurations parameter bag
Include:
(1) MSB (Most Significant Bit, highest significant position) and LSB (Least Significant Bit,
Least significant bit) priority, the most first send MSB or LSB；
(2) data sampling sequential, i.e. data sampling are to carry out at rising edge clock or enter at clock falling edge
OK；
(3) the SCK level value of idle condition, i.e. SCK level value during idle condition be high level still
Low level.
In the present embodiment, Address count module 12 receives the bit wide configuration parameter of address/control information and counts
Number, sends count results to controlled state machine 14.Because the bit wide configuration parameter of this address/control information is direct
Have influence on the length of address/control information in the value of address counter and SPI serial data.
In the present embodiment, the input of data count module 17 receives the bit wide configuration parameter of input data and goes forward side by side
Row counting, sends count results to controlled state machine 14.Therefore the bit wide configuration parameter inputting data is direct
Have influence on the data length in the value of address counter and SPI serial data.
In the present embodiment, controlled state machine 14 is commander's core of whole system, specifically, controlled state machine
14 control according to address counting module 12, data count module 17, the parameter of mode selection module 13 output
The work schedule of parallel serial conversion module 15 processed, according to the output to sheet choosing distribution module 16 of the sheet arrangement information
Signal is allocated.It addition, controlled state machine 14 is also responsible for the beginning of whole system/terminate and send transmission
Complete indication signal and back read data.
In the present embodiment, parallel serial conversion module 15 is according to the indication signal of controlled state machine 14, by input
Address/control information and input data merge, and the data after then merging are according to clock frequency division module 11
The clock of output carries out serioparallel exchange, serial data is exported on SPI data wire while conversion.
In the present embodiment, the outfan of sheet choosing distribution module 16 connects SPI equipment, by sheet choosing distribution module
The chip selection signal of 16 outputs selects different SPI equipment to be controlled, it is achieved that the timesharing of multiple SPI equipment
Multiplexing, saves peripheral hardware number of pin, reduces wiring complexity.
The system that the realizes tool of based on FPGA the self-defined variable bit width spi bus agreement that the present embodiment provides
There is a following characteristics:
(1) the address bit wide of self-defined spi bus is variable, and mobility scale is 0～128bit；
(2) data bit width of self-defined spi bus is variable, and mobility scale is 0～128bit；
(3) within a SPI data segment transmission cycle, dynamically address and data bit width can be changed；
(4) operating frequency of self-defined spi bus can reach 50MHz, the 25MHz that the standard of breaching specifies；
(5) all time series patterns of SPI protocol it are capable of；
(6) possesses higher time sequence precision, up to ns level；
(7) possess the chip selection signal of variable number, 8 sheets choosing outputs of maximum support；
(8) support to switch in 3 ray modes and 4 ray modes.
As can be seen from the above embodiments, the system that this utility model embodiment provides is realized certainly by FPGA
The spi bus agreement of definition variable bit width, is fully compatible with standard SPI protocol sequential, and this system provides simultaneously
Address/control bit wide, data bit width and sheet select the extension of quantity, take that resource is few, operating frequency is high.Separately
Outward, this system controls have preferable versatility for domestic multiple radio-frequency module, can be at various FPGA
Chip is transplanted easily, there is the highest reusability.
It is to be appreciated that embodiments described above is a part of embodiment of the present utility model rather than all
Embodiment, is not to restriction of the present utility model.Based on embodiment of the present utility model, this area is common
The every other embodiment that technical staff is obtained under not paying creative work premise, broadly falls into this practicality
Novel protection domain.
Claims (4)
1. self-defined variable bit width spi bus agreement based on FPGA realize a system, its feature exists
In including clock frequency division module, Address count module, mode selection module, controlled state machine, parallel-serial conversion
Module, sheet choosing distribution module, data count module, the input of described clock frequency division module and local clock
Connecting, an outfan of described clock frequency division module is connected with Address count module, described Address count mould
The input of block receives the bit wide configuration parameter of address/control information, the input termination of described data count module
Receiving the bit wide configuration parameter of input data, the input of described mode selection module receives pattern configurations parameter,
The input of described parallel serial conversion module receives address/control information and input data, described parallel serial conversion module
Outfan be connected with SPI data wire, another outfan of described Address count module, model selection mould
The outfan of block, the control end of parallel serial conversion module, the outfan of data count module, sheet choosing distribution module
Input be all connected with controlled state machine.
The reality of self-defined variable bit width spi bus agreement based on FPGA the most according to claim 1
Existing system, it is characterised in that described mode selection module is configured to: according to pattern configurations parameter selection work
The operational module of selection is also passed to controlled state machine by pattern.
The reality of self-defined variable bit width spi bus agreement based on FPGA the most according to claim 1
Existing system, it is characterised in that described controlled state machine is configured to: according to address counting module, data counts
The parameter of module, mode selection module output controls the work schedule of parallel serial conversion module, matches according to sheet
The output signal of sheet choosing distribution module is allocated by confidence breath.
The reality of self-defined variable bit width spi bus agreement based on FPGA the most according to claim 1
Existing system, it is characterised in that described parallel serial conversion module is configured to: according to the indication signal of controlled state machine,
The address of input/control information and input data being merged, the data after then merging are divided according to clock
The clock of frequency module output carries out serioparallel exchange, serial data is exported on SPI data wire while conversion.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106649187A (en) * | 2016-12-28 | 2017-05-10 | 中国科学院微电子研究所 | Chip automatic peripheral device protocol selection method |
| CN109165176A (en) * | 2018-07-27 | 2019-01-08 | 北京无线电测量研究所 | A kind of width phase control chip and bus type data transfer components |
| CN109359083A (en) * | 2018-09-27 | 2019-02-19 | 浙江大学 | The hardware implementation method of restructural series bus controller in a kind of chip |
| WO2021258956A1 (en) * | 2020-06-22 | 2021-12-30 | 中兴通讯股份有限公司 | Clock configuration system and method |
| CN115328846A (en) * | 2022-10-12 | 2022-11-11 | 中科声龙科技发展（北京）有限公司 | Method and device for realizing data operation |
-
2016
- 2016-04-07 CN CN201620285931.5U patent/CN205563555U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106649187A (en) * | 2016-12-28 | 2017-05-10 | 中国科学院微电子研究所 | Chip automatic peripheral device protocol selection method |
| CN109165176A (en) * | 2018-07-27 | 2019-01-08 | 北京无线电测量研究所 | A kind of width phase control chip and bus type data transfer components |
| CN109359083A (en) * | 2018-09-27 | 2019-02-19 | 浙江大学 | The hardware implementation method of restructural series bus controller in a kind of chip |
| WO2021258956A1 (en) * | 2020-06-22 | 2021-12-30 | 中兴通讯股份有限公司 | Clock configuration system and method |
| CN115328846A (en) * | 2022-10-12 | 2022-11-11 | 中科声龙科技发展（北京）有限公司 | Method and device for realizing data operation |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 610045 No. 130 Wuxing Fourth Road, Wuhou New Town Management Committee, Chengdu City, Sichuan Province Patentee after: Chengdu Huari Communication Technology Co., Ltd Address before: 610000 Sichuan city of Chengdu Province East Road three Wuhou District Wuke 6 (CMC in Wuhou new town) Patentee before: CHENGDU HUARI COMMUNICATION TECHNOLOGY Co.,Ltd. |
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| CP03 | Change of name, title or address |