CN205407591U - Be applied to voltage peak control circuit of DC -DC converter - Google Patents

Abstract

The utility model discloses a be applied to voltage peak control circuit of DC -DC converter, include: DC power supply, DC -DC chopper circuit, filter capacitance, RS trigger, clock module, drive module, comparator, partial pressure module, this circuit is a closed -loop control scheme, through detecting output voltage, carries out the comparison with output voltage with preset the reference to the break -make of switch tube realizes the control of voltage peak among the adoption RS trigger control DC -DC chopper circuit. The utility model discloses a voltage peak control circuit configuration simple and clear, control is convenient, than PID control, does not need loaded down with trivial details parameter calculation process, and voltage dynamic characteristic is good, and response speed is fast, and adjust the time is short, has the overvoltage protection function in addition.

Description

A kind of voltage peak control circuit being applied to DC-DC converter

Technical field

This utility model belongs to electric and electronic technical field, relates to a kind of voltage peak control circuit, particularly relates to a kind of voltage peak control circuit being applied to DC-DC converter.

Background technology

DC dc converter (abbreviation DC-DC converter) is the galvanic Power Electronic Circuit topology that the unidirectional current of a kind of electric pressure is changed into other electric pressure.DC source has extremely wide application market and application.Current DC-DC converter mainly has following several prevailing topology: Buck circuit buck chopper, and average voltage U0 is less than input voltage Ui in its output, and polarity is identical；Boost circuit boost chopper, average voltage U0 is more than input voltage Ui in its output, and polarity is identical；Buck-Boost circuit buck or boost chopper, average voltage U0 is more than or less than input voltage Ui, opposite polarity in its output；Cuk circuit buck or boost chopper, average voltage U0 is more than or less than input voltage Ui, opposite polarity in its output；Also has Sepic, Zeta circuit.Above-mentioned for non-isolation type circuit, isolated form circuit has forward converter, circuit of reversed excitation, half-bridge circuit, full-bridge circuit, push-pull circuit.For current various DC-DC converter, it is substantially by above topology combination or develops.

In the control of DC-DC converter, if adopting simple opened loop control, to there is output accuracy low, the adjustment time is long, the problems such as dynamic response is slow, it is therefore necessary to adopting closed loop feedback to control, the mode of closed loop control currently mainly has Voltage Feedback PID to control, Hysteresis control, the mode such as current peak control.Voltage Feedback PID controls to need changer is carried out Accurate Model, and the pid parameter of optimum reasonable in design is relatively complicated；Hysteresis control is mainly by the voltage in circuit or the stagnant ring scope of one given voltage x current of current tracking, and the frequency of switching tube is not fixed, affected by a load relatively larger, and filter design difficult, electromagnetic interference problem ratio is more serious；Current peak controls possess certain current-limiting protection function, improves reliability, but current peak controls circuit noise is very sensitive, and directly do not control output voltage, so the dynamic characteristic of output voltage is bad.

Summary of the invention

The purpose of this utility model is in that for the deficiencies in the prior art, it is provided that a kind of voltage peak control strategy, is applied to the feedback control of DC-DC converter.

This utility model is applied to the voltage peak control circuit of DC-DC converter, including: DC source, DC-DC chopper circuit, filter capacitor, rest-set flip-flop, clock module, driving module, comparator, division module；DC source is that DC-DC chopper circuit is powered, the earth terminal of DC-DC chopper circuit and one end of filter capacitor, one end of load is connected and ground connection, the PWM outfan of DC-DC chopper circuit and the other end of filter capacitor, the other end of load and division module input are connected, the outfan of division module connects the signal input part of comparator, the outfan of comparator and the outfan of clock module connect two inputs of rest-set flip-flop respectively, the outfan of rest-set flip-flop is connected with driving module input, drive module for driving the switching device in DC-DC chopper circuit.

Additionally, be also provided with analog circuit or the digital circuit for adding sawtooth waveforms in comparator between division module outfan and the signal input part of comparator, analog circuit can adopt discharge circuit to realize, and digital circuit can adopt DSP to realize.

The beneficial effects of the utility model are:

1) voltage peak control circuit simple in construction of the present utility model understands, easy to control, and relatively PID controls, it is not necessary to loaded down with trivial details parameter calculation procedure；

2) dynamic voltage characteristics is good because voltage peak control be the direct feedback ratio about voltage relatively, therefore need not by electric current, it is achieved that voltage directly control, fast response time, adjustment the time short；

3) there is over-voltage protection function, because voltage peak controls to be detect output voltage to realize control, therefore there is over-voltage protection function.

Accompanying drawing explanation

Fig. 1 is a kind of voltage peak control circuit figure being applied to DC-DC converter；

Fig. 2 is the voltage peak control circuit figure for buck circuit；

Fig. 3 is that voltage peak controls lower capacitance voltage oscillogram；

Capacitance voltage oscillogram when Fig. 4 is there is disturbance；

Fig. 5 adds the voltage peak control block diagram that sawtooth waveforms compensates；

Fig. 6 adds the voltage peak control capacitance voltage oscillogram that sawtooth waveforms compensates.

Detailed description of the invention

Below in conjunction with accompanying drawing, this utility model is described further.

Fig. 1 is the schematic diagram of the voltage peak control circuit being applied to DC-DC chopper circuit, for Buck chopper circuit, it is applied to the voltage peak control circuit of Buck circuit, as in figure 2 it is shown, include 1 DC source DC, 1 switch mosfet pipe Q1 carrying anti-paralleled diode, 1 diode VD1,1 inductance L, 1 electric capacity C, also have load resistance R, constitute main power circuit；And 1 proportional component (generally can be obtained by electric resistance partial pressure, i.e. division module), a comparator, a rest-set flip-flop, a clock module, one drives module, constitutes voltage peak and controls loop.Main power circuit Buck realizes the function of blood pressure lowering, and under continuous operation (CCM) pattern stable state, input and output voltage relation is:

$\frac{V_{out}}{V_{in}}=D$

Wherein V_outRepresent the voltage on load resistance, V during CCM pattern steady operation_inRepresenting the voltage of input DC power DC, D represents dutycycle.

After adding voltage peak control, output voltage v (t) becomes a feedback signal Vb through proportional component, this signal and output voltage are proportional, the reference voltage Vref of this signal Yu setting is compared, comparator output only high level and low level two states, when Vb is more than Vref, comparator output high level；When Vb is less than Vref, comparator output low level.This compare if analog chip realize words, it is possible to accomplish that real-time sampling compares, if digit chip realize, it is possible to its comparison speed is set by arranging sample frequency.Exporting to the reset terminal R of rest-set flip-flop as input of comparator, and input a clock signal to the set end S of rest-set flip-flop, the per interval Ts of this signal triggers with regard to high level, by trigger set, Q exports high level, is turned on by switch mosfet pipe Q1 through overdriving, then Buck circuit enters charge mode, inductive current rises, and capacitance voltage rises.When rise to so that Vb more than Vref time, comparator output high level, rest-set flip-flop reset, Q end output low level, turns off MOSFET through overdriving, then Buck circuit enters freewheeling mode, capacitance voltage declines, until next cycle clock pulses triggering and conducting MOSFET.Thus realizing the maximum of voltage less than the Vref set, having little fluctuation at below Vref, this fluctuation size and inductance, capacitance size are relevant.Namely voltage peak control is achieved.

As it is shown on figure 3, for controlling capacitance voltage oscillogram, when the time is 0, the set end of clock pulses triggered RS flip-flop, capacitance voltage begins to ramp up, and knows according to capacitance characteristic equation, and inductive current meets with capacitance voltage:

$i_L\left(t\right)=C\frac{dv\left(t\right)}{dt}+\frac{v\left(t\right)}{R}$

Wherein i_LT () represents inductive current, v (t) represents capacitance voltage and output voltage, and C is capacitance, and R is load resistor value.

When MOSFET turns on time, inductance magnetizes, and electric current rises, and electric capacity charges, and voltage rises.The climbing k1 of electric capacity charging voltage meets:

$k1=\frac{dv\left(t\right)}{dt}=\frac{i_L\left(t\right)}{C}-\frac{v\left(t\right)}{CR}$

When MOSFET turns off time, inductance puts magnetic, and electric current declines, and electric capacity discharges, and voltage declines.The absolute value k2 of the rate of descent of voltage meets:

$k2=\frac{v\left(t\right)}{CR}-\frac{i_L\left(t\right)}{C}$

After reference voltage Vref is given, capacitance voltage will rise in 0-dTs interval, decline, rise to Vref at dTs moment voltage within the scope of dTs-Ts.Having v (t)=v (Ts) under steady operation, if ignoring voltage fluctuation of capacitor, then output voltage is approximately equal to Vref.Namely the peak value achieving voltage controls.

As shown in Figure 4, represent there is under disturbance capacitance voltage at the whole story in a cycle, the change of disturbance quantity.The relation being not difficult to derive the disturbance quantity △ Vc (Ts) in 0 moment disturbance quantity △ Vc (0) and Ts moment according to geometrical relationship is:

$\left|\frac{\mathrm{\Δ}Vc\left(Ts\right)}{\mathrm{\Δ}Vc\left(0\right)}\right|=\left|\frac{k2}{k1}\right|$

Then if it is desired that capacitance voltage reaches stable state after a period of time, i.e. v (t)=v (Ts).It has to be ensured thatLess than 1, namely disturbance restrains in a small amount over time, and this is equivalent to dutycycle less than 0.5.For DC-DC variator, this working range being equivalent to define changer.In order to solve above-mentioned steady state problem, it is possible to add sawtooth signal at comparator input terminal and compensate, it may be assumed that add analog circuit or the digital circuit for injecting sawtooth waveforms in comparator between division module outfan and the signal input part of comparator.

As it is shown in figure 5, adding a slope in Vb is the sawtooth waveforms of-ma, this sawtooth waveforms and the output voltage through proportional component are sampled and are added, as new input signal Vb.The cycle of sawtooth waveforms is Ts, identical with the clock cycle.

Add sawtooth waveforms and compensate later capacitance voltage oscillogram as shown in Figure 6, from this oscillogram it can be seen that in the dTs moment, output voltage becomes Vs-ma*dTs.Under compensating at this so that when there is disturbance, being not difficult to derive according to simple geometrical relationship, the disturbance component relation at a whole story in cycle becomes:

$\left|\frac{\mathrm{\Δ}Vc\left(Ts\right)}{\mathrm{\Δ}Vc\left(0\right)}\right|=\left|\frac{k2-ma}{k1+ma}\right|$

This is good for the convergence of disturbance, therefore can pass through the size selecting to compensate sawtooth waveforms slope, it is achieved DC-DC converter works under wide scope dutycycle.Such as ma=k2,When this means to exist disturbance, a cycle just may return to steady-state operation.

Voltage peak control circuit of the present utility model mainly has the advantage that control is simple, and total is simple and clear, it is simple to understand, and relatively PID controls, it is not necessary to loaded down with trivial details parameter calculation procedure；Dynamic voltage characteristics is good because voltage peak control be the direct feedback ratio about voltage relatively, therefore need not be controlled by electric current, it is achieved that voltage directly control, fast response time, adjustment the time short；Having over-voltage protection function, because voltage peak controls to be detect output voltage to realize control, therefore have over-voltage protection function, once output voltage exceedes given reference voltage, switching tube immediately turns off, it is achieved that voltage protection function.This patent also analyzes the stable duty cycle range under being not added with sawtooth waveforms compensation situation, and gives the compensation result adding sawtooth waveforms, has analyzed for disturbance convergence problem.

Claims (2)

1. the voltage peak control circuit being applied to DC-DC converter, it is characterised in that including: DC source, DC-DC chopper circuit, filter capacitor, rest-set flip-flop, clock module, driving module, comparator, division module；DC source is that DC-DC chopper circuit is powered, the earth terminal of DC-DC chopper circuit and one end of filter capacitor, one end of load is connected and ground connection, the PWM outfan of DC-DC chopper circuit and the other end of filter capacitor, the other end of load and division module input are connected, the outfan of division module connects the signal input part of comparator, the outfan of comparator and the outfan of clock module connect two inputs of rest-set flip-flop respectively, the outfan of rest-set flip-flop is connected with driving module input, drive module for driving the switching device in DC-DC chopper circuit.

2. the voltage peak control circuit being applied to DC-DC converter according to claim 1, it is characterised in that be additionally provided with analog circuit or the digital circuit for adding sawtooth waveforms in comparator between division module outfan and the signal input part of comparator.