CN205407591U - Be applied to voltage peak control circuit of DC -DC converter - Google Patents

Abstract

The utility model discloses a voltage peak control circuit applied to a DC-DC converter, comprising: a DC power supply, a DC-DC chopping circuit, a filter capacitor, an RS trigger, a clock module, a drive module, a comparator, a voltage divider module; this circuit is a closed-loop control scheme, by detecting the output voltage, comparing the output voltage with a given reference, and using the RS trigger to control the on-off of the switching tube in the DC-DC chopper circuit, so as to realize the control of the voltage peak value . The structure of the voltage peak control circuit of the utility model is simple and clear, and the control is convenient. Compared with the PID control, it does not need the complicated parameter calculation process; and the voltage dynamic characteristics are good, the response speed is fast, and the adjustment time is short; in addition, it also has the function of overvoltage protection. .

Description

A Voltage Peak Control Circuit Applied to DC-DC Converter

technical field

The utility model belongs to the technical field of power electronics and relates to a voltage peak control circuit, in particular to a voltage peak control circuit applied to a DC-DC converter.

Background technique

A DC-DC converter (DC-DC converter for short) is a power electronic circuit topology that converts direct current at a voltage level into direct current at other voltage levels. DC power supply has a very wide range of application markets and application fields. The current DC-DC converter mainly has the following main topologies: Buck circuit——a step-down chopper, whose output average voltage U0 is smaller than the input voltage Ui, with the same polarity; Boost circuit——a step-up chopper, whose The average output voltage U0 is greater than the input voltage Ui, and the polarity is the same; Buck-Boost circuit--a step-down or step-up chopper, the output average voltage U0 is greater than or less than the input voltage Ui, and the polarity is opposite; Cuk circuit-- Buck Or a step-up chopper, the average output voltage U0 is greater than or less than the input voltage Ui, and the polarity is opposite; there are also Sepic and Zeta circuits. The above is a non-isolated circuit, and the isolated circuit includes a forward circuit, a flyback circuit, a half-bridge circuit, a full-bridge circuit, and a push-pull circuit. For the current various DC-DC converters, they are basically combined or evolved from the above topologies.

In the control of DC-DC converters, if a simple open-loop control is used, there will be problems such as low output accuracy, long adjustment time, and slow dynamic response. Therefore, closed-loop feedback control must be used. Currently, the closed-loop control method mainly includes voltage feedback. PID control, hysteresis control, current peak control, etc. Voltage feedback PID control requires accurate modeling of the converter, and it is cumbersome to design reasonable and optimal PID parameters; hysteresis control mainly uses the voltage or current in the circuit to track a given voltage and current hysteresis range, and the switching tube The frequency is not fixed, it is greatly affected by the load, the filter design is difficult, and the electromagnetic interference problem is serious; the current peak control has a certain current limiting protection function, which improves the reliability, but the current peak control is very sensitive to circuit noise, and there is no The output voltage is directly controlled, so the dynamic characteristics of the output voltage are not good.

Contents of the invention

The purpose of the utility model is to provide a voltage peak control strategy, which is applied to the feedback control of a DC-DC converter, aiming at the deficiencies of the prior art.

The utility model is applied to a voltage peak control circuit of a DC-DC converter, including: a DC power supply, a DC-DC chopping circuit, a filter capacitor, an RS trigger, a clock module, a drive module, a comparator, and a voltage divider module; a DC power supply To supply power to the DC-DC chopping circuit, the ground terminal of the DC-DC chopping circuit is connected to one end of the filter capacitor and one end of the load and grounded, and the PWM output terminal of the DC-DC chopping circuit is connected to the other end of the filter capacitor and the load. The other end is connected to the input end of the voltage divider module, the output end of the voltage divider module is connected to the signal input end of the comparator, the output end of the comparator and the output end of the clock module are respectively connected to the two input ends of the RS flip-flop, and the output end of the RS flip-flop The output terminal is connected with the input terminal of the driving module, and the driving module is used for driving the switch device in the DC-DC chopper circuit.

In addition, an analog circuit or a digital circuit for adding a sawtooth wave to the comparator may also be provided between the output terminal of the voltage divider module and the signal input terminal of the comparator. The analog circuit may be implemented by an operational amplifier circuit, and the digital circuit may be implemented by a DSP accomplish.

The beneficial effects of the utility model are:

1) The structure of the voltage peak control circuit of the utility model is simple and clear, and the control is convenient. Compared with the PID control, it does not need a complicated parameter calculation process;

2) The dynamic characteristics of the voltage are good, because the voltage peak control is a direct feedback comparison of the voltage, so the direct control of the voltage is realized without the help of the current, the response speed is fast, and the adjustment time is short;

3) It has an overvoltage protection function, because the voltage peak control is to detect the output voltage to achieve control, so it has an overvoltage protection function.

Description of drawings

Fig. 1 is a voltage peak control circuit diagram applied to a DC-DC converter;

Fig. 2 is a voltage peak control circuit diagram taking a buck circuit as an example;

Fig. 3 is a waveform diagram of capacitor voltage under voltage peak control;

Fig. 4 is the capacitor voltage waveform diagram when there is a disturbance;

Fig. 5 is a block diagram of voltage peak control with sawtooth compensation added;

Fig. 6 is a waveform diagram of the voltage peak control capacitor voltage with sawtooth compensation added.

detailed description

Below in conjunction with accompanying drawing, the utility model is further described.

Figure 1 is a schematic diagram of a voltage peak control circuit applied to a DC-DC chopper circuit. Taking a Buck chopper circuit as an example, the voltage peak control circuit applied to a Buck circuit, as shown in Figure 2, includes a DC power supply DC, 1 MOSFET switch tube Q1 with anti-parallel diode, 1 diode VD1, 1 inductor L, 1 capacitor C, and load resistor R, forming the main power circuit; and 1 proportional link (generally divided by resistors) Obtained, that is, the voltage divider module), a comparator, an RS flip-flop, a clock module, and a drive module to form a voltage peak control loop. The main power circuit Buck realizes the function of step-down, and the input-output voltage relationship in the steady state of continuous operation (CCM) mode is:

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; u</span>}\mathrm{<span\; class="notranslate">\; t</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; D.</span>}$

Among them, V _out represents the voltage on the load resistor when the CCM mode works in steady state, V _in represents the voltage of the input DC power supply DC, and D represents the duty cycle.

After the voltage peak control is added, the output voltage v(t) becomes a feedback signal Vb through the proportional link, which is proportional to the output voltage. The signal is compared with the set reference voltage Vref, and the output of the comparator is only high level and Two states of low level, when Vb is greater than Vref, the comparator outputs high level; when Vb is less than Vref, the comparator outputs low level. If this comparison is implemented by an analog chip, real-time sampling and comparison can be achieved; if it is implemented by a digital chip, its comparison speed can be set by setting the sampling frequency. The output of the comparator is input to the reset terminal R of the RS flip-flop, and a clock signal is input to the set terminal S of the RS flip-flop. This signal is triggered at a high level every time Ts, and the flip-flop is set. Q Output a high level, and drive the MOSFET switch Q1 to turn on, then the Buck circuit enters the charging mode, the inductor current rises, and the capacitor voltage rises. When it rises to make Vb greater than Vref, the comparator outputs a high level, the RS flip-flop resets, and the Q terminal outputs a low level. After being driven to turn off the MOSFET, the Buck circuit enters the freewheeling mode, and the capacitor voltage drops until the next A periodic clock pulse triggers the MOSFET to turn on. In this way, the maximum value of the voltage does not exceed the set Vref, and there is a small fluctuation below Vref, and the magnitude of the fluctuation is related to the size of the inductance and capacitance. That is, the voltage peak control is realized.

As shown in Figure 3, it is the waveform diagram of the control capacitor voltage. When the time is 0, the clock pulse triggers the set terminal of the RS flip-flop, and the capacitor voltage starts to rise. According to the capacitor characteristic equation, the inductor current and capacitor voltage satisfy:

${\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; C</span>}\frac{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; v</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; v</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}$

Among them, i _L (t) represents the inductor current, v(t) represents the capacitor voltage, that is, the output voltage, C is the capacitor value, and R is the load resistance value.

When the MOSFET is turned on, the inductor is magnetized, the current rises, the capacitor is charged, and the voltage rises. The rising rate k1 of the capacitor charging voltage satisfies:

$\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; v</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; v</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; R</span>}}$

When the MOSFET is turned off, the inductor is demagnetized, the current drops, the capacitor discharges, and the voltage drops. The absolute value k2 of the voltage drop rate satisfies:

$\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; v</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; C</span>}\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; t</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}$

When the reference voltage Vref is given, the capacitor voltage will rise in the range of 0-dTs, fall in the range of dTs-Ts, and the voltage will rise to Vref at the moment of dTs. Under stable operation, there is v(t)=v(Ts). If the capacitor voltage fluctuation is ignored, the output voltage is approximately equal to Vref. That is, the peak value control of the voltage is realized.

As shown in Figure 4, it represents the change of the disturbance amount at the beginning and end of a cycle of the capacitor voltage under the presence of disturbance. According to the geometric relationship, it is not difficult to derive the relationship between the disturbance amount △Vc(0) at time 0 and the disturbance amount △Vc(Ts) at time Ts as follows:

$<span\; class="notranslate">\; |</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; |</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; |</span>$

So after a period of time, if the capacitor voltage is to reach a steady state, that is, v(t)=v(Ts). must guarantee Less than 1, that is, the small amount of disturbance converges with time, which is equivalent to the duty cycle being less than 0.5. For DC-DC converters, this is equivalent to limiting the working range of the converter. In order to solve the above steady-state problem, a sawtooth signal compensation can be added at the input end of the comparator, that is, an analog circuit for injecting a sawtooth wave into the comparator is added between the output end of the voltage divider module and the signal input end of the comparator or Digital circuits.

As shown in Figure 5, a sawtooth wave with a slope of -ma is added to Vb, and the sawtooth wave is added to the output voltage sampled through the proportional link as a new input signal Vb. The period of the sawtooth wave is Ts, which is the same as the period of the clock.

The waveform diagram of the capacitor voltage after sawtooth compensation is shown in Figure 6. It can be seen from the waveform diagram that the output voltage becomes Vs-ma*dTs at the moment of dTs. Under this compensation, in the presence of disturbance, it is not difficult to derive according to the simple geometric relationship, the relationship between the disturbance components at the beginning and end of a cycle becomes:

$<span\; class="notranslate">\; |</span>\frac{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; \&Delta;</span>}\mathrm{<span\; class="notranslate">\; V</span>}\mathrm{<span\; class="notranslate">\; c</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; |</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; |</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; a</span>}}{\mathrm{<span\; class="notranslate">\; k</span>}\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; |</span>$

This is good for the convergence of the disturbance, so the DC-DC converter can be realized to work in a wide range of duty cycles by selecting the size of the compensation sawtooth wave slope. For example, when ma=k2, This means that in the presence of disturbances, one cycle can return to steady state operation.

The voltage peak control circuit of the utility model mainly has the following advantages: the control is simple, the whole structure is simple and clear, and it is easy to understand. Compared with the PID control, it does not need cumbersome parameter calculation process; the voltage dynamic characteristics are good, because the voltage peak control is about the voltage Compared with the direct feedback of the current, it does not need to be controlled by the current, and the direct control of the voltage is realized, the response speed is fast, and the adjustment time is short; it has an over-voltage protection function, because the voltage peak control is to detect the output voltage to achieve control, so it has over-voltage Protection function, once the output voltage exceeds a given reference voltage, the switch tube is turned off immediately, realizing the voltage protection function. This patent also analyzes the stable duty cycle range without adding sawtooth wave compensation, and gives the compensation result with adding sawtooth wave, and analyzes the disturbance convergence problem.

Claims (2)

1. A voltage peak control circuit applied to a DC-DC converter, characterized in that it comprises: DC power supply, DC-DC chopping circuit, filter capacitor, RS flip-flop, clock module, drive module, comparator, splitter voltage module; the DC power supply supplies power to the DC-DC chopping circuit, the ground terminal of the DC-DC chopping circuit is connected to one terminal of the filter capacitor and one terminal of the load and grounded, and the PWM output terminal of the DC-DC chopping circuit is connected to the terminal of the filter capacitor The other end, the other end of the load, and the input end of the voltage divider module are connected, the output end of the voltage divider module is connected to the signal input end of the comparator, and the output end of the comparator and the output end of the clock module are respectively connected to the two input ends of the RS flip-flop , the output terminal of the RS flip-flop is connected to the input terminal of the driving module, and the driving module is used to drive the switching device in the DC-DC chopper circuit. 2. the voltage peak control circuit that is applied to DC-DC converter according to claim 1, is characterized in that, be also provided with for adding in the comparator between the signal input end of voltage divider module output terminal Analog circuit or digital circuit of sawtooth wave.