CN205377797U - Prevent direct power drive circuit - Google Patents
Prevent direct power drive circuit Download PDFInfo
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- CN205377797U CN205377797U CN201521097421.7U CN201521097421U CN205377797U CN 205377797 U CN205377797 U CN 205377797U CN 201521097421 U CN201521097421 U CN 201521097421U CN 205377797 U CN205377797 U CN 205377797U
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Abstract
The utility model relates to a prevent direct power drive circuit, including PWM signal generator, half -bridge drive circuit, first switch tube and second switch pipe. This PWM signal generator produces a PWM signal and the two PWM signal opposite with a PWM signal phase. This half -bridge drive circuit has first input end, second input, first drive end and a second drive end, and a PWM signal and the 2nd PWM signal are imported respectively with this second input to this first input end, and this half -bridge drive circuit includes a delay element, the 2nd delay element, delay control unit, a power drive ware and the 2nd power drive ware, can control the blind spot time between the switching on of two switch tubes according to the in service behavior. This first switch tube and this second switch pipe are established ties between power end and earthing terminal, and this first drive end of the control end of this first switch tube connection, and this second drive end is connected to the control end of this second switch pipe.
Description
Technical field
This utility model relates to circuit field, especially relates to a kind of anti-straight-through power driving circuit.
Background technology
In various amplifying circuits, output signal is mostly as the output of driving device and is supplied to load, for instance broadcast, the output of communication transmitter, the output stage of sound system and control system drive etc..All kinds of multistage amplifier circuits, except should having voltage amplifier, also require there is power amplification circuit, in order to have the output of certain power, are used for providing power to load.
When simulated power amplifying circuit is due to work, transistor (such as audion or field effect transistor) is in linear amplification region, and power consumption is very big.Although what can adopt push-pull type output minimizing transistor bears power, but when relatively high power supply voltage and relatively high power, power device still has very big threat, so simulated power amplifying circuit has no idea to solve high efficiency, powerful problem.
Pulse width modulation (PWM) square-wave signal that prime is exported by D class power amplification circuit is added to the grid of transistor, by controlling its switch, thus realizing amplifying.D class power amplification circuit compares analog amplify circuit the outstanding feature of high efficiency, low distortion.But D class power amplification circuit there is also a problem, can cause when being exactly rising edge and the trailing edge overlong time of pwm signal that moment upper and lower two transistors simultaneously turn on, instantaneous power and ground short circuit, electric current is very big, power device can be caused to damage, have very big potential safety hazard.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of anti-straight-through power driving circuit, it is possible to reduce the risk that power device damages.
This utility model employed technical scheme comprise that the anti-straight-through power driving circuit of proposition one for solving above-mentioned technical problem, including PWM signal generator, half-bridge drive circuit, the first switching tube and second switch pipe.This PWM signal generator produces the first pwm signal and the second pwm signal with this first pwm signal opposite in phase.This half-bridge drive circuit has first input end, the second input, the first drive end and the second drive end, this first input end and this second input input this first pwm signal and this second pwm signal respectively, and this half-bridge drive circuit includes: the first delay unit, having the first end, the second end and control end, the first end of this first delay unit connects this first input end；Second delay unit, has the first end, the second end and controls end, and the first end of this second delay unit connects this second input；Delays time to control unit, connects the control end controlling end and this second delay unit of this first delay unit；First analog line driver, connects the second end of this first delay unit and this first drive end to export the first power drive signal；And second analog line driver, connect the second end of this second delay unit and this second drive end to export the second power drive signal, this first power drive signal and this second power drive signal；This first switching tube and this second switch pipe are connected between the powered end and the ground end, and the control end of this first switching tube connects this first drive end, and the control end of this second switch pipe connects this second drive end.
In an embodiment of the present utility model, anti-straight-through power driving circuit also includes the first level translator, second electrical level transducer, the first low-voltage lock circuit and the second low-voltage lock circuit, this first level translator is connected between this first delay unit and this first analog line driver, this the second low-voltage lock circuit connects this second electrical level transducer, this second electrical level transducer is connected between this second delay unit and this second analog line driver, and this second low-voltage lock circuit connects this second electrical level transducer.
In an embodiment of the present utility model, this half-bridge drive circuit is IC chip.
In an embodiment of the present utility model, this first switching tube and this second switch pipe are field effect transistor, control end respectively its grid controlling end and this second switch pipe of this first switching tube.
In an embodiment of the present utility model, the source electrode of this first switching tube connects the drain electrode of this second switch pipe, and the drain electrode of this first switching tube connects power end, and the drain electrode of this second switch pipe connects earth terminal.
This utility model is owing to adopting above technical scheme; so as to compared with prior art; there is following remarkable advantage: the Dead Time between the conducting of two switching tubes can be controlled according to service condition; the situation avoiding the overlong time by pwm pulse signal rising and falling edges and cause switching tube to simultaneously turn on; protection drive circuit, it is ensured that power amplification circuit also can safe and reliable work under higher supply voltage.
Accompanying drawing explanation
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent, below in conjunction with accompanying drawing, detailed description of the invention of the present utility model is elaborated, wherein:
Fig. 1 illustrates the circuit block diagram of the anti-straight-through power driving circuit of utility model one embodiment.
Fig. 2 illustrates the drive waveforms figure of anti-straight-through power driving circuit shown in Fig. 1.
Fig. 3 illustrates the circuit block diagram of the anti-straight-through power driving circuit of another embodiment of utility model.
Detailed description of the invention
Fig. 1 illustrates the circuit block diagram of the anti-straight-through power driving circuit of utility model one embodiment.Refer to shown in Fig. 1, the anti-straight-through power driving circuit 100 of the present embodiment includes PWM signal generator 110, half-bridge drive circuit the 120, first switching tube 132 and second switch pipe 134.PWM signal generator 110 produces the first pwm signal PWM1 and the second pwm signal PWM2.The frequency of the second pwm signal PWM2 and the first pwm signal PWM1 is identical, opposite in phase.At this, the frequency of the pwm signal that PWM signal generator 110 exports is 1-300KHz, and dutycycle is adjustable.
Half-bridge drive circuit 120 has first input end H, the second input L, the first drive end HG, the second drive end LG, power input HC, HS, LC and LS.Power input HC connects LC, power input HS by diode and is connected between the first switching tube 132 and second switch pipe 134, and is connected by electric capacity between HC and HS.Power input LC is connected to the low tension source of 5V～20V, LS ground connection.First input end H and the second input L inputs the first pwm signal PWM1 and the second pwm signal PWM2 respectively.The internal structure of half-bridge drive circuit 120 includes first delay unit the 121, second delay unit 122, delays time to control unit the 123, first analog line driver 124 and the second analog line driver 125.First delay unit 121 has the first end, the second end and controls end, and this first end connects the first input end H of half-bridge drive circuit 120, introduces the first pwm signal PWM1.Second delay unit 122, has the first end, the second end and controls end, and this first end connects the second input L of half-bridge drive circuit 120, introduces the second pwm signal PWM2.First delay unit 121 and the second delay unit 122 are able to signal carries out certain time delay τ 1, τ 2.Delays time to control unit 123, connects the control end controlling end and the second delay unit 122 of the first delay unit 121, to control the delay parameter τ 1, τ 2 of the first delay unit 121 and the second delay unit 122.
First analog line driver 124 connects the second end of the first delay unit 121 and the first drive end HG of half-bridge drive circuit 120 to export the first power drive signal S1.Second analog line driver 125 connects the second end of the second delay unit 122 and the second drive end LG of half-bridge drive circuit 120 to export the second power drive signal S2.
First switching tube 132 and second switch pipe 134 are connected between power end VDD and earth terminal GND, and first switching tube 132 control end connect half-bridge drive circuit 120 the first drive end HG, second switch pipe 134 control end connect half-bridge drive circuit 120 the second drive end LG.
In the present embodiment, the delays time to control unit 123 of half-bridge drive circuit 120 can arrange according to inside and automatically process signal, make to keep between the first drive end HG and the second drive end LG significant level (such as high level) driving signal S1, S2 exported respectively the low level time of certain time, be Dead Time.Fig. 2 illustrates the drive waveforms figure of anti-straight-through power driving circuit shown in Fig. 1.With reference to, shown in Fig. 2, all having one section of low level clearance G between high level and the high level of two driving signal S2 of the first driving signal S1.This can effectively be avoided overlong time in ascending and descending process, causes the situation that the first switching tube 132 and second switch pipe 134 simultaneously turn on, it is ensured that the work that power amplification circuit also can be safe and reliable under very high voltage.And, this design need not do any process during PWM signal generator 110 output pwm signal.If it addition, PWM signal generator 110 is made mistakes, two-way pwm signal is high simultaneously, and half-bridge drive circuit 120 also can close the output of the first drive end HG timely, protects load.
Fig. 3 illustrates the circuit block diagram of the anti-straight-through power driving circuit of another embodiment of utility model.Refer to shown in Fig. 3, the anti-straight-through power driving circuit 300 of the present embodiment includes PWM signal generator 310, half-bridge drive circuit the 320, first switching tube 332 and second switch pipe 334.PWM signal generator 310 produces the first pwm signal PWM1 and the second pwm signal PWM2.The frequency of the second pwm signal PWM2 and the first pwm signal PWM1 is identical, opposite in phase.At this, the frequency of the pwm signal that PWM signal generator 310 exports is 1-300KHz, and dutycycle is adjustable.
Half-bridge drive circuit 320 has first input end H, the second input L, the first drive end HG, the second drive end LG, power input HC, HS, LC and LS.Power input HC, HS, LC and LS connect power end VDD and earth terminal GND respectively.First input end H and the second input L inputs the first pwm signal PWM1 and the second pwm signal PWM2 respectively.The internal structure of half-bridge drive circuit 320 includes first delay unit the 321, second delay unit 322, delays time to control unit the 323, first analog line driver 324 and the second analog line driver 325.First delay unit 321 has the first end, the second end and controls end, and this first end connects the first input end H of half-bridge drive circuit 320, introduces the first pwm signal PWM1.Second delay unit 322, has the first end, the second end and controls end, and this first end connects the second input L of half-bridge drive circuit 320, introduces the second pwm signal PWM2.First delay unit 321 and the second delay unit 322 are able to signal carries out certain time delay τ 1, τ 2.Delays time to control unit 323, connects the control end controlling end and the second delay unit 322 of the first delay unit 321, to control the delay parameter τ 1, τ 2 of the first delay unit 321 and the second delay unit 322.
First analog line driver 324 connects the second end of the first delay unit 321 and the first drive end HG of half-bridge drive circuit 320 to export the first power drive signal S1.Second analog line driver 325 connects the second end of the second delay unit 322 and the second drive end LG of half-bridge drive circuit 320 to export the second power drive signal S2.
The half-bridge drive circuit 320 of the present embodiment also includes the first level translator 326, second electrical level transducer the 327, first low-voltage locking (UnderVoltageLockoutCircuit, UVLO) circuit 328 and the second low-voltage lock circuit 329.First level translator 326 is connected between the first delay unit 321 and the first analog line driver 324.First low-voltage lock circuit 328 connects the first level translator 326.Second electrical level transducer 327 is connected between the second delay unit 321 and the second analog line driver 324, and the second low-voltage lock circuit 329 connects second electrical level transducer 327.
First switching tube 332 and second switch pipe 334 are connected between power end VDD and earth terminal GND, and first switching tube 332 control end connect half-bridge drive circuit 320 the first drive end HG, second switch pipe 334 control end connect half-bridge drive circuit 320 the second drive end LG.
It addition, in the present embodiment, the first switching tube 332 and second switch pipe 334 can be field effect transistor, control end respectively its grid controlling end and second switch pipe 334 of the first switching tube 332.It addition, the source electrode of the first switching tube 332 connects the drain electrode of second switch pipe 334, the drain electrode of the first switching tube 332 connects power end VDD, and the drain electrode of second switch pipe 334 connects earth terminal GND.
In Fig. 1 and embodiment illustrated in fig. 3, PWM signal generator can be embodied as single-chip microcomputer.Half-bridge drive circuit can be embodied as IC chip.
Although this utility model describes with reference to current specific embodiment, but those of ordinary skill in the art will be appreciated that, above embodiments is intended merely to explanation this utility model, change or the replacement of various equivalence also can be made when without departing from this utility model spirit, therefore, as long as to the change of above-described embodiment, modification all by the scope dropping on following claims in spirit of the present utility model.
Claims (5)
1. an anti-straight-through power driving circuit, including PWM signal generator, half-bridge drive circuit, the first switching tube and second switch pipe, it is characterised in that:
This PWM signal generator produces the first pwm signal and the second pwm signal with this first pwm signal opposite in phase；
This half-bridge drive circuit has first input end, the second input, the first drive end and the second drive end, this first input end and this second input and inputs this first pwm signal and this second pwm signal respectively, and this half-bridge drive circuit includes:
First delay unit, has the first end, the second end and controls end, and the first end of this first delay unit connects this first input end；
Second delay unit, has the first end, the second end and controls end, and the first end of this second delay unit connects this second input；
Delays time to control unit, connects the control end controlling end and this second delay unit of this first delay unit；
First analog line driver, connects the second end of this first delay unit and this first drive end to export the first power drive signal；And
Second analog line driver, connects the second end of this second delay unit and this second drive end to export the second power drive signal, this first power drive signal and this second power drive signal；
This first switching tube and this second switch pipe are connected between the powered end and the ground end, and the control end of this first switching tube connects this first drive end, and the control end of this second switch pipe connects this second drive end.
2. anti-straight-through power driving circuit as claimed in claim 1, it is characterized in that, also include the first level translator, second electrical level transducer, the first low-voltage lock circuit and the second low-voltage lock circuit, this first level translator is connected between this first delay unit and this first analog line driver, this the second low-voltage lock circuit connects this second electrical level transducer, this second electrical level transducer is connected between this second delay unit and this second analog line driver, and this second low-voltage lock circuit connects this second electrical level transducer.
3. anti-straight-through power driving circuit as claimed in claim 1, it is characterised in that this half-bridge drive circuit is IC chip.
4. anti-straight-through power driving circuit as claimed in claim 1, it is characterised in that this first switching tube and this second switch pipe are field effect transistor, control end respectively its grid controlling end and this second switch pipe of this first switching tube.
5. anti-straight-through power driving circuit as claimed in claim 4, it is characterised in that the source electrode of this first switching tube connects the drain electrode of this second switch pipe, and the drain electrode of this first switching tube connects power end, and the drain electrode of this second switch pipe connects earth terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521097421.7U CN205377797U (en) | 2015-12-24 | 2015-12-24 | Prevent direct power drive circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521097421.7U CN205377797U (en) | 2015-12-24 | 2015-12-24 | Prevent direct power drive circuit |
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| CN205377797U true CN205377797U (en) | 2016-07-06 |
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| CN201521097421.7U Active CN205377797U (en) | 2015-12-24 | 2015-12-24 | Prevent direct power drive circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107204762A (en) * | 2017-05-04 | 2017-09-26 | 河北新华北集成电路有限公司 | A kind of high pressure NMOS driver dead-time control circuit |
| CN108199708A (en) * | 2017-12-21 | 2018-06-22 | 大唐恩智浦半导体有限公司 | A kind of gate drive circuit, method and apparatus |
-
2015
- 2015-12-24 CN CN201521097421.7U patent/CN205377797U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107204762A (en) * | 2017-05-04 | 2017-09-26 | 河北新华北集成电路有限公司 | A kind of high pressure NMOS driver dead-time control circuit |
| CN107204762B (en) * | 2017-05-04 | 2020-12-22 | 河北新华北集成电路有限公司 | Dead time control circuit of high-voltage NMOS driver |
| CN108199708A (en) * | 2017-12-21 | 2018-06-22 | 大唐恩智浦半导体有限公司 | A kind of gate drive circuit, method and apparatus |
| CN108199708B (en) * | 2017-12-21 | 2021-06-11 | 大唐恩智浦半导体有限公司 | Gate drive circuit, method and device |
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