CN205355051U - Multilayer semiconductor package - Google Patents
Multilayer semiconductor package Download PDFInfo
- Publication number
- CN205355051U CN205355051U CN201521143330.2U CN201521143330U CN205355051U CN 205355051 U CN205355051 U CN 205355051U CN 201521143330 U CN201521143330 U CN 201521143330U CN 205355051 U CN205355051 U CN 205355051U
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- CN
- China
- Prior art keywords
- semiconductor chip
- aluminium lamination
- lager
- layer
- thickness
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a multilayer semiconductor package, including base plate and shell, the shell is provided with the four layers, by outward to the interior division maybe first aluminium lamination, resin layer, second aluminium lamination and mould the layer, be provided with first adhesive layer between first aluminium lamination and the resin layer, be provided with the second adhesive layer between resin layer and the second aluminium lamination, the inside enhancement layer that is provided with of second aluminium lamination, the surface of enhancement layer is the cockscomb structure setting, the mould is moulded in situ portion and is provided with the 2nd semiconductor chip, the 2nd semiconductor chip is provided with more than one, be electric connection between the 2nd semiconductor chip, be range upon range of formula setting between the 2nd semiconductor chip, the design of this multilayer semiconductor package is simple, intensity is big, stable in structure, heat dispersion is good goes with insulating properties.
Description
Technical field
This utility model relates to a kind of multi-lager semiconductor encapsulation.
Background technology
Semiconductor packages refers to processes, according to product type and functional requirement, the process obtaining individual chips by the wafer passing through to test.Encapsulation process is: the wafer from wafer front road technique is cut into little wafer by after scribing process, then the wafer glue of well cutting is mounted on the island of corresponding frame substrate, recycle ultra-fine plain conductor or electroconductive resin and the bond pad of wafer is connected to the respective pins of substrate, and constitute required circuit；Then again to independent wafer cabinet packaging protection in addition, it is also performed to sequence of operations after plastic packaging, after having encapsulated, carries out finished product test, generally go through into operations such as inspection, test and packagings, finally put shipment in storage.There is the shortcomings such as intensity is low, structure is not sufficiently stable, heat dispersion is good not in existing semiconductor packages.
Utility model content
The technical problems to be solved in the utility model be to provide a kind of design simple, intensity big, the multi-lager semiconductor encapsulation of Stability Analysis of Structures, perfect heat-dissipating and good insulation preformance.
For solving above-mentioned technical problem, this utility model adopts the following technical scheme that
A kind of multi-lager semiconductor encapsulation, include substrate and shell, described shell is provided with four layers, it is the first aluminium lamination from outside to inside respectively, resin bed, second aluminium lamination and molding layer, it is provided with the first adhesive layer between described first aluminium lamination and resin bed, the second adhesive layer it is provided with between described resin bed and the second aluminium lamination, described second aluminium lamination is internally provided with enhancement Layer, the surface indentation of described enhancement Layer is arranged, described molding layer is internally provided with the second semiconductor chip, described second semiconductor chip is provided with more than one, for being electrically connected between described second semiconductor chip, it is stacked setting between described second semiconductor chip, described molding layer is arranged below the first semiconductor chip, described first semiconductor chip and the second semiconductor chip are electrically connected, the length of described first semiconductor chip is less than the length of the second semiconductor chip, it is provided with joint sheet bottom described first semiconductor chip, described joint sheet is connected with electrical property of substrate, described first semiconductor chip both sides are provided with supporting member, described base plate bottom is provided with ball bonding pad, described ball bonding pad and substrate are for being electrically connected, described ball bonding pad is provided with connection terminal.
As preferably, the thickness of described first aluminium lamination is 0.02-0.03cm.
As preferably, the thickness of described resin bed is 0.03-0.05cm.
As preferably, the thickness of described second aluminium lamination is 0.03-0.06cm.
As preferably, the height of described shell is 0.5-0.6cm.
As preferably, the thickness of described substrate is 0.1-0.2cm.
As preferably, described second aluminium lamination and molding layer are that integral type is arranged, and make structure more firm.
As preferably, the thickness of described supporting member is 0.08-0.1cm.
The beneficial effects of the utility model are: the encapsulation design of this multi-lager semiconductor is simple, by being equipped with of the first aluminium lamination, resin bed, the second aluminium lamination and molding layer, substantially increases heat dispersion and the insulating properties of semiconductor packages；By being internally provided with enhancement Layer at the second aluminium lamination, the surface indentation of this enhancement Layer is arranged, and considerably improves the intensity of semiconductor packages；This multi-lager semiconductor encapsulation chip chamber adopts stacked setting, even if the chip of its stacking up has more than the size of the chip being arranged below, it is possible to guarantee structural stability.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of multi-lager semiconductor encapsulation of this utility model.
Detailed description of the invention
As shown in Figure 1, a kind of multi-lager semiconductor encapsulation, include substrate 2 and shell 1, described shell 1 is provided with four layers, it is the first aluminium lamination 3 from outside to inside respectively, resin bed 4, second aluminium lamination 5 and molding layer 9, it is provided with the first adhesive layer 8 between described first aluminium lamination 3 and resin bed 4, it is provided with the second adhesive layer 7 between described resin bed 4 and the second aluminium lamination 5, described second aluminium lamination 5 is internally provided with enhancement Layer 6, the surface indentation of described enhancement Layer 6 is arranged, described molding layer 9 is internally provided with the second semiconductor chip 10, described second semiconductor chip 10 is provided with more than one, for being electrically connected between described second semiconductor chip 10, it is stacked setting between described second semiconductor chip 10, described molding layer 6 is arranged below the first semiconductor chip 12, described first semiconductor chip 12 and the second semiconductor chip 10 are electrically connected, the length of described first semiconductor chip 12 is less than the length of the second semiconductor chip 12, it is provided with joint sheet 13 bottom described first semiconductor chip 12, described joint sheet 13 is electrically connected with substrate 2, described first semiconductor chip 12 both sides are provided with supporting member 11, it is provided with ball bonding pad 14 bottom described substrate 2, described ball bonding pad 14 and substrate 2 are for being electrically connected, described ball bonding pad 14 is provided with connection terminal 15.
The thickness of described first aluminium lamination 3 is 0.02-0.03cm.
The thickness of described resin bed 4 is 0.03-0.05cm.
The thickness of described second aluminium lamination 5 is 0.03-0.06cm.
The height of described shell 1 is 0.5-0.6cm.
The thickness of described substrate 2 is 0.1-0.2cm.
Described second aluminium lamination 5 is arranged for integral type with molding layer 9, makes structure more firm.
The thickness of described supporting member 11 is 0.08-0.1cm.
The beneficial effects of the utility model are: the encapsulation design of this multi-lager semiconductor is simple, by being equipped with of the first aluminium lamination, resin bed, the second aluminium lamination and molding layer, substantially increases heat dispersion and the insulating properties of semiconductor packages；By being internally provided with enhancement Layer at the second aluminium lamination, the surface indentation of this enhancement Layer is arranged, and considerably improves the intensity of semiconductor packages；This multi-lager semiconductor encapsulation chip chamber adopts stacked setting, even if the chip of its stacking up has more than the size of the chip being arranged below, it is possible to guarantee structural stability.
The above, be only detailed description of the invention of the present utility model, but protection domain of the present utility model be not limited thereto, any change expected without creative work or replacement, all should be encompassed within protection domain of the present utility model.
Claims (8)
1. a multi-lager semiconductor encapsulation, it is characterized in that: include substrate and shell, described shell is provided with four layers, it is the first aluminium lamination from outside to inside respectively, resin bed, second aluminium lamination and molding layer, it is provided with the first adhesive layer between described first aluminium lamination and resin bed, the second adhesive layer it is provided with between described resin bed and the second aluminium lamination, described second aluminium lamination is internally provided with enhancement Layer, the surface indentation of described enhancement Layer is arranged, described molding layer is internally provided with the second semiconductor chip, described second semiconductor chip is provided with more than one, for being electrically connected between described second semiconductor chip, it is stacked setting between described second semiconductor chip, described molding layer is arranged below the first semiconductor chip, described first semiconductor chip and the second semiconductor chip are electrically connected, the length of described first semiconductor chip is less than the length of the second semiconductor chip, it is provided with joint sheet bottom described first semiconductor chip, described joint sheet is connected with electrical property of substrate, described first semiconductor chip both sides are provided with supporting member, described base plate bottom is provided with ball bonding pad, described ball bonding pad and substrate are for being electrically connected, described ball bonding pad is provided with connection terminal.
2. a kind of multi-lager semiconductor encapsulation according to claim 1, it is characterised in that: the thickness of described first aluminium lamination is 0.02-0.03cm.
3. a kind of multi-lager semiconductor encapsulation according to claim 2, it is characterised in that: the thickness of described resin bed is 0.03-0.05cm.
4. a kind of multi-lager semiconductor encapsulation according to claim 3, it is characterised in that: the thickness of described second aluminium lamination is 0.03-0.06cm.
5. a kind of multi-lager semiconductor encapsulation according to claim 4, it is characterised in that: the height of described shell is 0.5-0.6cm.
6. a kind of multi-lager semiconductor encapsulation according to claim 5, it is characterised in that: the thickness of described substrate is 0.1-0.2cm.
7. a kind of multi-lager semiconductor encapsulation according to claim 6, it is characterised in that: described second aluminium lamination and molding layer are that integral type is arranged.
8. a kind of multi-lager semiconductor encapsulation according to claim 7, it is characterised in that: the thickness of described supporting member is 0.08-0.1cm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521143330.2U CN205355051U (en) | 2015-12-31 | 2015-12-31 | Multilayer semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521143330.2U CN205355051U (en) | 2015-12-31 | 2015-12-31 | Multilayer semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205355051U true CN205355051U (en) | 2016-06-29 |
Family
ID=56173504
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521143330.2U Expired - Fee Related CN205355051U (en) | 2015-12-31 | 2015-12-31 | Multilayer semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205355051U (en) |
-
2015
- 2015-12-31 CN CN201521143330.2U patent/CN205355051U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160629 Termination date: 20191231 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |