CN205193965U

CN205193965U - Ware is raced to be first to answer a question to multichannel based on FPGA

Info

Publication number: CN205193965U
Application number: CN201520747419.3U
Authority: CN
Inventors: 于万霞
Original assignee: Tianjin University of Technology
Current assignee: Tianjin University of Technology
Priority date: 2015-09-25
Filing date: 2015-09-25
Publication date: 2016-04-27
Anticipated expiration: 2025-09-25

Abstract

The utility model discloses a ware is raced to be first to answer a question to multichannel based on FPGA, circuit arrangement includes: FPGA main control unit, button module, clock module, charactron display module, LED indicating module, power module, buzzer module, downloader module. Race to be the first to answer a question the group in the inside realization of FPGA main control unit and distinguish and latch the function, race to be the first to answer a question timing function of beginning back, each number of components statistics function, charactron decoding drives function, input clock signal frequency division function. Such design has reduced the quantity of outside required chip, the circuit has characteristics of small, simple structure, low power dissipation, and FPGA has a high restructural nature moreover, very easily the product the later stage extension and upgrade.

Description

A kind of Multiple-Line-Snatch-Answer-Machine based on FPGA

Technical field

The utility model relates to a kind of Multiple-Line-Snatch-Answer-Machine.

Background technology

At present, mostly conventional question-and-answer game apparatus is to adopt single-chip microcomputer to be that core controls, and the chip that this system uses is many, and along with the increase of function, circuit is more complicated, and is unfavorable for the upgrading of product.Based on FPGA Multiple-Line-Snatch-Answer-Machine due to fpga chip inside realize race to be the first to answer a question the functions such as discriminating, Coding and driving, timing, score, frequency division, external chip quantity greatly reduces, so system bulk is little, low in energy consumption, circuit structure is simple, and the portability of simultaneity factor is strong.

Utility model content

There is baroque problem for existing Multiple-Line-Snatch-Answer-Machine, the utility model provides a kind of Multiple-Line-Snatch-Answer-Machine based on FPGA, and the utility model structure is relatively simple, and system bulk is little, described below.

A kind of Multiple-Line-Snatch-Answer-Machine based on FPGA, circuit arrangement comprises: FPGA master controller, key-press module, clock module, numeral method module, LED indicating module, power module, hummer module, downloader module, it is characterized in that, described key-press module is connected with described FPGA master controller; Described clock module is connected with described FPGA master controller; Described numeral method module is connected with described FPGA master controller; Described LED indicating module is connected with described FPGA master controller; Described hummer module is connected with described FPGA master controller; Described power module is connected with described FPGA master controller; Described downloader module is connected with described FPGA master controller.

Described charactron adopts the working method of Dynamic Announce.

Described key-press module comprises races to be the first to answer a question load button, system reset pad, races to be the first to answer a question start button, mark reset button, and count down time loads and adjustment button.

Described FPGA model is EP3C25F324C8N.

The beneficial effect of the technical scheme that the utility model provides is: realize racing to be the first to answer a question group with fpga chip in inside and differentiate and latch function, race to be the first to answer a question countdown function after starting, each number of components statistical function, charactron Coding and driving function, input clock signal division function, such design decreases the quantity of outside required chip, reduces system complexity, improves the competitiveness of product in market; And FPGA has the reconfigurability of height, be highly susceptible to later stage expansion and the upgrading of product.

Accompanying drawing explanation

Fig. 1 is the structural representation of the Multiple-Line-Snatch-Answer-Machine based on FPGA.

Fig. 2 is the design concept figure of FPGA internal circuit.

Embodiment

For making the purpose of this utility model, technical scheme and advantage clearly, below in conjunction with accompanying drawing, the utility model embodiment is described in further detail.

Based in the Multiple-Line-Snatch-Answer-Machine of FPGA, the internal resource of FPGA should be made full use of, thus reduce the quantity of extended chip.Realization approach of the present utility model realizes racing to be the first to answer a question player to differentiate in fpga chip inside and latch, race to be the first to answer a question countdown after starting, each number of components statistics, charactron Coding and driving, input clock signal division function, the outside Input/Output Device only connecting necessity.

Based on above-mentioned analysis, the utility model provides a kind of Multiple-Line-Snatch-Answer-Machine based on FPGA, see Fig. 1 and Fig. 2, described below.

As specific embodiment, please refer to shown in Fig. 1.Should comprise based on the Multiple-Line-Snatch-Answer-Machine circuit arrangement of FPGA: FPGA master controller, key-press module, clock module, numeral method module, LED indicating module, power module, hummer module, downloader module, it is characterized in that, described key-press module is connected with described FPGA master controller, realize system reset, count down time adjustment, race to be the first to answer a question beginning, mark Protection Counter Functions; Described clock module is connected with described FPGA master controller provides system reference clock; Described numeral method module is connected with described FPGA master controller and carries out racing to be the first to answer a question the display of group number, each number of components and count down time; Described LED indicating module is connected with described FPGA master controller, races to be the first to answer a question group with LED instruction; Described hummer module is connected with described FPGA master controller and carries out count down time to reminding; Described power module is connected with described FPGA master controller; Described downloader module is connected with described FPGA master controller the download of the program that realizes.

In practical application, what charactron adopted is 16 7 sections of common cathode charactrons; Fpga chip is EP3C25F324C8N.

As specific embodiment, the design concept figure based on the Multiple-Line-Snatch-Answer-Machine of FPGA refers to Fig. 2.QD module realizes racing to be the first to answer a question discriminating latch function, and RST is system reset end, and A, B, C, D are four and race to be the first to answer a question input end; JSQ module realizes countdown function, and LD, AT, BT are time adjustment end, and EN is for racing to be the first to answer a question commencing signal, and BEEP is that count down time arrives prompting end; JFQ module realizes scoring functions, and RST1 is mark clear terminal, ADD and SUB is respectively bonus point and deduction end; FPQ module realizes division function, and for system provides required clock signal, the external 1MHZ clock signal of CLK pin, produces 1HZ and 1KHZ signal respectively to JSQ and YMQ by FPQ module; YMQ module realizes the Coding and driving function of charactron.

The foregoing is only preferred embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection domain of the present utility model.

Claims

1. the Multiple-Line-Snatch-Answer-Machine based on FPGA, circuit arrangement comprises: FPGA master controller, key-press module, clock module, numeral method module, LED indicating module, power module, hummer module, downloader module, it is characterized in that, described key-press module is connected with described FPGA master controller, realize system reset, count down time adjustment, race to be the first to answer a question beginning, mark Protection Counter Functions; Described clock module is connected with described FPGA master controller provides system reference clock; Described numeral method module is connected with described FPGA master controller and carries out racing to be the first to answer a question the display of group number, each number of components and count down time; Described LED indicating module is connected with described FPGA master controller, races to be the first to answer a question group with LED instruction; Described hummer module is connected with described FPGA master controller and carries out count down time to reminding; Described power module is connected with described FPGA master controller; Described downloader module is connected with described FPGA master controller the download of the program that realizes.

2. a kind of Multiple-Line-Snatch-Answer-Machine based on FPGA according to claim 1, is characterized in that, described FPGA model is EP3C25F324C8N.