CN205092262U - Led chip - Google Patents
Led chip Download PDFInfo
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- CN205092262U CN205092262U CN201520816594.3U CN201520816594U CN205092262U CN 205092262 U CN205092262 U CN 205092262U CN 201520816594 U CN201520816594 U CN 201520816594U CN 205092262 U CN205092262 U CN 205092262U
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Abstract
The utility model discloses a LED chip, LED chip follows and upwards includes in proper order down: a substrate. Be located buffer layer on the substrate, be located N type semiconductor layer on the buffer layer, be located luminescent layer on the N type semiconductor layer, be located P type semiconductor layer on the luminescent layer, be formed with the P electrode on the P type semiconductor layer, LED chip is located the step on the buffer layer last still including, be equipped with the N electrode on the step, P electrode and N electrode respectively with P type semiconductor layer and N type semiconductor layer electric connection, whole or partial the setting to the inclined plane of lateral wall of step. The utility model discloses a burying deeply of N electrode is realized to sculpture all or partial buffer layer, reduces the height of N electrode to it goes out light absorption, the luminous luminance that has effectively improved LED chip to reduce the chip lateral wall.
Description
Technical field
The utility model relates to technical field of semiconductor luminescence, particularly relates to a kind of LED chip.
Background technology
Light-emitting diode (Light-EmittingDiode, LED) is a kind of semiconductor electronic component that can be luminous.This electronic component occurred as far back as 1962, and can only send the ruddiness of low luminosity in early days, develop other monochromatic versions afterwards, the light that can send even to this day is throughout visible ray, infrared ray and ultraviolet, and luminosity also brings up to suitable luminosity.And purposes is also by the beginning as indicator light, display panel etc.; Along with the continuous progress of technology, light-emitting diode has been widely used in display, television set daylighting decoration and illumination.
Ginseng Fig. 1 a, 1b are depicted as the structural representation of LED chip in prior art, it comprises substrate 10 ', resilient coating 20 ', n type semiconductor layer 30 ', luminescent layer 40 ', p type semiconductor layer 50 ' from bottom to top successively, wherein, be formed with a step 60 ' in the upper etching of n type semiconductor layer 30 ', step 60 ' and p type semiconductor layer 50 ' are respectively equipped with the N electrode 70 ' and P electrode 80 ' that are electrically connected with n type semiconductor layer 30 ' and p type semiconductor layer 50 '.
Early stage LED development concentrates on and improves in its internal quantum, mainly adopt with the following method: build brilliant structure by improving to build brilliant quality and change, electric energy is made not easily to convert heat energy to, and then indirectly improve the luminous efficiency of LED, thus can obtain the theoretical internal quantum of about 70%, but such internal quantum is almost close to the theoretic limit.
And the light extraction efficiency of chip refers to the photon that component internal produces, after the absorption of assembly itself, refraction, reflection, the photon number that reality can measure at component external.Thus known, the refringence of material that the factor affecting extraction efficiency also comprises the absorption of LED chip material itself, the geometry of chip, chip use and the light scattering characteristic etc. of modular construction.In order to improve the light extraction efficiency of LED chip to greatest extent, in LED technology is in the past improved, do different improvement for the above some factor.Optimal design as chip geometry has surface coarsening, ITO (IndiumTinOxide (In
2o
3+ SnO
2)) alligatoring, flip-chip, vertical stratification, photonic crystal etc.But, N electrode cannot be avoided in said method to the absorption of chip sidewall bright dipping, the luminous efficiency of LED chip is exerted a certain influence.
Therefore, for above-mentioned technical problem, be necessary to provide a kind of LED chip.
Utility model content
The purpose of this utility model is to provide a kind of LED chip.
To achieve these goals, the technical scheme that provides of the utility model embodiment is as follows:
A kind of LED chip, described LED chip comprises from bottom to top successively:
Substrate;
Be positioned at the resilient coating on described substrate;
Be positioned at the n type semiconductor layer on described resilient coating;
Be positioned at the luminescent layer on described n type semiconductor layer;
Be positioned at the p type semiconductor layer on described luminescent layer;
Described p type semiconductor layer is formed with P electrode, LED chip also comprises the step be positioned on resilient coating, described step is provided with N electrode, and described P electrode and N electrode are electrically connected with p type semiconductor layer and n type semiconductor layer respectively, and the sidewall of described step is all or part of is set to inclined-plane.
As further improvement of the utility model, the bottom surface of described step lower than resilient coating upper surface and be not less than the lower surface of resilient coating.
As further improvement of the utility model, described step comprises the some first steps be formed on n type semiconductor layer and the second step be formed on resilient coating, described N electrode is located on second step, the sidewall of described second step is set to inclined-plane, and the angle on described inclined-plane and vertical direction is 10 ~ 60 °.
As further improvement of the utility model, the sidewall Epitaxial growth of described second step has insulating barrier, and described insulating barrier is isolation buffer layer and N electrode at least.
As further improvement of the utility model, described N electrode comprises the N electrode main part that is positioned on second step bottom surface and to be positioned at outside insulating barrier and the N electrode extension be electrically connected with N electrode main part and n type semiconductor layer, and described N electrode main part and n type semiconductor layer are electrically connected by N electrode extension.
As further improvement of the utility model, be also provided with transparency conducting layer outside described insulating barrier, described N electrode main part and n type semiconductor layer are electrically connected by transparency conducting layer and N electrode extension.
As further improvement of the utility model, the sidewall of described second step is set to plane or the curved surface of inclination, and the lateral surface of insulating barrier is the plane or curved surface that are obliquely installed.
The beneficial effects of the utility model are:
The utility model realizes the buried of N electrode by etching all or part of resilient coating, reduces the height of N electrode, thus reduces the absorption of chip sidewall bright dipping, effectively improves the luminosity of LED chip.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 a is the planar structure schematic diagram of LED chip in prior art.
Fig. 1 b is the cross section structure schematic diagram of LED chip in prior art.
Fig. 2 a is the planar structure schematic diagram of LED chip in the utility model first execution mode.
Fig. 2 b is the cross section structure schematic diagram of LED chip in the utility model first execution mode.
Fig. 2 c is the structural representation that in the utility model first execution mode, LED chip is topped bar.
Fig. 3 is the cross section structure schematic diagram of LED chip in the utility model second execution mode.
Fig. 4 is the cross section structure schematic diagram of LED chip in the utility model the 3rd execution mode.
Embodiment
Technical scheme in the utility model is understood better in order to make those skilled in the art person, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all should belong to the scope of the utility model protection.
In addition, label or the sign of repetition may be used in various embodiments.These repeat only clearly to describe the utility model in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.
Shown in ginseng Fig. 2 a, 2b, in the first execution mode of the present utility model, LED chip comprises from bottom to up successively:
Substrate 10, substrate can be sapphire, Si, SiC, GaN, ZnO etc.;
Resilient coating 20, resilient coating can be GaN etc.;
N type semiconductor layer 30, n type semiconductor layer can be N-type GaN etc.;
Luminescent layer 40, luminescent layer can be GaN, InGaN etc.;
P type semiconductor layer 50, p type semiconductor layer can be P type GaN etc.;
P type semiconductor layer 50 is formed with P electrode 80, LED chip also comprises the step 60 be positioned on resilient coating 20, step is provided with N electrode 70, and P electrode 80 and N electrode 70 are electrically connected with p type semiconductor layer 50 and n type semiconductor layer 30 respectively.
Wherein, in present embodiment, step 60 is formed on resilient coating 20, the bottom surface of step lower than resilient coating upper surface and be not less than the lower surface of resilient coating, below in conjunction with Fig. 2 c, the step 60 in present embodiment is further described.
Shown in composition graphs 2c, step 60 comprises the first step 61 be formed on n type semiconductor layer 30 and the second step 62 be formed on resilient coating 20, N electrode 70 comprises the N electrode main part 701 that is positioned on second step 62 bottom surface and to be positioned at outside insulating barrier and the N electrode extension 702 be electrically connected with N electrode main part 701 and n type semiconductor layer 30, this N electrode extension is segmentation arrangement on second step 62, shown in concrete ginseng Fig. 2 a, certain N electrode extension also can as a wholely be arranged on second step 62.Wherein, the bottom surface of second step 62 lower than resilient coating 20 upper surface and be not less than the lower surface of resilient coating 20, the sidewall of second step 62 is set to inclined-plane, and this inclined-plane can be the plane that is obliquely installed or curved surface, is described in present embodiment for plane; The bottom surface of first step 61 lower than n type semiconductor layer 30 upper surface and higher than the lower surface of n type semiconductor layer, the sidewall of first step 61 is vertical setting.
In the utility model, the sidewall of second step 62 is set to inclined-plane, angle on this inclined-plane and vertical direction is 10 ~ 60 °, the object arranging this inclined-plane is when adopting plating or other modes to grow N electrode, the formation of N electrode extension 702 can be convenient to, the end of final N electrode extension 702 terminates on the bottom surface of first step 61, if and this inclined-plane is vertical plane, then cannot form N electrode extension thereon.
In order to ensure the insulation between N electrode 70 and resilient coating 20, there is insulating barrier 90 at the sidewall Epitaxial growth of second step 62.Shown in ginseng Fig. 2 b, in present embodiment, the lateral surface of insulating barrier 92 is cambered surface, and insulating barrier 92 from the top down width increase gradually.Insulating barrier can be other shapes in other embodiments, and its lateral surface can be also plane etc., illustrates no longer one by one, as long as the insulating barrier that can realize insulation effect between N electrode and resilient coating all belongs to the scope that the utility model is protected at this.
Further, transparency conducting layer (not shown) also can be provided with in the present embodiment between N electrode extension 702 and insulating barrier 90 lateral surface, transparency conducting layer and n type semiconductor layer are electrically connected, N electrode main part 701 is electrically connected with n type semiconductor layer 30 by transparency conducting layer and N electrode extension 702, connects effect better.Preferably, this transparency conducting layer is ITO transparency conducting layer, also can be ZITO, ZIO, GIO, ZTO, FTO, AZO, GZO, In in other embodiments
4sn
3o
12, the transparency conducting layer such as NiAu, further, transparency conducting layer can be one deck, also can be two or more combination layer structure in above-mentioned transparency conducting layer.
Correspondingly, the preparation method of LED chip in present embodiment, specifically comprises the following steps:
S1, provide a substrate;
S2, on substrate epitaxial growth buffer, n type semiconductor layer, luminescent layer and p type semiconductor layer successively;
S3, etching p type semiconductor layer, luminescent layer, n type semiconductor layer and resilient coating form step, and the sidewall sections of step is set to inclined-plane;
Present embodiment comprises:
Adopt dry etching or wet-etching technology etching p type semiconductor layer, luminescent layer and part n type semiconductor layer to form first step, control the parameter in etching technics, make the sidewall of first step roughly in vertical plane;
Dry etching or wet-etching technology is adopted to continue etching N type semiconductor layer and all or part of resilient coating, form second step, control the parameter in etching technics, make the sidewall of second step be inclined-plane, and the angle on this inclined-plane and vertical direction is 10 ~ 60 °.
S4, on p type semiconductor layer and step, prepare the P electrode and N electrode that are electrically connected with p type semiconductor layer and n type semiconductor layer respectively, specifically comprise:
The P electrode that preparation and p type semiconductor layer are electrically connected on p type semiconductor layer;
At the sidewall Epitaxial growth insulating barrier of second step, and form with the bottom surface of second step the N electrode be electrically connected with n type semiconductor layer outside insulating barrier.
Second step bottom surface in present embodiment and the bottom surface of resilient coating contour, namely during second time etching, resilient coating is etched to substrate surface, so can reduce the height residing for N electrode as far as possible, thus reduce the absorption of chip sidewall bright dipping, certainly also can determine as the case may be in other embodiments, the etched portions resilient coating when meeting light extraction efficiency.
Ginseng Figure 3 shows that the structural representation of LED chip in the utility model second execution mode, and identical with the first execution mode, it comprises from bottom to up successively:
Substrate 10; Resilient coating 20; N type semiconductor layer 30; Luminescent layer 40; P type semiconductor layer 50;
P type semiconductor layer 50 is formed with P electrode 80, LED chip also comprises the step 60 be positioned on resilient coating 20, step is provided with N electrode 70, and P electrode 80 and N electrode 70 are electrically connected with p type semiconductor layer 50 and n type semiconductor layer 30 respectively.
With the first execution mode unlike, only comprise a step 60 in present embodiment, the sidewall of step 60 is all set to inclined-plane.Similarly, have the insulating barrier 90 for insulating at the sidewall peripheral hardware of resilient coating 20, N electrode 70 comprises the N electrode main part 701 that is positioned on step 60 bottom surface and to be positioned at outside insulating barrier 90 and the N electrode extension 702 be electrically connected with N electrode main part 701 and n type semiconductor layer 30.
Correspondingly, the preparation method of LED chip in present embodiment, specifically comprises the following steps:
S1, provide a substrate;
S2, on substrate epitaxial growth buffer, n type semiconductor layer, luminescent layer and p type semiconductor layer successively;
S3, etching p type semiconductor layer, luminescent layer, n type semiconductor layer and resilient coating form step, and the sidewall of step is all set to inclined-plane;
Preferably, by controlling the parameter in etching technics in this step, make the sidewall of step be inclined-plane, and the angle on this inclined-plane and vertical direction is 10 ~ 60 °.
S4, on p type semiconductor layer and step, prepare the P electrode and N electrode that are electrically connected with p type semiconductor layer and n type semiconductor layer respectively, specifically comprise:
The P electrode that preparation and p type semiconductor layer are electrically connected on p type semiconductor layer;
At the sidewall Epitaxial growth insulating barrier of resilient coating, and form with the bottom surface of step the N electrode be electrically connected with n type semiconductor layer outside insulating barrier.
Ginseng Figure 4 shows that the structural representation of LED chip in the utility model the 3rd execution mode, and identical with the first execution mode, it comprises from bottom to up successively:
Substrate 10; Resilient coating 20; N type semiconductor layer 30; Luminescent layer 40; P type semiconductor layer 50;
P type semiconductor layer 50 is formed with P electrode 80, LED chip also comprises the step 60 be positioned on resilient coating 20, step is provided with N electrode 70, and P electrode 80 and N electrode 70 are electrically connected with p type semiconductor layer 50 and n type semiconductor layer 30 respectively.
With the first execution mode unlike, in present embodiment, step 60 is set to three rank, and it comprises two first steps 611,612 be positioned on n type semiconductor layer 30 and the second step 62 be positioned on resilient coating 20, and the sidewall of second step 62 is set to inclined-plane.Similarly, second step 62 the sidewall peripheral hardware N electrode main part 701 that has insulating barrier 90 for insulating, N electrode 70 to comprise to be positioned on second step 62 bottom surface and to be positioned at outside insulating barrier 90 and the N electrode extension 702 be electrically connected with first step on N electrode main part 701 and n type semiconductor layer 611,612.
Correspondingly, the preparation method of LED chip in present embodiment, specifically comprises the following steps:
S1, provide a substrate;
S2, on substrate epitaxial growth buffer, n type semiconductor layer, luminescent layer and p type semiconductor layer successively;
S3, etching p type semiconductor layer, luminescent layer, n type semiconductor layer and resilient coating form step, and the sidewall sections of step is set to inclined-plane;
Present embodiment comprises:
Adopt dry etching or wet-etching technology etching p type semiconductor layer, luminescent layer and part n type semiconductor layer to form two first steps successively, control the parameter in etching technics, make the sidewall of first step roughly in vertical plane;
Dry etching or wet-etching technology is adopted to continue etching N type semiconductor layer and all or part of resilient coating, form second step, control the parameter in etching technics, make the sidewall of second step be inclined-plane, and the angle on this inclined-plane and vertical direction is 10 ~ 60 °.
S4, on p type semiconductor layer and step, prepare the P electrode and N electrode that are electrically connected with p type semiconductor layer and n type semiconductor layer respectively, specifically comprise:
The P electrode that preparation and p type semiconductor layer are electrically connected on p type semiconductor layer;
At the sidewall Epitaxial growth insulating barrier of second step, and form with the bottom surface of second step the N electrode be electrically connected with n type semiconductor layer outside insulating barrier.
As can be seen from the above technical solutions, compared with prior art, the utility model realizes the buried of N electrode by etching all or part of resilient coating, reduces the height of N electrode, thus reduce the absorption of chip sidewall bright dipping, effectively improve the luminosity of LED chip.
To those skilled in the art, obvious the utility model is not limited to the details of above-mentioned one exemplary embodiment, and when not deviating from spirit of the present utility model or essential characteristic, can realize the utility model in other specific forms.Therefore, no matter from which point, all should embodiment be regarded as exemplary, and be nonrestrictive, scope of the present utility model is limited by claims instead of above-mentioned explanation, and all changes be therefore intended in the implication of the equivalency by dropping on claim and scope are included in the utility model.Any Reference numeral in claim should be considered as the claim involved by limiting.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should by specification integrally, and the technical scheme in each embodiment also through appropriately combined, can form other execution modes that it will be appreciated by those skilled in the art that.
Claims (7)
1. a LED chip, is characterized in that, described LED chip comprises from bottom to top successively:
Substrate;
Be positioned at the resilient coating on described substrate;
Be positioned at the n type semiconductor layer on described resilient coating;
Be positioned at the luminescent layer on described n type semiconductor layer;
Be positioned at the p type semiconductor layer on described luminescent layer;
Described p type semiconductor layer is formed with P electrode, LED chip also comprises the step be positioned on resilient coating, described step is provided with N electrode, and described P electrode and N electrode are electrically connected with p type semiconductor layer and n type semiconductor layer respectively, and the sidewall of described step is all or part of is set to inclined-plane.
2. LED chip according to claim 1, is characterized in that, the bottom surface of described step lower than resilient coating upper surface and be not less than the lower surface of resilient coating.
3. LED chip according to claim 1, it is characterized in that, described step comprises the some first steps be formed on n type semiconductor layer and the second step be formed on resilient coating, described N electrode is located on second step, the sidewall of described second step is set to inclined-plane, and the angle on described inclined-plane and vertical direction is 10 ~ 60 °.
4. LED chip according to claim 3, is characterized in that, the sidewall Epitaxial growth of described second step has insulating barrier, and described insulating barrier is isolation buffer layer and N electrode at least.
5. LED chip according to claim 4, it is characterized in that, described N electrode comprises the N electrode main part that is positioned on second step bottom surface and to be positioned at outside insulating barrier and the N electrode extension be electrically connected with N electrode main part and n type semiconductor layer, and described N electrode main part and n type semiconductor layer are electrically connected by N electrode extension.
6. LED chip according to claim 5, is characterized in that, is also provided with transparency conducting layer outside described insulating barrier, and described N electrode main part and n type semiconductor layer are electrically connected by transparency conducting layer and N electrode extension.
7. LED chip according to claim 3, is characterized in that, the sidewall of described second step is set to plane or the curved surface of inclination, and the lateral surface of insulating barrier is the plane or curved surface that are obliquely installed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520816594.3U CN205092262U (en) | 2015-10-20 | 2015-10-20 | Led chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520816594.3U CN205092262U (en) | 2015-10-20 | 2015-10-20 | Led chip |
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| Publication Number | Publication Date |
|---|---|
| CN205092262U true CN205092262U (en) | 2016-03-16 |
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| CN201520816594.3U Active CN205092262U (en) | 2015-10-20 | 2015-10-20 | Led chip |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336827A (en) * | 2015-10-20 | 2016-02-17 | 聚灿光电科技股份有限公司 | Led chip and preparation method thereof |
| CN114335281A (en) * | 2021-12-31 | 2022-04-12 | 淮安澳洋顺昌光电技术有限公司 | Semiconductor light-emitting element, preparation method thereof and LED chip |
-
2015
- 2015-10-20 CN CN201520816594.3U patent/CN205092262U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105336827A (en) * | 2015-10-20 | 2016-02-17 | 聚灿光电科技股份有限公司 | Led chip and preparation method thereof |
| CN114335281A (en) * | 2021-12-31 | 2022-04-12 | 淮安澳洋顺昌光电技术有限公司 | Semiconductor light-emitting element, preparation method thereof and LED chip |
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