CN204993288U - Time switch of anti -interference high accuracy - Google Patents
Time switch of anti -interference high accuracy Download PDFInfo
- Publication number
- CN204993288U CN204993288U CN201520777307.2U CN201520777307U CN204993288U CN 204993288 U CN204993288 U CN 204993288U CN 201520777307 U CN201520777307 U CN 201520777307U CN 204993288 U CN204993288 U CN 204993288U
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- triode
- resistance
- nand gate
- relay
- switch
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Abstract
The utility model discloses a time switch of anti -interference high accuracy, including NAND gate U1, relay J, triode V2 and switch S1, switch S1's one end connecting resistance R2, triode V3's projecting pole, power VCC and load A, switch S1's other end connecting resistance R4, resistance R4's other end connecting resistance R5 and triode V1's base, electric capacity C2, electric capacity C3, resistance R7, diode D4's positive pole, triode V1's projecting pole, relay J and relay J's contact J -1 is connected to resistance R5's the other end. The utility model discloses time switch of anti -interference high accuracy circuit structure is simple, components and parts are few, adopts two NOT AND door module constitution oscillators, and the quiescent power dissipation is low, and the precision is high, through the purpose that reaches the timing control load that switches on of control triode and relay, consequently has the advantage that the cost of manufacture is hanged down, is consumed low battery and stable performance.
Description
Technical field
The utility model relates to a kind of timing switch, specifically a kind of anti-interference high-precision timing switch.
Background technology
Timing switch is the widely used switching component of current electronic applications, be widely used in delay control system, but the timing switch most of the time is in idle state, most of timing switch is good not for the process of quiescent dissipation in the market, cause the quiescent dissipation of timing switch when not working very large, and the loss of timing switch components and parts can be increased, existing timing switch uses electrochemical capacitor as delay cell simultaneously, its leakage current is very large, thus the charging and discharging time is often affected, cause timing accuracy inadequate.
Utility model content
The purpose of this utility model is to provide a kind of anti-interference high-precision timing switch, to solve the problem proposed in above-mentioned background technology.
For achieving the above object, the utility model provides following technical scheme:
A kind of anti-interference high-precision timing switch, comprise NAND gate U1, relay J, triode V2 and switch S 1, one end contact resistance R2 of described switch S 1, the emitter of triode V3, power supply VCC and load A, the other end contact resistance R4 of switch S 1, the other end contact resistance R5 of resistance R4 and the base stage of triode V1, the other end of resistance R5 connects electric capacity C2, electric capacity C3, resistance R7, the anode of diode D4, the emitter of triode V1, the contact J-1 of relay J and relay J, the collector electrode of triode V1 connects the other end of electric capacity C2, the negative electrode of diode D2 and two of NAND gate U3 inputs, the output contact resistance R1 of NAND gate U3, two inputs of NAND gate U1 and the anode of diode D3, the other end of resistance R1 connects electric capacity C1, the negative electrode of diode D1 and resistance R3, the anode of diode D1 connects a stiff end of potentiometer RP1 and the sliding end of potentiometer RP1, the other end of another stiff end chain connecting resistance R3 of potentiometer RP1, resistance R6, the output of NAND gate U1 and two of NAND gate U2 inputs, the output of NAND gate U2 connects the other end of electric capacity C1, the other end of the negative electrode contact resistance R7 of diode D3, the other end of electric capacity C3 and two of NAND gate U4 inputs, the output contact resistance R8 of NAND gate U4, the base stage of the other end connecting triode V2 of resistance R8, the other end of emitter contact resistance R2 of triode V2 and the base stage of triode V3, the collector electrode of the collector electrode connecting triode V2 of triode V3, the negative electrode of diode D4 and the other end of relay J, the other end of the contact J-1 of relay J connects the other end of load A.
As preferred version of the present utility model: described not gate U1 ~ not gate U4 is four NAND gate modules of CD4011 chip internal.
Compared with prior art, the beneficial effects of the utility model are: the anti-interference high-precision timing switch circuit structure of the utility model is simple, components and parts are few, adopt two NAND gate module composition oscillators, quiescent dissipation is low, precision is high, reached the object of timing controlled load by the conducting controlling triode and relay, therefore have that cost of manufacture is low, power consumption is low and the advantage of stable performance.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of anti-interference high-precision timing switch.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
Refer to Fig. 1, a kind of anti-interference high-precision timing switch, comprise NAND gate U1, relay J, triode V2 and switch S 1, one end contact resistance R2 of described switch S 1, the emitter of triode V3, power supply VCC and load A, the other end contact resistance R4 of switch S 1, the other end contact resistance R5 of resistance R4 and the base stage of triode V1, the other end of resistance R5 connects electric capacity C2, electric capacity C3, resistance R7, the anode of diode D4, the emitter of triode V1, the contact J-1 of relay J and relay J, the collector electrode of triode V1 connects the other end of electric capacity C2, the negative electrode of diode D2 and two of NAND gate U3 inputs, the output contact resistance R1 of NAND gate U3, two inputs of NAND gate U1 and the anode of diode D3, the other end of resistance R1 connects electric capacity C1, the negative electrode of diode D1 and resistance R3, the anode of diode D1 connects a stiff end of potentiometer RP1 and the sliding end of potentiometer RP1, the other end of another stiff end chain connecting resistance R3 of potentiometer RP1, resistance R6, the output of NAND gate U1 and two of NAND gate U2 inputs, the output of NAND gate U2 connects the other end of electric capacity C1, the other end of the negative electrode contact resistance R7 of diode D3, the other end of electric capacity C3 and two of NAND gate U4 inputs, the output contact resistance R8 of NAND gate U4, the base stage of the other end connecting triode V2 of resistance R8, the other end of emitter contact resistance R2 of triode V2 and the base stage of triode V3, the collector electrode of the collector electrode connecting triode V2 of triode V3, the negative electrode of diode D4 and the other end of relay J, the other end of the contact J-1 of relay J connects the other end of load A.
Described not gate U1 ~ not gate U4 is four NAND gate modules of CD4011 chip internal.
Operation principle of the present utility model is: U1 and U2 is connected to form oscillator, and operating frequency is 2 hertz, and C2 is charging capacitor.The input terminal voltage of U3 is very low, and therefore, its output presents high-tension electricity.When U1 be input as high potential time, oscillator is started working.The D1 conducting when the output of U1 is positive voltage, potentiometer RP1 controls the charging current entering C1.And the discharging current of C1 can only be flowed out by R1.A series of positive pulses to the charging voltage of C1 like this.Its width is regulated by potentiometer RP1.Positive pulse is charged to C2 by R6, D2.Be flushed to its voltage when reaching the enabling voltage of U3, U3 overturns always.Output LOW voltage.The output of U1 is caused to become high potential.Thus the charging of C2 can complete rapidly.U4 also overturns.Carry out power amplification by V2, V3, promote the contact J-1 action of relay J, thus reach the object of timing controlled load A.In addition, when relay J action, battery voltage ripple may be caused to cause relay contact to be shaken.In order to eliminate this phenomenon, D3, C3, R7 are set up in addition.Triode TR1 makes capacitor C2 discharge device when being used to allow switch activated.
Claims (2)
1. an anti-interference high-precision timing switch, comprise NAND gate U1, relay J, triode V2 and switch S 1, it is characterized in that, one end contact resistance R2 of described switch S 1, the emitter of triode V3, power supply VCC and load A, the other end contact resistance R4 of switch S 1, the other end contact resistance R5 of resistance R4 and the base stage of triode V1, the other end of resistance R5 connects electric capacity C2, electric capacity C3, resistance R7, the anode of diode D4, the emitter of triode V1, the contact J-1 of relay J and relay J, the collector electrode of triode V1 connects the other end of electric capacity C2, the negative electrode of diode D2 and two of NAND gate U3 inputs, the output contact resistance R1 of NAND gate U3, two inputs of NAND gate U1 and the anode of diode D3, the other end of resistance R1 connects electric capacity C1, the negative electrode of diode D1 and resistance R3, the anode of diode D1 connects a stiff end of potentiometer RP1 and the sliding end of potentiometer RP1, the other end of another stiff end chain connecting resistance R3 of potentiometer RP1, resistance R6, the output of NAND gate U1 and two of NAND gate U2 inputs, the output of NAND gate U2 connects the other end of electric capacity C1, the other end of the negative electrode contact resistance R7 of diode D3, the other end of electric capacity C3 and two of NAND gate U4 inputs, the output contact resistance R8 of NAND gate U4, the base stage of the other end connecting triode V2 of resistance R8, the other end of emitter contact resistance R2 of triode V2 and the base stage of triode V3, the collector electrode of the collector electrode connecting triode V2 of triode V3, the negative electrode of diode D4 and the other end of relay J, the other end of the contact J-1 of relay J connects the other end of load A.
2. the anti-interference high-precision timing switch of one according to claim 1, is characterized in that, described not gate U1 ~ not gate U4 is four NAND gate modules of CD4011 chip internal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520777307.2U CN204993288U (en) | 2015-10-09 | 2015-10-09 | Time switch of anti -interference high accuracy |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520777307.2U CN204993288U (en) | 2015-10-09 | 2015-10-09 | Time switch of anti -interference high accuracy |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204993288U true CN204993288U (en) | 2016-01-20 |
Family
ID=55127607
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520777307.2U Expired - Fee Related CN204993288U (en) | 2015-10-09 | 2015-10-09 | Time switch of anti -interference high accuracy |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204993288U (en) |
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2015
- 2015-10-09 CN CN201520777307.2U patent/CN204993288U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160120 Termination date: 20161009 |