CN210404817U - Time-delay power-off power supply based on super capacitor - Google Patents
Time-delay power-off power supply based on super capacitor Download PDFInfo
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- CN210404817U CN210404817U CN201921831383.1U CN201921831383U CN210404817U CN 210404817 U CN210404817 U CN 210404817U CN 201921831383 U CN201921831383 U CN 201921831383U CN 210404817 U CN210404817 U CN 210404817U
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Abstract
The utility model discloses a time delay outage power based on super capacitor, include: the pre-stage filter circuit is connected with a power supply; one end of the first resistor is connected with the preceding stage filter circuit; the anode of the first diode is connected with one end of the first resistor, and the cathode of the first diode is connected with the other end of the first resistor; the anode of the first capacitor is connected with the other end of the first resistor, and the cathode of the first capacitor is a grounding end; the anode of the second diode is connected with the cathode of the first diode; the two ends of the third diode are connected with the two ends of the second diode; one end of the control circuit is connected with the cathode of the second diode; a power conversion circuit connected to the other end of the control circuit; a post-stage filter circuit, one end of which is connected with the power conversion circuit; and one end of the sampling circuit is connected with the post-stage filter circuit, and the other end of the sampling circuit is connected with the output end. The utility model discloses can accomplish the function of power outage time delay effectively.
Description
Technical Field
The utility model relates to a power application technology field, concretely relates to time delay outage power supply based on super capacitor.
Background
The sudden nature of power supply system fault or voltage sag fault easily causes many consumer to be unable normal work at the outage moment, for example the task machine of record important data, and applied UPS or battery in many occasions, this is a fine solution, but in the environment that should not use UPS and battery, need to adopt the energy storage power supply of high power density to provide outage delay function for equipment such as task machine, just so provided new requirement for power supply, required the power to have outage delay function, however current power does not have outage delay function, like this after the power cut-off, consumer will unable normal work.
At present, the common power supply of many consumer does not have the function of time delay outage, under many circumstances, the power can short time outage or trouble, and then the power resumes to be normal again, consumer can restart like this, and some consumer can directly be bad or restart time can be very long, this is a concrete damage to consumer, under this condition, present power supply unit still can not solve the short time outage or the trouble of power, very big restriction the use of this kind of power, consequently, also make the equipment life who uses this kind of power too short, thereby the application of this kind of power has been restricted.
SUMMERY OF THE UTILITY MODEL
The utility model relates to a developed a time delay outage power based on super capacitor. The utility model aims to charge the super capacitor through the resistance when the power supply system starts to work through the charging and discharging technology of the charging energy storage circuit; when the power supply system is closed, fails or temporarily drops, the super capacitor starts to discharge to supply power for the task machine system, and current is transmitted to the power conversion circuit through the diode, so that the task machine is maintained to work for a short time, and data safety in electric equipment is guaranteed.
The utility model provides a technical scheme does:
a super capacitor based time delay power-off power supply, comprising:
the pre-stage filter circuit is connected with a power supply; and
one end of the first resistor is connected with the preceding stage filter circuit;
the anode of the first diode is connected with one end of the first resistor, and the cathode of the first diode is connected with the other end of the first resistor;
the anode of the first capacitor is connected with the other end of the first resistor, and the cathode of the first capacitor is a grounding end;
the anode of the second diode is connected with the cathode of the first diode;
the anode of the third diode is connected with the anode of the second diode, and the cathode of the third diode is connected with the cathode of the second diode;
one end of the control circuit is connected with the cathode of the second diode;
a power conversion circuit connected to the other end of the control circuit;
a post-stage filter circuit, one end of which is connected with the power conversion circuit;
one end of the sampling circuit is connected with the post-stage filter circuit, and the other end of the sampling circuit is connected with the output end;
the post-stage filter circuit and the sampling circuit are both connected with the control circuit.
Preferably, the pre-filter circuit includes:
the filter capacitor is arranged between the positive electrode and the negative electrode of the power supply;
the negative electrode of the second capacitor is connected with the positive electrode of the filter capacitor, and the positive electrode of the second capacitor is a grounding end;
the third capacitor is connected in parallel to two ends of the second capacitor, and the positive electrode of the third capacitor is connected with the negative electrode of the filter capacitor;
the common mode inductor comprises a first joint, a second joint, a third joint and a fourth joint;
the first connecting point and the third connecting point are connected between the filter capacitor and the third capacitor, and the second connecting point is connected with the anode of the first diode;
a fourth capacitor disposed between the second junction and the fourth junction, and grounded between the fourth capacitor and the fourth junction.
Preferably, the control circuit includes:
the chip comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin;
a collector of the first triode is connected with the other end of the second diode;
a second resistor, one end of which is connected with the emitter of the first triode,
one end of the third resistor is connected with the other end of the second resistor, and the other end of the third resistor is connected with the negative electrode of the first capacitor;
one end of the fourth resistor is connected between the second resistor and the third resistor, and the other end of the fourth resistor is connected with the collector of the first triode;
one end of the fifth resistor is connected with the base electrode of the first triode;
a collector of the second triode is connected with the other end of the fifth resistor, a base of the second triode is connected between the second resistor and the third resistor, and a grid of the second triode is connected with the negative electrode of the first capacitor;
a sixth resistor, one end of which is connected between the collector of the second triode and the fifth resistor, and the other end of which is connected between the collector of the first triode and the fourth resistor;
a gate of the MOS transistor is connected between a collector of the second triode and the sixth resistor, a source of the MOS transistor is connected with a negative electrode of the first capacitor, and a drain of the MOS transistor is connected with the second pin;
one end of the seventh resistor is connected between the drain electrode of the MOS tube and the second pin;
one end of the fifth capacitor is connected with the other end of the seventh resistor, and the other end of the fifth capacitor is connected with the source electrode of the MOS tube;
a sixth capacitor, wherein the anode and the cathode of the sixth capacitor are respectively connected to the source electrode of the MOS tube and the drain electrode of the MOS tube;
a seventh capacitor, one end of which is connected with the fourth pin;
one end of the eighth capacitor is connected with the other end of the seventh capacitor, and the other end of the eighth capacitor is connected with the first pin;
the seventh capacitor and the fourth pin are grounded, and an eighth pin and a collector of the first triode are respectively connected between the seventh capacitor and the eighth capacitor;
and one end of the ninth capacitor is connected with the seventh pin, and the other end of the ninth capacitor is connected with the fifth pin.
Preferably, the power conversion circuit includes:
an eighth resistor having one end connected between the eighth pin and the collector of the first transistor,
a drain electrode of the field effect transistor is connected with the other end of the eighth resistor, a grid electrode of the field effect transistor is connected with a sixth pin, and a source electrode of the field effect transistor is connected between the fifth pin and the ninth capacitor;
a ninth resistor, two ends of which are respectively connected with two ends of the eighth resistor;
a tenth resistor, one end of which is connected between the eighth resistor and the first pin, and the other end of which is connected to the drain of the field effect transistor;
and the anode of the tenth capacitor is connected to one end of the ninth resistor, and the cathode of the tenth capacitor is connected to the other end of the ninth resistor.
Preferably, the post-stage filter circuit includes:
an eleventh resistor, one end of which is connected to the source of the field effect transistor,
one end of the eleventh capacitor is connected with the other end of the eleventh resistor, and the other end of the eleventh capacitor is connected with the third pin;
wherein ground is provided between the eleventh capacitor and the third pin, and a negative terminal of the output is connected between the eleventh capacitor and the third pin;
one end of the inductor is connected with the source electrode of the field effect transistor, and the other end of the inductor is connected with the anode of the output end;
one end of the fourth diode is connected between the source electrode of the field effect transistor and the inductor, and the other end of the fourth diode is connected between the eleventh capacitor and the third pin;
and one end of the twelfth capacitor is connected between the inductor and the anode of the output end, and the other end of the twelfth capacitor is connected between the fourth diode and the third pin.
Preferably, the sampling circuit includes:
a twelfth resistor having one end connected between the inductor and the positive electrode of the output terminal,
a thirteenth resistor having one end connected to the other end of the twelfth resistor,
a fourteenth resistor, one end of which is connected to the other end of the thirteenth resistor, and the other end of which is connected between the twelfth capacitor and the third pin;
and a third pin is connected between the thirteenth resistor and the fourteenth resistor.
Compared with the prior art, the utility model beneficial effect who has:
the utility model provides a super capacitor can keep the normal work of consumer not influenced in the short time outage to super capacitor's volume ratio UPS is little, than the longe-lived of using the battery, more environmental protection, and the circuit is simpler, and the consumption is little, and the effect is big, strong adaptability, the reliability is high, can accomplish the function of power outage delay effectively.
Drawings
Fig. 1 is a schematic block diagram of the circuit according to the present invention.
Fig. 2 is a schematic circuit diagram of the present invention.
Fig. 3 is a schematic diagram of charging and discharging currents of the super capacitor according to the present invention.
Fig. 4 is a discharge curve diagram of the super capacitor of the present invention.
Detailed Description
The present invention is further described in detail below with reference to the drawings so that those skilled in the art can implement the invention with reference to the description.
A supercapacitor is an electric double layer capacitor, and is also called a "capacitive battery" because it has a large capacity and behaves as a battery to the outside. The basic principle of the method is the same as that of other kinds of double-layer capacitors, and the extra-large capacity is obtained by using an electric double-layer structure consisting of an activated carbon porous electrode and an electrolyte. As shown in fig. 4, as the capacitance of the supercapacitor discharges, the voltage decreases. The super capacitor has many advantages, firstly, the super capacitor has high charging speed, and the charging time is 10 seconds to 10 minutes, so that the rated capacity of the super capacitor can reach more than 95 percent; secondly, the super capacitor has long cycle service life, the cycle use frequency of deep charge and discharge can reach 1-50 ten thousand times, and no memory effect exists; thirdly, the super capacitor has super-strong large-current discharge capacity, high energy conversion efficiency and small process loss, and the large-current energy circulation efficiency is not less than 90 percent; fourthly, the power density of the super capacitor is high and can reach 300W/KG to 5000W/KG, which is 5-10 times of that of the battery.
As shown in fig. 1, for the utility model discloses a circuit schematic block diagram, the utility model discloses constitute by preceding stage filter circuit, charging circuit, tank circuit, control circuit, power conversion circuit, back level filter circuit, sampling circuit and control chip, wherein preceding stage filter circuit includes: a filter capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4 and a common mode inductor L1; the charging circuit and the energy storage circuit comprise: a first fourth resistor R14, a first capacitor C5, a first diode D1, a second diode D2, and a third diode D3; the control circuit includes: the circuit comprises a control chip U1, a first triode Q1, a second resistor R2, a third resistor R5, a fourth resistor R1, a fifth resistor R3, a second triode Q2, a sixth resistor R4, an MOS transistor Q3, a seventh resistor R6, a fifth capacitor C8, a sixth capacitor C7, a seventh capacitor C9, an eighth capacitor C10 and a ninth tenth capacitor C12; the power conversion circuit includes: an eighth resistor R7, a field effect transistor Q4, a ninth resistor R8, a tenth resistor R9 and a tenth capacitor C12; the post-stage filter circuit includes: an eleventh resistor R10, an eleventh capacitor C13, a twelfth capacitor C14, a fourth diode D4 and an inductor L2; the sampling circuit includes: a twelfth resistor R11, a thirteenth resistor R12 and a fourteenth resistor R13.
As shown in fig. 2, which is a schematic circuit diagram according to the present invention, wherein the control chip U1 includes a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin, a filter capacitor C1 is connected between the positive and negative electrodes of the 24V power supply, the negative electrode of the filter capacitor C1 is connected to the ground through the third capacitor C3, the positive electrode of the filter capacitor C1 is connected to the ground through the second capacitor C2, the positive electrode of the third capacitor C3 is connected to the contact 1 and the contact 3 of the common mode inductor L1, the fourth capacitor C4 is connected between the contact 2 and the contact 4 of the common mode inductor L1, the negative electrode of the fourth capacitor C4 is a ground terminal, the contact 2 is connected to the positive electrode of the first capacitor C5 through the first fourth resistor R14, a first diode D1 is further connected between the first capacitor C5 and the contact 2, the negative electrode of the first capacitor C5 is connected to the ground terminal of the fourth capacitor C4, the anode of the second diode D2 is connected to the junction 2, the cathode of the second diode D2 is connected to the ground through the fourth resistor R1 and the third resistor R5, both end terminals of the third diode D3 are connected to the anode and the cathode of the second diode D2, the collector of the first transistor Q1 is connected to the cathode of the capacitor D2, the emitter of the first transistor Q1 is connected to the ground through the second resistor R2 and the third resistor R5, the base of the first transistor Q1 is connected to the collector of the second transistor Q2 through the fifth resistor R3, the base of the second transistor Q2 is connected to the ground through the third resistor R5, the gate of the second transistor Q5 is connected to the ground of the fourth capacitor C5, the collector of the second diode D5 and the collector of the second transistor Q5 are connected through the sixth resistor R5, the gate of the MOS transistor Q5 is connected to the collector of the second transistor Q5, the source of the MOS transistor Q5 is connected to the ground of the fourth capacitor C5, and the drain of the MOS transistor Q5 is connected to the drain of the fourth capacitor C5, a seventh resistor R6 and a fifth capacitor C8 are connected to both ends of the sixth capacitor C7, the drain of the MOS transistor Q3 is connected to the second pin of the control chip U1, the fourth pin and the eighth pin of the control chip U1 are connected through the seventh capacitor C9 at right angles, the seventh capacitor C9 is grounded, the eighth pin of the control chip U1 is connected to the first pin of the control chip U1 through the filter eighth capacitor C10, the anode of the filter eighth capacitor C10 is connected to the cathode of the second diode D2, the first pin of the control chip U1 is connected to the anode of the eighth capacitor C10 through a tenth resistor R9 and a tenth capacitor C12, a ninth resistor R8 is connected between the anode and the cathode of the tenth capacitor C12, an eighth resistor R7 is connected to both ends of the ninth resistor R8, the drain of the fet Q4 is connected between the eighth resistor R4 and the gate of the sixth resistor Q4, a source of the field-effect transistor Q4 is connected to the fifth pin of the control chip U1, a seventh pin of the control chip U1 is connected to the fifth pin of the control chip U1 through a ninth capacitor C11, a source of the field-effect transistor Q4 is connected to the output terminal through an inductor L2, a source of the field-effect transistor Q4 is connected to the output terminal (ground terminal) through a fourth diode D4, an eleventh resistor R10 and an eleventh capacitor C13 are connected to both ends of a fourth diode D4, one end of a twelfth capacitor C14 is connected to the source of the field-effect transistor Q4 through an inductor L2, the other end of the twelfth capacitor C14 is connected to the output terminal (ground terminal), a twelfth resistor R11, a thirteenth resistor R12 and a fourteenth resistor R13 are connected to both ends of the twelfth capacitor C14, and the twelfth resistor R11, the thirteenth resistor R12 and the fourteenth resistor R13 are connected to the third pin of the control chip U1.
As shown in fig. 2 and 3, the first capacitor C5 is a super energy storage capacitor, and when the power supply system works normally, current is transmitted to the power conversion circuit through the second diode D2 and the third diode D3, and the first capacitor C5 is charged through the first fourth resistor R14; when the power supply system does not work normally, the discharge current of the first capacitor C5 is transmitted to the power conversion circuit through the diode D1, the second diode D2 and the third diode D3 to temporarily maintain the normal work of the power supply.
The utility model has the advantages that: the power-off delay power supply can keep normal work of the electric equipment unaffected in short-time power-off, the volume of the power supply is much smaller than that of a UPS (uninterrupted Power supply), the power supply has long service life and is more environment-friendly than a storage battery, a circuit is simpler, the power consumption is low, the effect is large, the adaptability is strong, the reliability is high, and the power-off delay function can be effectively completed.
While the embodiments of the invention have been described above, it is not intended to be limited to the details shown, or described, but rather to cover all modifications, which would come within the scope of the appended claims, and all changes which come within the meaning and range of equivalency of the art are therefore intended to be embraced therein.
Claims (6)
1. A time delay outage power supply based on super capacitor, its characterized in that includes:
the pre-stage filter circuit is connected with a power supply; and
one end of the first resistor is connected with the preceding stage filter circuit;
the anode of the first diode is connected with one end of the first resistor, and the cathode of the first diode is connected with the other end of the first resistor;
the anode of the first capacitor is connected with the other end of the first resistor, and the cathode of the first capacitor is a grounding end;
the anode of the second diode is connected with the cathode of the first diode;
the anode of the third diode is connected with the anode of the second diode, and the cathode of the third diode is connected with the cathode of the second diode;
one end of the control circuit is connected with the cathode of the second diode;
a power conversion circuit connected to the other end of the control circuit;
a post-stage filter circuit, one end of which is connected with the power conversion circuit;
one end of the sampling circuit is connected with the post-stage filter circuit, and the other end of the sampling circuit is connected with the output end;
the post-stage filter circuit and the sampling circuit are both connected with the control circuit.
2. The supercapacitor-based power supply according to claim 1, wherein the pre-filter circuit comprises:
the filter capacitor is arranged between the positive pole of the power supply and the negative pole of the power supply;
the negative electrode of the second capacitor is connected with the positive electrode of the filter capacitor, and the positive electrode of the second capacitor is a grounding end;
the third capacitor is connected in parallel to two ends of the second capacitor, and the positive electrode of the third capacitor is connected with the negative electrode of the filter capacitor;
the common mode inductor comprises a first joint, a second joint, a third joint and a fourth joint;
the first connecting point and the third connecting point are connected between the filter capacitor and the third capacitor, and the second connecting point is connected with the anode of the first diode;
a fourth capacitor disposed between the second junction and the fourth junction, and grounded between the fourth capacitor and the fourth junction.
3. The supercapacitor-based power supply according to claim 2, wherein the control circuit comprises:
the chip comprises a first pin, a second pin, a third pin, a fourth pin, a fifth pin, a sixth pin, a seventh pin and an eighth pin;
a collector of the first triode is connected with the other end of the second diode;
a second resistor, one end of which is connected with the emitter of the first triode,
one end of the third resistor is connected with the other end of the second resistor, and the other end of the third resistor is connected with the negative electrode of the first capacitor;
one end of the fourth resistor is connected between the second resistor and the third resistor, and the other end of the fourth resistor is connected with the collector of the first triode;
one end of the fifth resistor is connected with the base electrode of the first triode;
a collector of the second triode is connected with the other end of the fifth resistor, a base of the second triode is connected between the second resistor and the third resistor, and a grid of the second triode is connected with the negative electrode of the first capacitor;
a sixth resistor, one end of which is connected between the collector of the second triode and the fifth resistor, and the other end of which is connected between the collector of the first triode and the fourth resistor;
a gate of the MOS transistor is connected between a collector of the second triode and the sixth resistor, a source of the MOS transistor is connected with a negative electrode of the first capacitor, and a drain of the MOS transistor is connected with the second pin;
one end of the seventh resistor is connected between the drain electrode of the MOS tube and the second pin;
one end of the fifth capacitor is connected with the other end of the seventh resistor, and the other end of the fifth capacitor is connected with the source electrode of the MOS tube;
a sixth capacitor, wherein the anode and the cathode of the sixth capacitor are respectively connected to the source electrode of the MOS tube and the drain electrode of the MOS tube;
a seventh capacitor, one end of which is connected with the fourth pin;
one end of the eighth capacitor is connected with the other end of the seventh capacitor, and the other end of the eighth capacitor is connected with the first pin;
the seventh capacitor and the fourth pin are grounded, and an eighth pin and a collector of the first triode are respectively connected between the seventh capacitor and the eighth capacitor;
and one end of the ninth capacitor is connected with the seventh pin, and the other end of the ninth capacitor is connected with the fifth pin.
4. The supercapacitor-based power supply according to claim 3, wherein the power conversion circuit comprises:
an eighth resistor having one end connected between the eighth pin and the collector of the first transistor,
a drain electrode of the field effect transistor is connected with the other end of the eighth resistor, a grid electrode of the field effect transistor is connected with a sixth pin, and a source electrode of the field effect transistor is connected between the fifth pin and the ninth capacitor;
a ninth resistor, two ends of which are respectively connected with two ends of the eighth resistor;
a tenth resistor, one end of which is connected between the eighth resistor and the first pin, and the other end of which is connected to the drain of the field effect transistor;
and the anode of the tenth capacitor is connected to one end of the ninth resistor, and the cathode of the tenth capacitor is connected to the other end of the ninth resistor.
5. The supercapacitor-based power supply according to claim 4, wherein the post-filter circuit comprises:
an eleventh resistor, one end of which is connected to the source of the field effect transistor,
one end of the eleventh capacitor is connected with the other end of the eleventh resistor, and the other end of the eleventh capacitor is connected with the third pin;
wherein ground is provided between the eleventh capacitor and the third pin, and a negative terminal of the output is connected between the eleventh capacitor and the third pin;
one end of the inductor is connected with the source electrode of the field effect transistor, and the other end of the inductor is connected with the anode of the output end;
one end of the fourth diode is connected between the source electrode of the field effect transistor and the inductor, and the other end of the fourth diode is connected between the eleventh capacitor and the third pin;
and one end of the twelfth capacitor is connected between the inductor and the anode of the output end, and the other end of the twelfth capacitor is connected between the fourth diode and the third pin.
6. The supercapacitor-based power supply according to claim 5, wherein the sampling circuit comprises:
a twelfth resistor having one end connected between the inductor and the positive electrode of the output terminal,
a thirteenth resistor having one end connected to the other end of the twelfth resistor,
a fourteenth resistor, one end of which is connected to the other end of the thirteenth resistor, and the other end of which is connected between the twelfth capacitor and the third pin;
and a third pin is connected between the thirteenth resistor and the fourteenth resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921831383.1U CN210404817U (en) | 2019-10-29 | 2019-10-29 | Time-delay power-off power supply based on super capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921831383.1U CN210404817U (en) | 2019-10-29 | 2019-10-29 | Time-delay power-off power supply based on super capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210404817U true CN210404817U (en) | 2020-04-24 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921831383.1U Expired - Fee Related CN210404817U (en) | 2019-10-29 | 2019-10-29 | Time-delay power-off power supply based on super capacitor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210404817U (en) |
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2019
- 2019-10-29 CN CN201921831383.1U patent/CN210404817U/en not_active Expired - Fee Related
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