CN204989912U - Distributing type multichannel vibration synchronizing data collection system - Google Patents

Abstract

The utility model relates to a distributing type multichannel vibration synchronizing data collection system belongs to civil engineering field, is applied to structure safety and health monitoring trade. It includes input interface, amplifier, low pass filter, adc, table tennis buffer memory, FPGA controller, synchronized clock interface, treater, system reset module, power management module, RTC real -time clock, EEPROM, gigabit ethernet, flash memory, SDcard, SRAM, the input interface is connected with the amplifier, and the amplifier is connected with low pass filter, and low pass filter is connected with adc, adc is connected with the FPGA controller, and the FPGA controller has the synchronized clock interface, the FPGA controller is connected with the treater, the treater is connected with RTC real -time clock, EEPROM, gigabit ethernet, flash memory, SDcard, SRAM respectively, the table tennis buffer memory is connected with the FPGA controller, the system reset module is connected with FPGA controller, treater.

Description

A kind of distributed multi-channel Vibration Synchronization data collector

Technical field

The utility model relates to a kind of distributed multi-channel Vibration Synchronization data collector, belongs to field of civil engineering, is applied to structural safety health monitoring industry.

Background technology

At present for the dynamic test of measuring large bridge, need to use hyperchannel Vibration Synchronization data acquisition system (DAS), when number of channels is greater than the number of channels of single device, consider to adopt the mode of multiple devices cascade to realize with regard to needing, but current techniques although to achieve single device synchronously interchannel, but be difficult to realize the synchronous of every platform equipment room, thus can phase differential be produced, error is produced to final data analysis and bridge characteristic evaluation.

Summary of the invention

In order to overcome above-mentioned defect, the utility model object is to provide a kind of distributed multi-channel Vibration Synchronization data collector, belongs to field of civil engineering, is applied to structural safety health monitoring industry.

To achieve these goals, the utility model adopts following technical scheme:

A kind of distributed multi-channel Vibration Synchronization data collector, it comprises input interface, amplifier, low-pass filter, analog to digital converter, ping-pong buffer, FPGA controller, synchronous clock interface, processor, system reset module, power management module, RTC real-time clock, EEPROM, gigabit Ethernet, flash storage, SDcard, SRAM;

Input interface is connected with amplifier, and amplifier is connected with low-pass filter, and low-pass filter is connected with analog to digital converter;

Analog to digital converter is connected with FPGA controller, and FPGA controller has synchronous clock interface;

FPGA controller is connected with processor; Processor is connected with RTC real-time clock, EEPROM, gigabit Ethernet, flash storage, SDcard, SRAM respectively;

Ping-pong buffer is connected with FPGA controller;

System reset module is connected with FPGA controller, processor.

Processor is Cortex-A8 processor.

The frequency of operation of synchronous clock configures to FPGA controller by processor, and FPGA controller is produced synchronizing clock signals and sent to synchronous clock from machine by synchronous clock interface.

PGA controller produces synchronous clock by the configuration of Cortex-A8 processor;

Synchronizing clock signals sends to from machine by synchronous clock interface by FPGA controller;

After signal becomes digital signal by analog to digital converter, by FPGA controller by data stored in ping-pong buffer;

From machine by synchronous clock interface synchronous clock, under making it be operated in the frequency of synchronous clock, and by the synchronous clock interface of oneself, synchronous clock is sent to next stage equipment;

Processor reads configuration information by EEPROM and configures to FPGA controller.

The utility model realizes principle: native system realize multiple devices see the principle of synchronous acquisition be by configuration multiple devices wherein one other equipment be from machine for main frame, and main equipment by transmission synchronous clock to the synchronous acquisition realizing multiple devices from machine.Wherein, synchronous clock carries out long-distance transmissions by the network twisted-pair cable of RJ45 or optical fiber.The effect of synchronous clock is exactly, under making all devices of consolidated network be operated in same timeticks, realize zero phase difference.The data of multiple devices are gathered by on-the-spot router and send to on-the-spot PC to carry out man-machine interactive operation.

Acquisition Instrument inside adopts FPGA as logic controller, for controlling analog to digital conversion sampling and providing sampling clock, and controls ping-pong buffer, ensures the continuity of data.Power management module is used for distribute digital, analog power, ensures that system power good runs and does not interfere with each other.System microcontroller uses the processor of Cortex-A8 kernel, for realizing the function such as this locality storage, communication, clock, initialization of data.

The beneficial effects of the utility model:

The utility model patent solve traditional data acquisition system when multiple devices carry out data acquisition cannot the problem of true synchronization, the measurement for works ensure that reliable data syn-chronization.

Accompanying drawing explanation

Fig. 1 is structural schematic block diagram of the present utility model;

Fig. 2 is the utility model multiple devices connected mode schematic diagram;

In Fig. 2: 21-human-computer interaction interface; 22-router; 23 main equipments; (24,25,26)-from equipment; 27-synchronous clock input end; 28 synchronous clock output terminals;

Fig. 3 is the utility model many actual field connected mode schematic diagram.

In Fig. 3: 31-PC machine; 32-router II; 33-main equipment II; (34,35)-optic fiber converter; 36-is from equipment II.

Embodiment

Be described in detail below in conjunction with accompanying drawing 1,2,3 pairs of the utility model:

A kind of distributed multi-channel Vibration Synchronization data collector, it comprises input interface 1, amplifier 2, low-pass filter 3, analog to digital converter 4, ping-pong buffer 5, FPGA controller 6, synchronous clock interface 7, processor 8, system reset module 9, power management module 10, RTC real-time clock 11, EEPROM12, gigabit Ethernet 13, flash storage 14, SDcard15, SRAM16;

Input interface 1 is connected with amplifier 2, and amplifier 2 is connected with low-pass filter 3, and low-pass filter 3 is connected with analog to digital converter 4;

Analog to digital converter 4 is connected with FPGA controller 6, and FPGA controller 6 has synchronous clock interface 7;

FPGA controller 6 is connected with processor 8; Processor is connected with RTC real-time clock 11, EEPROM12, gigabit Ethernet 13, flash storage 14, SDcard15, SRAM16 respectively;

Ping-pong buffer 5 is connected with FPGA controller 6;

System reset module 9 is connected with FPGA controller 6, processor 8.

Processor 8 is Cortex-A8 processor.

Fig. 2 is the utility model multiple devices connected mode schematic diagram;

Fig. 3 is the utility model many actual field connected mode schematic diagram.

The signal input of each passage adopts independently signal transacting link, comprises amplification, filtering, sampling; FPGA carries out logic control to analog to digital converter, for controlling the sampling rate, transmission mode etc. of analog to digital converter in inside; FPGA controller carries out buffered to the synchronous real time data that sampling comes simultaneously, external memory storage is carried out the continuity operation of data as a ping-pong buffer; Be transferred to Cortex-A8 processor by inner digital filtering again after data buffer storage completes, Cortex-A8 processor carries out packing to data according to agreement and processes and send.

The generation of synchronous clock is completed by FPGA controller, and by the output frequency of Cortex-A8 processor configuration synchronization clock, FPGA produces high-precision synchronous clock by inner clock module; Simultaneously when equipment is as during from machine, the reception noctivagation FPGA controller of synchronous clock realizes.Cascade such as Fig. 2 of multiple devices shows, realizes the synchronous clock transmission of formula hand in hand.

Claims (2)

1. a distributed multi-channel Vibration Synchronization data collector, is characterized in that: it comprises input interface (1), amplifier (2), low-pass filter (3), analog to digital converter (4), ping-pong buffer (5), FPGA controller (6), synchronous clock interface (7), processor (8), system reset module (9), power management module (10), RTC real-time clock (11), EEPROM(12), gigabit Ethernet (13), flash storage (14), SDcard(15), SRAM(16);

Input interface (1) is connected with amplifier (2), and amplifier (2) is connected with low-pass filter (3), and low-pass filter (3) is connected with analog to digital converter (4);

Analog to digital converter (4) is connected with FPGA controller (6), and FPGA controller (6) has synchronous clock interface (7);

FPGA controller (6) is connected with processor (8); Processor respectively with RTC real-time clock (11), EEPROM(12), gigabit Ethernet (13), flash storage (14), SDcard(15), SRAM(16) be connected;

Ping-pong buffer (5) is connected with FPGA controller (6);

System reset module (9) is connected with FPGA controller (6), processor (8).

2. distributed multi-channel Vibration Synchronization data collector according to claim 1, is characterized in that: processor (8) is Cortex-A8 processor.