CN204885153U - Integrated circuit packaging body - Google Patents
Integrated circuit packaging body Download PDFInfo
- Publication number
- CN204885153U CN204885153U CN201520672715.1U CN201520672715U CN204885153U CN 204885153 U CN204885153 U CN 204885153U CN 201520672715 U CN201520672715 U CN 201520672715U CN 204885153 U CN204885153 U CN 204885153U
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- CN
- China
- Prior art keywords
- grounding pin
- integrated circuit
- chip
- conductive projection
- circuit package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Abstract
The utility model relates to an integrated circuit packaging body. According to the utility model discloses an integrated circuit packaging body of embodiment, it includes: the chip, chip holder is through the configuration with the hosting core piece, the signal pin, set up in chip holder peripheral and through the configuration with chip electric connection, the ground connection pin sets up in chip holder is peripheral and through disposing with ground connection, an at least conductive projection sets up in order to be connected with ground connection pin electricity above the ground connection pin, insulating housing, it shields chip, chip holder, signal pin and ground connection pin to expose on making an at least conductive projection, the shielding metal layer, it covers in insulating housing's top and lateral wall and at least conductive projection upper end to be connected with at least conductive projection electricity. According to the utility model discloses the integrated circuit packaging body and method for forming same can be simplified manufacturing process, reduce manufacturing cost.
Description
Technical field
The utility model relates to a kind of integrated circuit package body.
Background technology
Because increasing radio communication device is highly integrateable in the mobile phone of a limited areal, make originally comparatively to carry no weight and the radio frequency component adopting the lead frame of low cost to process as radio-frequency power amplifier (RFPowerAmplifier, RFPA) interference of electromagnetic field problem that, low noise amplifier (LowNoiseAmplifier, LNA), duplexer (AntennaSwitch) etc. face also gets more and more.
Be in the patent application of CN102479767A at publication number, signal pad (SignalPad) and ground cushion (GNDPad) separate by the lead frame utilizing the height first designed to configure.In this technology, signal pins is concordant with the outer rim of lead frame, and grounding pin is recessed in the outer rim of lead frame.In order to the shielded metal layer enabling to be positioned at chip periphery to be electrically connected with grounding pin formed electromagnetic-field-shielded, need when making grounding pin, grounding pin to be made higher than signal pins, after utilizing hemisection (half-cut) the mode grounding pin (GND pin) switched to higher than signal pins to expose, namely cutting is stopped, complete metal coating afterwards, so complete electromagnetic-field-shielded.
In the patent application of CN102479767A, the lead frame that height pin configuration is good needs special dies customization to form, and makes its cost of manufacture higher.
Therefore, existing have integrated circuit package body of electromagnetic-field-shielded function and preparation method thereof and still need further improvement.
Utility model content
One of the purpose of this utility model is the method providing integrated circuit package body and form this integrated circuit package body, can obtain the integrated circuit package body with electromagnetic-field-shielded function with simple technique.
An embodiment of the present utility model provides an integrated circuit package body, and it comprises: chip; Chip carrier, is configured to carry this chip; Signal pins, is arranged at this chip carrier periphery and is configured to connect with this chip electrical; Grounding pin, is arranged at this chip carrier periphery and is configured to ground connection; At least one conductive projection, is arranged at above this grounding pin to be electrically connected with this grounding pin; Insulation shell, it covers this chip, this chip carrier, this signal pins and this grounding pin, and this at least one conductive projection upper end is exposed; Shielded metal layer, it covers the top of this insulation shell and sidewall and this at least one conductive projection upper end, to be electrically connected with this at least one conductive projection.
The method that still another embodiment provides a formation integrated circuit package body of the present utility model, it comprises: be fixed on by chip on chip carrier; This chip and the signal pins being positioned at this chip carrier periphery is connected with lead-in wire; At least one conductive projection be electrically connected with this grounding pin is formed above the grounding pin being positioned at this chip carrier periphery; Injection moulding and form insulation shell, this insulation shell covers this chip, this chip carrier, this signal pins, this lead-in wire, this grounding pin and this at least one conductive projection between this chip and this signal pins; Just slot until this at least one conductive projection upper end is exposed from top to bottom to above this at least one conductive projection in this insulation shell; And above this insulation shell and the sidewall of this groove and bottom cover shielded metal layer, this shielded metal layer is electrically connected with this at least one conductive projection.
According to the integrated circuit package body of the utility model embodiment and the method for formation integrated circuit package body, the conductive projection be electrically connected with grounding pin is formed above grounding pin, and the upper end making metal screen layer cover conductive projection forms electrical connection, thus reach the object of shield electromagnetic interference.Therefore, do not need to need to adopt certain moduli tool to customize the lead frame of height pin configuration as prior art.Accordingly, it is simple that the utility model has manufacturing process, the advantage of low cost of manufacture.
Accompanying drawing explanation
Fig. 1 is the longitudinal cross-section schematic diagram of the integrated circuit package body according to the utility model embodiment.
Fig. 2 is the transverse sectional view of the integrated circuit package body in Fig. 1.
Fig. 3 is the transverse sectional view of the integrated circuit package body according to another embodiment of the utility model.
Fig. 4 is the flow chart of the method for formation integrated circuit package body according to the utility model embodiment.
Fig. 5 A-Fig. 5 F is the illustrative diagram adopting the method for Fig. 4 to make the process of integrated circuit package body.
Embodiment
Fig. 1 is the longitudinal cross-section schematic diagram of the integrated circuit package body 100 according to the utility model embodiment.Fig. 2 is the transverse sectional view of the integrated circuit package body 100 in Fig. 1.
As shown in Figure 1 and Figure 2, chip 101, chip carrier 102, signal pins 207, grounding pin 103, insulation shell 104, shielded metal layer 105 and at least one conductive projection 108 is comprised according to the integrated circuit package body 100 of the utility model embodiment.Chip carrier 102 is configured to carry this chip 101.Signal pins 207 is arranged at chip carrier 102 periphery and is configured to be electrically connected with chip 101.Grounding pin 103 is arranged at chip carrier 102 periphery and is configured to ground connection.In the present embodiment, signal pins 207 does not inside contract relative to grounding pin 103.Conductive projection 108 is arranged at above grounding pin 103 to be electrically connected with grounding pin 103.Insulation shell 104 covers chip 101, chip carrier 102, signal pins 207 and grounding pin 103, and conductive projection 108 upper end is exposed.Shielded metal layer 105 covers above insulation shell 104 and sidewall and conductive projection 108 upper end, to be electrically connected with conductive projection 108.Owing to forming the conductive projection 108 be electrically connected with grounding pin 103 above grounding pin 103, and the upper end making metal screen layer 105 cover conductive projection 108 forms electrical connection, thus can reach the object of shield electromagnetic interference.Therefore, do not need to need to adopt certain moduli tool to customize the lead frame of height pin configuration as prior art.Accordingly, it is simple that the utility model has manufacturing process, the advantage of low cost of manufacture.
As shown in Figure 1, in the present embodiment, conductive projection 108 can be the Metal Ball of soldered ball or other kind.
In the present embodiment, the number arranging the grounding pin 103 of chip carrier 102 periphery is relevant with the frequency of chip 101.The frequency of chip 101 is higher, the grounding pin more than 103 of needs.Grounding pin 103 can comprise the grounding pin 103 at the end angle place being positioned at integrated circuit package body 100.End angle place grounding pin 103 can be configured to by go between 107 or connecting portion 109 be electrically connected with chip carrier 102.Grounding pin 103 can also comprise at least one grounding pin 103 between the abutting end angle of integrated circuit package body 100.As shown in Figure 2, the grounding pin 103 between the abutting end angle of integrated circuit package body 100 is configured to 107 to be electrically connected with chip carrier 102 by going between, or is connected by the grounding pin 103 of lead-in wire 107 with this end angle place.As shown in Figure 2, in the present embodiment, grounding pin 103 alternately can be arranged with signal pins 207.
Fig. 3 is the transverse sectional view of the integrated circuit package body according to another embodiment of the utility model.In the embodiment shown in fig. 3, except signal pins 207 inside contracts relative to grounding pin 103, the structure of integrated circuit package body is identical with the embodiment shown in Fig. 1, Fig. 2.In the embodiment shown in fig. 3, signal pins 207 such as inside contracts 50 μm relative to grounding pin 103,100 μm, or 150 μm, but be not limited thereto.
Fig. 4 is the flow chart of the method for formation integrated circuit package body 100 according to the utility model embodiment, and it can form the integrated circuit package body 100 in Fig. 1,2 illustrated embodiments.Fig. 5 A-Fig. 5 F is the illustrative diagram adopting the method for Fig. 4 to make the process of integrated circuit package body 100.
Embodiment according to Fig. 4, in step S301, as shown in Figure 5A, lead frame bar to be packaged is provided with the lead frame unit of some arrayed, and wherein the grounding pin 103 of each lead frame unit interconnects.For each lead frame unit, chip 101 is fixed on chip carrier 102.In step s 302, chip 101 and signal pins 207 is connected with lead-in wire 107.In step S303, as shown in Figure 5 B, above the grounding pin 103 being positioned at chip carrier 102 periphery, form the conductive projection 108 be electrically connected with grounding pin 103.For example use wire bonder to be formed and be used as the soldered ball of conductive projection 108 or the Metal Ball of other kinds.As shown in Figure 2, signal pins 207 inside contracts relative to grounding pin 103.In step s 304, as shown in Figure 5 C, injection moulding and form insulation shell 104, insulation shell 104 covers chip 101, chip carrier 102, signal pins 207, lead-in wire 107, grounding pin 103 and conductive projection 108 between chip 101 and signal pins 207.In step S305, as shown in Figure 5 D, in insulation shell 104 just to slotting 410 above conductive projection 108 from top to bottom until conductive projection 108 upper end is exposed.In step S306, as shown in fig. 5e, above insulation shell 101 and the sidewall of the groove 410 opened and bottom cover shielded metal layer 105, shielded metal layer 105 is electrically connected with conductive projection 108.Shielded metal layer 105 is formed such as but not limited to by sputter.As illustrated in figure 5f, the multiple integrated circuit package bodies 100 connected together are split, obtain the integrated circuit package body 100 of multiple separation.Owing to forming the conductive projection 108 be electrically connected with grounding pin 103 above grounding pin 103, and the upper end making metal screen layer 105 cover conductive projection 108 forms electrical connection, thus can reach the object of shield electromagnetic interference.Therefore, do not need to need to adopt certain moduli tool to customize the lead frame of height pin configuration as prior art.Accordingly, it is simple that the utility model has manufacturing process, the advantage of low cost of manufacture.
Technology contents of the present utility model and technical characterstic disclose as above, but those of ordinary skill in the art still may do all replacement and the modification that do not deviate from the utility model spirit based on teaching of the present utility model and announcement.Therefore, protection range of the present utility model should be not limited to the content that embodiment discloses, and should comprise various do not deviate from replacement of the present utility model and modification, and is contained by present patent application claims.
Claims (4)
1. an integrated circuit package body, it comprises:
Chip;
Chip carrier, is configured to carry described chip;
Signal pins, is arranged at described chip carrier periphery and is configured to connect with described chip electrical;
Grounding pin, is arranged at described chip carrier periphery and is configured to ground connection;
At least one conductive projection, is arranged at above described grounding pin to be electrically connected with described grounding pin;
Insulation shell, it covers described chip, described chip carrier, described signal pins and described grounding pin, and described at least one conductive projection upper end is exposed;
Shielded metal layer, it covers the top of described insulation shell and sidewall and described at least one conductive projection upper end, to be electrically connected with described at least one conductive projection.
2. integrated circuit package body according to claim 1, wherein said at least one conductive projection is the Metal Ball of soldered ball or other kind.
3. integrated circuit package body according to claim 1, comprise the grounding pin at the end angle place being positioned at described integrated circuit package body in the middle of wherein said grounding pin, the grounding pin at described end angle place is configured to be electrically connected with described chip carrier by lead-in wire or connecting portion.
4. integrated circuit package body according to claim 3, also comprise at least one grounding pin between the abutting end angle of described integrated circuit package body in the middle of wherein said grounding pin, the grounding pin between described abutting end angle is configured to be electrically connected by the grounding pin at lead-in wire and described end angle place or described chip carrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520672715.1U CN204885153U (en) | 2015-09-01 | 2015-09-01 | Integrated circuit packaging body |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520672715.1U CN204885153U (en) | 2015-09-01 | 2015-09-01 | Integrated circuit packaging body |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204885153U true CN204885153U (en) | 2015-12-16 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520672715.1U Active CN204885153U (en) | 2015-09-01 | 2015-09-01 | Integrated circuit packaging body |
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| CN (1) | CN204885153U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070710A (en) * | 2015-09-01 | 2015-11-18 | 苏州日月新半导体有限公司 | Integrated circuit packaging body and formation method thereof |
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2015
- 2015-09-01 CN CN201520672715.1U patent/CN204885153U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105070710A (en) * | 2015-09-01 | 2015-11-18 | 苏州日月新半导体有限公司 | Integrated circuit packaging body and formation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 215101 No. 188, Suhong West Road, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee after: Riyuexin semiconductor (Suzhou) Co.,Ltd. Address before: 215026 No.188 Suhong West Road, Suzhou Industrial Park, Suzhou City, Jiangsu Province Patentee before: SUZHOU ASEN SEMICONDUCTORS Co.,Ltd. |
|
| CP03 | Change of name, title or address |