CN204858966U - Voltage converting circuit - Google Patents
Voltage converting circuit Download PDFInfo
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- CN204858966U CN204858966U CN201520642327.9U CN201520642327U CN204858966U CN 204858966 U CN204858966 U CN 204858966U CN 201520642327 U CN201520642327 U CN 201520642327U CN 204858966 U CN204858966 U CN 204858966U
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Abstract
The utility model discloses a voltage converting circuit, include: the first -order charge pump, including input, output, forward clock control end and reverse clock control end, the first -order charge pump is used for forming output voltage and following under forward clock control end and the reverse clock control end clock signal's that provides control output is for load provide voltage, burden feedback loop, including power end, voltage feedback end and feedback output, voltage feedback end with the output of first -order charge pump links to each other, is used for the basis the output voltage adjustment the source voltage of power end input to form feedback voltage, follow the feedback output exports to the input of first -order charge pump. The embodiment of the utility model provides a through the input voltage of burden feedback loop control first -order charge pump and clock signal's amplitude, transmit the output with the input voltage of first -order charge pump to form stable output voltage.
Description
Technical field
The utility model embodiment relates to circuit engineering, particularly relates to a kind of voltage conversion circuit.
Background technology
Voltage conversion circuit is used to the voltage of signal to be transformed into another analog voltage range from an analog voltage range.
But prior art there will be the problem of spread of voltage, need to solve.
Utility model content
The utility model provides a kind of voltage conversion circuit, with the target voltage of stable output.
The utility model embodiment provides a kind of voltage conversion circuit, comprise: single order charge pump, comprise input, output, forward clock control end and reverse clock control end, described single order charge pump be used for forward clock control end and reverse clock control end the control of clock signal is provided under, form output voltage to export from described output, for load provides voltage; Feedback loop, comprise power end, pressure feedback port and feedback output end, described pressure feedback port is connected with described single order electric charge delivery side of pump, for adjusting the source voltage of described power end input according to described output voltage, to form feedback voltage, export the input of described single order charge pump to from described feedback output end.
Described voltage conversion circuit also comprises clock-signal generator, and the input of described clock-signal generator is connected with the output of an oscillator, and output is connected with the clock control end of described single order charge pump, for adjusting the amplitude of clock signal.
Described single order charge pump comprises: a N NMOS N-channel MOS N type field effect transistor NMOS, the first P-channel metal-oxide-semiconductor type field effect transistor PMOS, the second PMOS, the 3rd PMOS, the first electric capacity and the second electric capacity.Wherein, the drain electrode of described first NMOS tube is the input of described single order charge pump, and grid is forward clock control end, and source electrode is connected with reverse clock control end by the first electric capacity, and is connected with the source electrode of described first PMOS; The grid of described first PMOS is connected with forward clock control end by the second electric capacity, drains as described single order electric charge delivery side of pump; The grid of described second PMOS is connected with the grid of source electrode with described first PMOS, and drain electrode is connected with described single order electric charge delivery side of pump; The grid of described 3rd PMOS is connected with described single order electric charge delivery side of pump with drain electrode, and source electrode is connected with the grid of described first PMOS.
Described feedback loop comprises the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 4th PMOS, the 5th PMOS, the 6th PMOS and the 3rd resistance.Wherein, the grid of described second NMOS tube is the pressure feedback port of feedback loop, is connected with described single order electric charge delivery side of pump by the first resistance, and by the second grounding through resistance, drain electrode is connected with the drain and gate of described 5th PMOS respectively; The source electrode of described 5th PMOS is connected with power end; Described 6th PMOS becomes mirror image to be connected with described 5th PMOS with described second NMOS tube with described 3rd NMOS tube respectively; The source electrode of described 4th PMOS is connected with power end, and grid is connected with the drain electrode of described 3rd NMOS tube, drains as the feedback output end of feedback loop, by the 3rd grounding through resistance; The drain electrode of described 4th NMOS tube is connected with described second NMOS tube source electrode with the source electrode of described 3rd NMOS tube respectively, source ground.
Described clock-signal generator comprises the first inverter, the second inverter, the 3rd inverter, the 4th inverter and the 5th inverter.Wherein said first inverter, the second inverter and the 3rd inverter are sequentially connected in series; In parallel with described first inverter, the second inverter and the 3rd inverter after described 4th inverter and the 5th inverter series.
The voltage conversion circuit that the utility model embodiment provides, controls the input voltage of single order charge pump and the amplitude of clock signal by feedback loop, the input terminal voltage of single order charge pump is delivered to output, thus forms stable output voltage.
Accompanying drawing explanation
Fig. 1 is a kind of voltage conversion circuit figure that the utility model embodiment one provides;
Fig. 2 is the circuit diagram of the clock-signal generator that the utility model embodiment two provides;
Fig. 3 is the waveform of clock control signal CLKB and CLK that the utility model embodiment two provides and the voltage waveform at corresponding net1 and VDDP place.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.Be understandable that, specific embodiment described herein only for explaining the utility model, but not to restriction of the present utility model.It also should be noted that, for convenience of description, illustrate only the part relevant to the utility model in accompanying drawing but not entire infrastructure.
Embodiment one
A kind of voltage conversion circuit figure that Fig. 1 provides for the utility model embodiment one, the present embodiment is applicable to the situation of the supply power voltage that load needs excursion narrow.A kind of voltage conversion circuit figure that the present embodiment provides, as shown in Figure 1, comprising: single order charge pump 110 and feedback loop 120.
Single order charge pump 110 comprises input, output, forward clock control end (CLKB) and reverse clock control end (CLK), described single order charge pump be used for forward clock control end and reverse clock control end the control of clock signal is provided under, form output voltage to export from described output, for load provides voltage.
Feedback loop 120 comprises power end, pressure feedback port and feedback output end, described pressure feedback port is connected with described single order electric charge delivery side of pump, for adjusting the source voltage of described power end input according to described output voltage, to form feedback voltage, export the input of described single order charge pump to from described feedback output end.
The technical scheme of the present embodiment, by clock signal and feedback loop, carries out reverse feedback by the change of basic voltage, makes output voltage stabilization like this near basic voltage.
Particular circuit configurations as shown in Figure 1 can be adopted for realizing above-mentioned functions.
Described single order charge pump 110 comprises: N NMOS N-channel MOS N type field effect transistor (NMOS) N1, first P-channel metal-oxide-semiconductor type field effect transistor (PMOS) P1, second PMOS P2, the 3rd PMOS P3, the first electric capacity C1 and the second electric capacity C2;
Wherein, the drain electrode of described first NMOS tube is the input of described single order charge pump, and grid is forward clock control end, and source electrode is connected with reverse clock control end by the first electric capacity, and is connected with the source electrode of described first PMOS; The grid of described first PMOS is connected with forward clock control end by the second electric capacity, drains as described single order electric charge delivery side of pump; The grid of described second PMOS is connected with the grid of source electrode with described first PMOS, and drain electrode is connected with described single order electric charge delivery side of pump; The grid of described 3rd PMOS is connected with described single order electric charge delivery side of pump with drain electrode, and source electrode is connected with the grid of described first PMOS.
Described feedback loop 120 comprises the second NMOS tube N2, the 3rd NMOS tube N3, the 4th NMOS tube N4, the 4th PMOS P4, the 5th PMOS P5, the 6th PMOS P6 and the 3rd resistance R3;
Wherein, the grid of described second NMOS tube is the pressure feedback port (REGLEVEL) of feedback loop, be connected with described single order electric charge delivery side of pump by the first resistance (R1), and by the second resistance (R2) ground connection, drain electrode is connected with the drain and gate of described 5th PMOS respectively; The source electrode of described 5th PMOS is connected with power end; Described 6th PMOS becomes mirror image to be connected with described 5th PMOS with described second NMOS tube with described 3rd NMOS tube respectively; The source electrode of described 4th PMOS is connected with power end, and grid is connected with the drain electrode of described 3rd NMOS tube, drains as the feedback output end of feedback loop, by the 3rd grounding through resistance; The drain electrode of described 4th NMOS tube is connected with described second NMOS tube source electrode with the source electrode of described 3rd NMOS tube respectively, source ground.
Wherein, VDDP is the output voltage of described single order charge pump, is also target voltage, can sets according to actual needs, and as shown in Figure 1, VDDP=VREF* (R1+R2)/R2, can regulate VDDP by regulating VREF, R1 or R2.In order to more clearly describe the operation principle of described feedback loop, suppose that output voltage VDDP is lower than target voltage, as shown in Figure 1, the voltage of REGLEVEL reduces, the ducting capacity of N2 weakens, net3 voltage raises, the ducting capacity that net3 voltage raises P6 declines, N3 ducting capacity increases, and (N4 that BIAS controls can regard current source as, the current value flowing through it is constant, equal to flow through the electric current of N2 and N3 and constant, the electric current of N2 is little, N3 is naturally just large), then net4 voltage drop (N3 is greater than to the ability that net4 extracts electric charge the ability that P6 provides electric charge), net4 voltage drop, the ducting capacity of P4 increases, VC voltage raises.When VC voltage raises, single order charge pump under forward clock control end and reverse clock control end institute provide the control of clock signal, the ability of single order charge pump enhancing, thus VDDP voltage is lifted, thus VDDP is tended towards stability.The specific works process of single order charge pump is as follows: VC voltage raises, when the amplitude of clock control signal CLK drops to 0 from VC, the voltage drop of net1 VC, but now the amplitude of clock control signal CLKB is VC, N1 conducting, charged until net1=VC to net1 by N1, net2 voltage has been lifted the closedown of VC (because under electric capacity C2, step has been lifted VC by CLKB from 0 to VC) P1 pipe simultaneously; When the amplitude of clock control signal CLKB drops to 0 from VC, N1 pipe is closed, the voltage of net1 has been lifted VC by electric capacity C1 through CLK, now net1=VC+VC, simultaneously net2 voltage drop VC, P1 pipe is opened, electric charge is delivered to VDDP from net1, VDDP voltage obtains lifting, and as said process constantly circulates, the waveform of clock control signal CLKB and CLK and the voltage waveform at net1 and VDDP place are as shown in Figure 3.VC voltage is higher, and net1 is lifted higher, and electric capacity C1 stores more electric charges, stronger to VDDP power supply capacity, finally makes VDDP tend towards stability.When VDDP equals target voltage, REGLEVEL=VDDP, flows through P5, and the electric current of N2, N3 and P6 is all equal, net3 and net4 voltage does not all change, and maintains a balance.When VDDP is just in time contrary lower than course of work during target voltage with VDDP higher than course of work during target voltage.Owing to employing single order charge pump, so the VDD that the numerical value of VDDP is less than 2 times, VDD are external voltage source, VDDP is the narrower voltage of an excursion.
It should be noted that supply power voltage VDD in feedback loop, reference voltage VREF and BIAS does not have specific requirement, does not limit it herein, can choose suitable numerical value according to actual needs.The effect of P2 and the P3 pipe in single order charge pump is that voltage in order to ensure net2 place can the break-make of control P1 pipe.
The technical scheme of the present embodiment, controls the input voltage of single order charge pump and the amplitude of clock signal by feedback loop, feedback voltage is delivered to output, thus forms stable output voltage and be supplied to load.
Embodiment two
On the basis of above-described embodiment, Fig. 2 is the circuit diagram of the clock-signal generator that the utility model embodiment two provides, as shown in Figure 2, the input of described clock-signal generator is connected with the output of an oscillator, output is connected with the clock control end of described single order charge pump, for adjusting the amplitude of clock signal.
Described clock signal treatment circuit comprises the first inverter T1, the second inverter T2, the 3rd inverter T3, the 4th inverter T4 and the 5th inverter T5; Wherein said first inverter, the second inverter and the 3rd inverter are sequentially connected in series; In parallel with described first inverter, the second inverter and the 3rd inverter after described 4th inverter and the 5th inverter series.
The amplitude of clock signal is finally determined by the supply power voltage VC of T3 and T5, and as shown in Figure 2, output exports clock signal clk B and CLK with oscillator same frequency.
It should be noted that the type of described oscillator is not construed as limiting herein, can be crystal oscillator, frequency of oscillation be chosen according to practical application, such as, can be 100M.
In the technical scheme of the present embodiment, by the supply power voltage of inverter T3 and T5 being connected to the feedback output end VC of feedback loop, the amplitude of clock signal clk B and CLK is made to be VC, by controlling the amplitude of clock signal clk B and CLK, control the output of single order charge pump, finally obtain stable output voltage.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Skilled person in the art will appreciate that the utility model is not limited to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and protection range of the present utility model can not be departed from.Therefore, although be described in further detail the utility model by above embodiment, but the utility model is not limited only to above embodiment, when not departing from the utility model design, can also comprise other Equivalent embodiments more, and scope of the present utility model is determined by appended right.
Claims (5)
1. a voltage conversion circuit, is characterized in that, comprising:
Single order charge pump, comprise input, output, forward clock control end and reverse clock control end, described single order charge pump be used for forward clock control end and reverse clock control end the control of clock signal is provided under, form output voltage to export from described output, for load provides voltage;
Feedback loop, comprise power end, pressure feedback port and feedback output end, described pressure feedback port is connected with described single order electric charge delivery side of pump, for adjusting the source voltage of described power end input according to described output voltage, to form feedback voltage, export the input of described single order charge pump to from described feedback output end.
2. circuit according to claim 1, it is characterized in that, also comprise clock-signal generator, the input of described clock-signal generator is connected with the output of an oscillator, output is connected with the clock control end of described single order charge pump, for adjusting the amplitude of clock signal.
3. circuit according to claim 1, is characterized in that, described single order charge pump comprises: a N NMOS N-channel MOS N type field effect transistor NMOS, first P-channel metal-oxide-semiconductor type field effect transistor PMOS, second PMOS, the 3rd PMOS, the first electric capacity and the second electric capacity;
Wherein, the drain electrode of described first NMOS tube is the input of described single order charge pump, and grid is forward clock control end, and source electrode is connected with reverse clock control end by the first electric capacity, and is connected with the source electrode of described first PMOS;
The grid of described first PMOS is connected with forward clock control end by the second electric capacity, drains as described single order electric charge delivery side of pump;
The grid of described second PMOS is connected with the grid of source electrode with described first PMOS, and drain electrode is connected with described single order electric charge delivery side of pump;
The grid of described 3rd PMOS is connected with described single order electric charge delivery side of pump with drain electrode, and source electrode is connected with the grid of described first PMOS.
4. circuit according to claim 1, is characterized in that, described feedback loop comprises the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the 4th PMOS, the 5th PMOS, the 6th PMOS and the 3rd resistance;
Wherein, the grid of described second NMOS tube is the pressure feedback port of feedback loop, is connected with described single order electric charge delivery side of pump by the first resistance, and by the second grounding through resistance, drain electrode is connected with the drain and gate of described 5th PMOS respectively;
The source electrode of described 5th PMOS is connected with power end;
Described 6th PMOS becomes mirror image to be connected with described 5th PMOS with described second NMOS tube with described 3rd NMOS tube respectively;
The source electrode of described 4th PMOS is connected with power end, and grid is connected with the drain electrode of described 3rd NMOS tube, drains as the feedback output end of feedback loop, by the 3rd grounding through resistance;
The drain electrode of described 4th NMOS tube is connected with described second NMOS tube source electrode with the source electrode of described 3rd NMOS tube respectively, source ground.
5. circuit according to claim 1, is characterized in that, described clock-signal generator comprises
First inverter, the second inverter, the 3rd inverter, the 4th inverter and the 5th inverter;
Wherein said first inverter, the second inverter and the 3rd inverter are sequentially connected in series; In parallel with described first inverter, the second inverter and the 3rd inverter after described 4th inverter and the 5th inverter series.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520642327.9U CN204858966U (en) | 2015-08-24 | 2015-08-24 | Voltage converting circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520642327.9U CN204858966U (en) | 2015-08-24 | 2015-08-24 | Voltage converting circuit |
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| CN204858966U true CN204858966U (en) | 2015-12-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105048801A (en) * | 2015-08-24 | 2015-11-11 | 北京兆易创新科技股份有限公司 | Voltage conversion circuit |
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- 2015-08-24 CN CN201520642327.9U patent/CN204858966U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105048801A (en) * | 2015-08-24 | 2015-11-11 | 北京兆易创新科技股份有限公司 | Voltage conversion circuit |
| CN105048801B (en) * | 2015-08-24 | 2018-04-17 | 北京兆易创新科技股份有限公司 | A kind of voltage conversion circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |
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| CP03 | Change of name, title or address |