CN204810246U

CN204810246U - Square signal amplifier circuit of anti - duty cycle

Info

Publication number: CN204810246U
Application number: CN201520422597.9U
Authority: CN
Inventors: 方镜清
Original assignee: ZHONGSHAN XINDA ELECTRONIC TECHNOLOGY Co Ltd
Current assignee: ZHONGSHAN XINDA ELECTRONIC TECHNOLOGY Co Ltd
Priority date: 2015-06-18
Filing date: 2015-06-18
Publication date: 2015-11-25
Anticipated expiration: 2025-06-18

Abstract

The utility model provides a square signal amplifier circuit of anti - duty cycle has input and output, its characterized in that: main system is become with the 2nd NMOS nest of tubes by a PMOS pipe, the 2nd PMOS pipe, NMOS pipe, PMOS pipe and NMOS pipe are established ties and are connect between first power end and ground end, and the grid of the grid of PMOS pipe and NMOS pipe is connected to jointly the input, PMOS pipe is connected to with the tie point of NMOS pipe the output, the grid of the 2nd PMOS pipe is connected the output, its source connection first power end, its drain electrode is connected to the grid of PMOS pipe, the 2nd NMOS union coupling in between the grid of an input and a PMOS pipe, NMOS pipe, the grid of the 2nd NMOS pipe is connected to the second source end. The utility model discloses circuit structure is simple, practical, only need the first power end of adjustment the magnitude of voltage alright easily obtain required voltage amplitude, make things convenient for the nimble square signal who is fit for the amplitude that acquires of electronic engineering teacher.

Description

A kind of square-wave signal amplifying circuit of anti-duty ratio

Technical field

The utility model relates to a kind of square-wave signal amplifying circuit of anti-duty ratio, and it is applied to microelectronic circuit design.

Background technology

Often can design in the middle of microelectronic circuit and chip circuit by cycle square wave as the control signal of circuit or drive singal; the most simply directly draw connection circuit clock signal; but the voltage magnitude that circuit clock signal is general is between 3.4V to 5V, this just more difficult realization to the control of subsequent conditioning circuit or driving.So, need to set up amplitude change-over circuit, voltage magnitude effective period of square wave is promoted to enough values, with the demand of satisfied control or driving.In addition, also consider that the drive singal duty ratio required by some circuit is contrary with clock signal, it is desirable to directly to realize the reverse of duty ratio while amplification, therefore have present patent application.

Utility model content

For solving problem mentioned in background technology, the utility model proposes a kind of square-wave signal amplifying circuit of anti-duty ratio, its concrete technical scheme is as follows:

A kind of square-wave signal amplifying circuit of anti-duty ratio, there is input and output, main system is made up of the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube, described first PMOS and the first NMOS tube be connected in series in the first power end and ground hold between, and the grid of the grid of the first PMOS and the first NMOS tube is connected to described input jointly, the tie point of the first PMOS and the first NMOS tube is connected to described output; The grid of described second PMOS connects described output, and its source electrode connects described first power end, and its drain electrode is connected to the grid of described first PMOS; Second NMOS tube is connected between the grid of described input and the first PMOS, the first NMOS tube, and the grid of described second NMOS tube is connected to second source end; Described first power end has the first direct voltage, and described second source end has the second direct voltage.

In the middle of one or more embodiment of the present utility model, the source electrode of described first PMOS connects described first power end, and its drain electrode connects the source electrode of described first NMOS tube, and the drain electrode of described first NMOS tube connects earth terminal.

In the middle of one or more embodiment of the present utility model, the desirable scope of described first direct voltage is+10V to+30V, and the desirable scope of described second direct voltage is+5V to+10V.

In the middle of one or more embodiment of the present utility model, described first direct voltage is+15V, and described second direct voltage is+5V.

Advantageous of the present utility model exists: exported by the signal that the square wave of low voltage amplitudes becomes to be enlarged into enough voltage magnitudes with anti-duty cycle conversion, meet the demand controlling or drive; Meanwhile, the utility model circuit structure is simple, practical, and the magnitude of voltage that only need adjust the first power end just can easily obtain required voltage amplitude, facilitates Electronics Engineer to obtain the square-wave signal of applicable amplitude flexibly.

Accompanying drawing explanation

Fig. 1 is the particular circuit configurations schematic diagram of the utility model.

Fig. 2 is that the utility model input contrasts schematic diagram with the signal of output.

Embodiment

Following 1-2 by reference to the accompanying drawings, is further described the application's scheme:

The source electrode of described first PMOS connects described first power end, and its drain electrode connects the source electrode of described first NMOS tube, and the drain electrode of described first NMOS tube connects earth terminal.

Concrete enforcement principle: (described input end input amplitude is the cycle square wave of+5V, and the first direct voltage is+15V, and described second direct voltage is+5V)

The grid of described second NMOS tube often connects+5V direct voltage, is in normally open, and the cycle square wave of+5V is directly by being connected to the grid of described first PMOS, the first NMOS tube;

When " 5V " of square wave arrives, described first PMOS T1 cut-off, the first NMOS tube T3 conducting, thus the voltage of output OUT is pulled low to 0V; The grid voltage of described second PMOS drags down, and makes its conducting, draws high the voltage of the first gate pmos, to ensure that it ends;

When " O " of square wave arrives, described first PMOS conducting, the first NMOS tube cut-off, thus order exports the voltage high of carbonyl OUT to+15V; The grid voltage of described 2nd PMO pipe is drawn high, and makes it end;

Described second NMOS tube utilizes PN junction electrical characteristic, and when making the second PMOS conducting ,+15V voltage can not regurgitate, plays the effect of isolation, protection square-wave signal source.

By aforesaid way, just can the amplifying with anti-duty ratio forward of right+5V periodic signal of square wave, produce+15V periodic signal of square wave, meet the driving voltage demand of subsequent conditioning circuit; In like manner, the magnitude of voltage of choose reasonable first power end, the signal that just can produce corresponding voltage amplitude exports, flexibly and convenient.

Above-mentioned preferred implementation should be considered as illustrating of the application's scheme implementation mode, allly to duplicate with the application's scheme, technology that is approximate or that make based on this is deduced, replaces, improvement etc., all should be considered as the protection range of this patent.

Claims

1. the square-wave signal amplifying circuit of an anti-duty ratio, there is input and output, it is characterized in that: main system is made up of the first PMOS, the second PMOS, the first NMOS tube and the second NMOS tube, described first PMOS and the first NMOS tube be connected in series in the first power end and ground hold between, and the grid of the grid of the first PMOS and the first NMOS tube is connected to described input jointly, the tie point of the first PMOS and the first NMOS tube is connected to described output; The grid of described second PMOS connects described output, and its source electrode connects described first power end, and its drain electrode is connected to the grid of described first PMOS; Second NMOS tube is connected between the grid of described input and the first PMOS, the first NMOS tube, and the grid of described second NMOS tube is connected to second source end; Described first power end has the first direct voltage, and described second source end has the second direct voltage.

2. the square-wave signal amplifying circuit of a kind of anti-duty ratio according to claim 1, it is characterized in that: the source electrode of described first PMOS connects described first power end, its drain electrode connects the source electrode of described first NMOS tube, and the drain electrode of described first NMOS tube connects earth terminal.

3. the square-wave signal amplifying circuit of a kind of anti-duty ratio according to claim 2, is characterized in that: the desirable scope of described first direct voltage is+10V to+30V, and the desirable scope of described second direct voltage is+5V to+10V.

4. the square-wave signal amplifying circuit of a kind of anti-duty ratio according to claim 3, it is characterized in that: described first direct voltage is+15V, described second direct voltage is+5V.