CN204794939U

CN204794939U - 60 second timer circuit

Info

Publication number: CN204794939U
Application number: CN201520517367.0U
Authority: CN
Inventors: 闵建亮
Original assignee: Jiangxi University of Technology
Current assignee: Jiangxi University of Technology
Priority date: 2015-07-17
Filing date: 2015-07-17
Publication date: 2015-11-18
Anticipated expiration: 2025-07-17

Abstract

The utility model discloses a 60 second timer circuit, its aim at provide a convenient operation, the accurate timer circuit of timing, and whole circuit comprises the three, and the branch maybe the counter part, the digital pipe display part of decoder subtotal, counter part mainly used sets up the initial time and carries out the subtraction and calculates, the decoder part is responsible for turning into the ten's digit with binary digital signal, and the drive charactron shows digitally, the charactron display part is used for showing the numeral, can show numerical value of a subpulse each.

Description

A kind of 60 seconds timer circuits

Technical field

The utility model relates to a kind of 60 seconds timer circuits, mainly plays the effect of timing, belongs to time intelligence control technology field.

Background technology

At present, timer has numerous in variety, multifarious.But lack more rare for the timer of timing in 60 seconds, and timing in 60 seconds is conventional timing mode, therefore provides a kind of 60 seconds timer circuits that are easy to operate, accurate timing to seem very necessary.

Summary of the invention

The technical problems to be solved in the utility model is to provide a kind of timer circuit of easy to operate, accurate timing.

For reaching above-mentioned purpose, a kind of 60 seconds timer circuits of the utility model, described circuit comprises counter portion, decoder part and numeral method part, and described counter portion comprises the decimal system reversible counter chip of a position cC74HC192 and decimal system reversible counter chip cC74HC192; Described decoder part comprises decoder cC4511 and decoder cC4511; Described numeral method part comprises charactron and charactron ; Described counter portion is mainly used in arranging initial time and carrying out subtraction, described decoder part is responsible for binary digital signal to be converted into ten's digit, driving numeral method numeral, described numeral method part, for showing numeral, can show the numerical value often carrying out pulsatile once.

Wherein the connection of its circuit is: described decimal system reversible counter chip cC74HC192 is a position, and it resets, and position CR holds, data input signal D3 ~ D0 connecting to neutral ground GND1, adds counting clock input CP _uconnect the high level of+5V, subtract counting clock input CP _dmeet pulse per second (PPS) CP, described decimal system reversible counter chip output Q3 ~ the Q0 of CC74HC192 connects described decoder the input of CC4511, carry flag CO is unsettled, and borrow mark BO receives decimal system reversible counter chip cC74HC192 subtracts counting clock input CP _d, described decimal system reversible counter chip cC74HC192 is ten, and its clear terminal CR, D3 and D0 ground connection GND2, D2 and D1 connects the power supply of+5V, decimal system reversible counter chip cC74HC192 adds counting clock input CP _uconnect the high level of+5V, subtract counting clock input CP _dconnect described decimal system reversible counter chip the borrow output BO of CC74HC192, described decimal system reversible counter chip the carry flag CO of CC74HC192 is unsettled, and BO is unsettled for borrow mark, and its output signal Q3 ~ Q0 connects described decoder the input of CC4511; Described decimal system reversible counter chip cC74HC192 and described decimal system reversible counter chip the resistance putting number end LD and 3k of CC74HC192 connects together, the power supply of another termination+5V of resistance, the resistance connecting valve S simultaneously of 3k, and switch S has two ends, and one end is starting end, and one end is for putting number end; Described decoder cC4511 and described decoder cC4511 is used to the numeral method data driving correspondence; Described decoder cC4511 and described decoder input A3 ~ the A0 of CC4511 connects described decimal system reversible counter chip respectively cC74HC192 and described decimal system reversible counter chip output Q3 ~ the Q0 of CC74HC192, keyed end LE connects low level, and blanking input BI and test input LT connects the power supply of+5V, described decoder cC4511 and described decoder output Ya ~ Yg end of CC4511 is connected to described charactron respectively by resistance R with described charactron a ~ g end.The utility model 60 seconds timer circuit differences from prior art are that the utility model achieves following technique effect: after circuit working, and charactron reduces with the speed of one second from display for 60 seconds, until reduce to display 00, thus realize the effect of timing in 60 seconds.

Below in conjunction with accompanying drawing, the utility model is described in further detail.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the utility model 60 seconds timer circuits.

Description of reference numerals: CC74HC192 (1): decimal system reversible counter chip ; CC74HC192 (2): decimal system reversible counter chip ; CPU: add counting clock input; CPD: subtract counting clock input; BO: borrow end; CO: carry end; CP: pulse per second (PPS); D3 ~ D0: counter data input; Q3 ~ Q0: counter data output; CC4511: decoder; LE: keyed end; BI: blanking input; LT: test input; A3 ~ A0: decoder data input; Ya ~ Yg: decoder data output; U1, U2: charactron; GND1, GND2: ground end.

Embodiment

Below in conjunction with drawings and Examples, to above-mentioned being described in more detail with other technical characteristic and advantage of the utility model.

Embodiment 1 when control switch S beats keep off " putting number " time, the LD end of two panels decimal system reversible counter chip CT74LS192 for low level, adds and resets as CR is low level.Decimal system reversible counter chip d3 ~ the D0 of CC74HC192 (1) is 0000, its output Q3 ~ Q0 is also 0000, the input signal end A3 ~ A0 of decoder chip CC4511 (2) is also 0000, according to decoder operation principle, it is 0 that input signal 0000 is converted into binary system by decoder, and charactron U2 shows digital signaling zero.Decimal system reversible counter chip d3 ~ the D0 of CC74HC192 (2) is 0110, in like manner its output Q3 ~ Q0 is also 0110, the input signal end A3 ~ A0 of decoder chip CC4511 (1) is also 0110, according to decoder operation principle, it is 6 that input signal 0110 is converted into binary system by decoder, and charactron U1 shows digital signal 6.Such charactron U1 and U2 shows 60, and namely counter is set to 60 seconds, subtracts counting pulse per second (PPS) CP by decimal system reversible counter chip the counting clock input CPD that subtracts of CC74HC192 (1) inputs, and its cycle is 1 second.

Embodiment 2

When control switch S beat keep off in " beginning " time, then counter starts to carry out subtracting timing, decimal system reversible counter chip cC74HC192 (1) from 0000 become 1001, such decimal system reversible counter chip output Q3 ~ the Q0 of CC74HC192 (1) is also 1001, the input signal end A3 ~ A0 of decoder chip CC4511 (2) is also 1001, according to decoder operation principle, it is 9 that input signal 1001 is converted into binary system by decoder, namely on charactron U2 from display 0 become 9.Borrow end BO produces high level signal, impels decimal system reversible counter chip cC74HC192 (2) works, i.e. decimal system reversible counter chip cC74HC192 (2) starts to do subtraction.Such decimal system reversible counter chip cC74HC192 (2) from 0110 become 0101, its output Q3 ~ Q0 is also 0101, the input signal end A3 ~ A0 of decoder chip CC4511 (1) is also 0101, according to decoder operation principle, it is 5 that input signal 0101 is converted into binary system by decoder, namely on charactron U1 from display 6 become 5.Such charactron U1 and U2 then by display 60 just become display 59 seconds, until change to 00, realize 60 seconds timers.When new round countdown in 60 seconds will be carried out, still need repetition aforesaid operations process.

Above-described embodiment is only be described preferred implementation of the present utility model; not scope of the present utility model is limited; under the prerequisite not departing from the utility model design spirit; the various distortion that those of ordinary skill in the art make the technical solution of the utility model and improvement, all should fall in protection range that the utility model claims determine.

Claims

1. 60 seconds timer circuits, is characterized in that: described circuit comprises counter portion, decoder part and numeral method part, and described counter portion comprises the decimal system reversible counter chip of a position cC74HC192 and decimal system reversible counter chip cC74HC192; Described decoder part comprises decoder cC4511 and decoder cC4511; Described numeral method part comprises charactron and charactron ; Described counter portion is mainly used in arranging initial time and carrying out subtraction, described decoder part is responsible for binary digital signal to be converted into ten's digit, driving numeral method numeral, described numeral method part, for showing numeral, can show the numerical value often carrying out pulsatile once; Its circuit connects: described decimal system reversible counter chip cC74HC192 is a position, and it resets, and position CR holds, data input signal D3 ~ D0 connecting to neutral ground GND1, adds counting clock input CP _uconnect the high level of+5V, subtract counting clock input CP _dmeet pulse per second (PPS) CP, described decimal system reversible counter chip output Q3 ~ the Q0 of CC74HC192 connects described decoder the input of CC4511, carry flag CO is unsettled, and borrow mark BO receives decimal system reversible counter chip cC74HC192 subtracts counting clock input CP _d, described decimal system reversible counter chip cC74HC192 is ten, and its clear terminal CR, D3 and D0 ground connection GND2, D2 and D1 connects the power supply of+5V, decimal system reversible counter chip cC74HC192 adds counting clock input CP _uconnect the high level of+5V, subtract counting clock input CP _dconnect described decimal system reversible counter chip the borrow output BO of CC74HC192, described decimal system reversible counter chip the carry flag CO of CC74HC192 is unsettled, and BO is unsettled for borrow mark, and its output signal Q3 ~ Q0 connects described decoder the input of CC4511; Described decimal system reversible counter chip cC74HC192 and described decimal system reversible counter chip the resistance putting number end LD and 3k of CC74HC192 connects together, the power supply of another termination+5V of resistance, the resistance connecting valve S simultaneously of 3k, and switch S has two ends, and one end is starting end, and one end is for putting number end; Described decoder cC4511 and described decoder cC4511 is used to the numeral method data driving correspondence; Described decoder cC4511 and described decoder input A3 ~ the A0 of CC4511 connects described decimal system reversible counter chip respectively cC74HC192 and described decimal system reversible counter chip output Q3 ~ the Q0 of CC74HC192, keyed end LE connects low level, and blanking input BI and test input LT connects the power supply of+5V, described decoder cC4511 and described decoder output Ya ~ Yg end of CC4511 is connected to described charactron respectively by resistance R with described charactron a ~ g end.