CN204649825U - Based on the high speed true effective value rectifying system of FPGA - Google Patents
Based on the high speed true effective value rectifying system of FPGA Download PDFInfo
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- CN204649825U CN204649825U CN201520331275.3U CN201520331275U CN204649825U CN 204649825 U CN204649825 U CN 204649825U CN 201520331275 U CN201520331275 U CN 201520331275U CN 204649825 U CN204649825 U CN 204649825U
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Abstract
The utility model discloses a kind of high speed true effective value rectifying system based on FPGA, comprise the signal amplifier, A/D converter, FPGA module and the control module that connect successively; The utility model utilizes A/D converter to be combined with FPGA module, carries out step_by_step integration to measured signal; In order to reduce noise to measurement impact, this wave detector also introduces the medium filtering of signal, improves measuring accuracy to a great extent; The utility model can in a cycle of measured signal, and the true rms measurement of complete pair signals, has the advantages such as the range of linearity is wide, precision is high, good stability, and dirigibility is strong simultaneously.
Description
Technical field
The utility model relates to electronic technology field, relates to a kind of high speed true effective value rectifying system based on FPGA by it.
Background technology
In the electric parameter measurement of electronic system and electric system and industrial enterprise's distribution system, real effective is a kind of most important, the most frequently used electrical quantity.Any measurement had about power, all be unable to do without the RMS to DC of current/voltage, and measures effective value and usually rely on peak value measurement or rectified mean value to measure or use integrated chip to carry out effective value detection, and as AD536, AD637 etc. realize.But when namely there being direct current also to there is complicated alternating component or harmonic wave in measured signal, only adopt peak value measurement or rectified mean value detection, this kind of measurement will produce larger error, even can not work on.Step by step integration can complete and detect the real effective of random waveform, a lot of integrated chip all adopts step by step integration to measure signal effective value, but its temperature influence is large, must to temperature compensation in circuit, poor stability, and work efficiency is lower, the measurement can only carried out lower than 10 times per second substantially.Obviously, when system needs Quick Measurement to carry out follow-up work, this kind of chip often also exists fatal defect.Therefore, need a kind of range of linearity wider, precision is high, and response is fast, can the true effective value rectifying system of widespread use.
Utility model content
Being subject to the shortcoming of measured signal restriction, low-response and the range of linearity in order to overcome existing true effective value rectifying measurement, the utility model proposes a kind of high speed true effective value rectifying system based on FPGA.
The technical scheme that the utility model adopts is: a kind of high speed true effective value rectifying system based on FPGA, comprises the signal amplifier, A/D converter, FPGA module and the control module that connect successively.
Further, described FPGA module comprises median filter unit, absolute value element, time weighted unit and quadratic sum unit; Described median filter unit, absolute value element are connected successively with time weighted unit, and described quadratic sum unit is connected with absolute value element.
Further, described control module comprises the root mean square unit and display unit that connect successively.
The beneficial effects of the utility model are: a kind of high speed true effective value rectifying system based on FPGA utilizes A/D converter to be combined with FPGA, carries out step_by_step integration to measured signal; In order to reduce noise to measurement impact, this wave detector also introduces the medium filtering of signal, improves measuring accuracy to a great extent.The utility model can in a cycle of measured signal, and the true rms measurement of complete pair signals, has the advantages such as the range of linearity is wide, precision is high, good stability, and dirigibility is strong simultaneously.
Accompanying drawing explanation
Fig. 1 is digital true effective value rectifying schematic diagram of the present utility model.
Embodiment
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, is exemplary below by the embodiment be described with reference to the drawings, and only for explaining the utility model, and can not be interpreted as restriction of the present utility model.
Based on a high speed true effective value rectifying system of FPGA, comprise the signal amplifier, A/D converter, FPGA module and the control module that connect successively.
Described FPGA module comprises median filter unit, absolute value element, time weighted unit and quadratic sum unit; Described median filter unit, absolute value element are connected successively with time weighted unit, and described quadratic sum unit is connected with absolute value element.
Described control module comprises the root mean square unit and display unit that connect successively.
As Fig. 1, signal is first through signal amplifier, after measured signal is amplified, enter AD converter analog quantity is converted into digital quantity enters FPGA module, median filter unit in FPGA module is by signal medium filtering, after removing noise, in time weighted unit, time weighted is carried out to it simultaneously, ask the absolute value of measured signal to ensure the correctness next asking quadratic sum to calculate to signal in absolute value element, quadratic sum is tried to achieve through quadratic sum unit, the root mean square unit outputting to control module asks root mean square, and is shown by display unit.
Signal is converted to by A/D the median filter unit that digital signal enters FPGA, median filter unit has Liang Ge data queue, and one keeps first in first out, data were sorted according to the time, ensure the participation intermediate value screening that each data can be real-time, improve the correctness of data.Another is for the sequence of data, thus chooses intermediate value and output to and ask absolute value element.Time weighted unit carries out time weighted, when known signal frequency, sampling number is set according to the actual requirements and produces sampling clock with Direct Digital Synthesizer DDS, the time of carrying out weighted, ensure that the whole cycle of control module to signal carries out step_by_step integration, quadratic sum result and set sampling number are outputted to control module and process by final FPGA module.
When the unknown of measured signal frequency, estimate the maximum possible frequency of measured signal, the signal gathered according to actual needs is counted and is obtained the sampling clock of signal.At signal after median filter unit medium filtering, sampling clock is as the work clock asking absolute value and quadratic sum to calculate, and have the function of absolute value element, quadratic sum unit, quadratic sum result outputs in control module the most at last.Sampling number adds one at the rising edge of each sampling clock, judge signal be a complete cycle according to being signal whether zero crossing, when forward (by just bearing) zero crossing, sampling number outputs to zero setting in FPGA module again after in control module, realizes the time weighted of time weighted unit.
The concrete control realization of the utility model is prior art, and the utility model is generator structure-design technique scheme only.
Claims (2)
1. based on a high speed true effective value rectifying system of FPGA, it is characterized in that: comprise the signal amplifier, A/D converter, FPGA module and the control module that connect successively; Described FPGA module comprises median filter unit, absolute value element, time weighted unit and quadratic sum unit; Described median filter unit, absolute value element are connected successively with time weighted unit, and described quadratic sum unit is connected with absolute value element.
2. a kind of high speed true effective value rectifying system based on FPGA according to claim 1, is characterized in that: described control module comprises the root mean square unit and display unit that connect successively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520331275.3U CN204649825U (en) | 2015-05-21 | 2015-05-21 | Based on the high speed true effective value rectifying system of FPGA |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520331275.3U CN204649825U (en) | 2015-05-21 | 2015-05-21 | Based on the high speed true effective value rectifying system of FPGA |
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| CN204649825U true CN204649825U (en) | 2015-09-16 |
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| CN201520331275.3U Expired - Fee Related CN204649825U (en) | 2015-05-21 | 2015-05-21 | Based on the high speed true effective value rectifying system of FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112782460A (en) * | 2019-11-04 | 2021-05-11 | 江苏莱提电气股份有限公司 | Method for calculating effective value of alternating voltage |
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2015
- 2015-05-21 CN CN201520331275.3U patent/CN204649825U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112782460A (en) * | 2019-11-04 | 2021-05-11 | 江苏莱提电气股份有限公司 | Method for calculating effective value of alternating voltage |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150916 Termination date: 20160521 |
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| CF01 | Termination of patent right due to non-payment of annual fee |