CN204649825U - Based on the high speed true effective value rectifying system of FPGA - Google Patents

Abstract

The utility model discloses a high-speed true effective value detection system based on FPGA, which comprises a signal amplifier, an A/D converter, an FPGA module and a control module connected in sequence; the utility model utilizes the combination of the A/D converter and the FPGA module, The signal to be measured is gradually integrated; in order to reduce the influence of noise on the measurement, the detector also introduces the median filter of the signal, which greatly improves the measurement accuracy; The true RMS measurement of the signal has the advantages of wide linear range, high precision, good stability and strong flexibility.

Description

High Speed True RMS Detection System Based on FPGA

technical field

The utility model relates to the field of electronic technology, in particular to an FPGA-based high-speed true effective value detection system.

Background technique

In the measurement of electrical parameters of electronic systems, power systems, and industrial enterprise power distribution systems, the true effective value is one of the most important and commonly used electrical parameters. Any measurement related to power is inseparable from the RMS detection of current and voltage, and the measurement of RMS usually relies on peak measurement or rectified average value measurement or the use of integrated chips for RMS detection, such as AD536, AD637, etc. to achieve. However, when the signal to be measured contains both DC and complex AC components or harmonics, only using peak value measurement or rectified average value detection, this type of measurement will produce large errors, and even cannot continue to work. The step-by-step integration method can complete the true RMS detection of arbitrary waveforms. Many integrated chips use the step-by-step integration method to measure the signal RMS, but it is greatly affected by temperature, and the circuit must be compensated for temperature, which has poor stability and low work efficiency. Low, basically only less than 10 measurements can be made per second. Obviously, such chips often have fatal flaws when the system requires fast measurements for follow-up work. Therefore, there is a need for a true RMS detection system with wide linear range, high precision, fast response and wide application.

Utility model content

In order to overcome the shortcomings of the existing true effective value detection measurement being limited by the signal to be tested, slow response and linear range, the utility model proposes a high-speed true effective value detection system based on FPGA.

The technical scheme adopted by the utility model is: a high-speed true RMS detection system based on FPGA, including a signal amplifier, an A/D converter, an FPGA module and a control module connected in sequence.

Further, the FPGA module includes a median filter unit, an absolute value unit, a time weighting unit and a square sum unit; the median filter unit, the absolute value unit and the time weight unit are connected in sequence, and the square And unit and absolute value unit connection.

Further, the control module includes a root mean square unit and a display unit connected in sequence.

The beneficial effects of the utility model are: a high-speed true RMS detection system based on FPGA utilizes the combination of A/D converter and FPGA to gradually integrate the signal to be measured; in order to reduce the impact of noise on the measurement, the detector also introduces a signal The median filter improves the measurement accuracy to a great extent. The utility model can complete the measurement of the true effective value of the signal in one period of the signal to be measured, and has the advantages of wide linear range, high precision, good stability and strong flexibility.

Description of drawings

Fig. 1 is a schematic diagram of digital true RMS detection of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, and examples of said embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary, and are only used to explain the present utility model, and cannot be construed as a reference to the present utility model. New types of restrictions.

A FPGA-based high-speed true RMS detection system includes signal amplifiers, A/D converters, FPGA modules and control modules connected in sequence.

Described FPGA module comprises median filtering unit, absolute value unit, time weighting unit and square sum unit; Described median filtering unit, absolute value unit and time weighting unit are connected successively, and described square sum unit and Absolute unit connection.

The control module includes a root mean square unit and a display unit connected in sequence.

As shown in Figure 1, the signal first passes through the signal amplifier, after the signal to be tested is amplified, it enters the AD converter to convert the analog quantity into a digital quantity and enters the FPGA module. The median filter unit in the FPGA module filters the median value of the signal and removes the noise. At the same time, it is time-weighted in the time weighting unit, and the absolute value of the signal to be measured is calculated in the absolute value unit to ensure the correctness of the subsequent calculation of the square sum of the signal, and the square sum is obtained through the square sum unit and output to The root mean square unit of the control module calculates the root mean square and displays it on the display unit.

The signal is converted into a digital signal through A/D and enters the median filter unit of the FPGA. The median filter unit has two data queues, one of which maintains the first-in-first-out principle and sorts the data according to time to ensure that each bit of data can be processed in real time. Participate in median screening to improve data accuracy. The other is used for data sorting, so that the median value is selected and output to the absolute value unit. The time weighting unit performs time weighting. When the signal frequency is known, the number of sampling points is set according to the actual demand and the direct digital frequency synthesizer DDS is used to generate the sampling clock for time weighting, so as to ensure that the control module controls the entire period of the signal. Integrate step by step, and finally the FPGA module outputs the sum of squares and the set number of sampling points to the control module for processing.

When the frequency of the signal to be measured is unknown, the maximum possible frequency of the signal to be measured is estimated, and the sampling clock of the signal is obtained according to the actual number of signal points to be collected. After the signal is filtered by the median filter unit, the sampling clock is used as the working clock for absolute value and square sum calculation, and has the functions of absolute value unit and square sum unit, and finally outputs the square sum result to the control module. The number of sampling points is increased by one on each rising edge of the sampling clock. The basis for judging that the signal is a complete cycle is whether the signal crosses zero. When the positive direction (from negative to positive) zero crosses, the number of sampling points is output to the control module and re-introduced in the FPGA Set zero in the module to realize the time weighting of the time weighting unit.

The concrete control realization of the utility model is the prior art, and the utility model only provides the technical scheme of device structure design.

Claims (2)

1. based on a high speed true effective value rectifying system of FPGA, it is characterized in that: comprise the signal amplifier, A/D converter, FPGA module and the control module that connect successively; Described FPGA module comprises median filter unit, absolute value element, time weighted unit and quadratic sum unit; Described median filter unit, absolute value element are connected successively with time weighted unit, and described quadratic sum unit is connected with absolute value element.

2. a kind of high speed true effective value rectifying system based on FPGA according to claim 1, is characterized in that: described control module comprises the root mean square unit and display unit that connect successively.