CN204576487U - Parallel computation multiplexing Mux - Google Patents
Parallel computation multiplexing Mux Download PDFInfo
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- CN204576487U CN204576487U CN201520184406.XU CN201520184406U CN204576487U CN 204576487 U CN204576487 U CN 204576487U CN 201520184406 U CN201520184406 U CN 201520184406U CN 204576487 U CN204576487 U CN 204576487U
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- calculating sub
- single task
- transfer bus
- parallel computation
- sub module
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Abstract
The utility model relates to a kind of parallel computation multiplexing Mux, comprise multiple single task calculating sub module and transfer bus, described single task calculating sub module comprises central processing unit, internal memory, storer, power management module and multibus controller transfer bus, described central processing unit, internal memory, storer, power management module, multibus controller connect successively, and the multibus controller of each single task calculating sub module is connected with transfer bus respectively.Compared with prior art, the utility model has that computing velocity is fast, extendability is strong and the advantage such as the product life cycle is long.
Description
Technical field
The utility model relates to a kind of calculating multiplexing Mux, especially relates to a kind of parallel computation multiplexing Mux being applicable to long-time use.
Background technology
Existing embedded OS, has multiple IO (input and output) port usually, and these IO ports comprise universal asynchronous receiving-transmitting interface, Serial Peripheral Interface (SPI), speed universal serial bus interface, SD card interface etc.Just require that when two or more IO port carries out data transmit-receive simultaneously embedded OS can carry out parallel processing.Multitask then refers at a time has multiple task to run at the same time, realizes multitask by multiprocessors parallel processing.But the situation of bus collision can be there is in the communication between CPU.At present, there is the bus architecture of some parallel multiprocessor communications, the Communication between each CPU in the application of existing multiprocessors parallel processing can be solved.But it is short all to there is the product life cycle in most of multitask system, the shortcomings such as extendability is not enough.
Utility model content
The purpose of this utility model is exactly provide that a kind of computing velocity is fast, extendability is strong to overcome defect that above-mentioned prior art exists and parallel computation multiplexing Mux that life cycle is long.
The purpose of this utility model can be achieved through the following technical solutions:
A kind of parallel computation multiplexing Mux, it is characterized in that, comprise multiple single task calculating sub module and transfer bus, described single task calculating sub module comprises central processing unit, internal memory, storer, power management module and multibus controller transfer bus, described central processing unit, internal memory, storer, power management module, multibus controller connect successively, and the multibus controller of each single task calculating sub module is connected with transfer bus respectively.
Described central processing unit adopts Intel 80486 type CPU.
Described transfer bus is Multibus bus.
Described storer is electrically-erasable memory
Described multiple single task calculating sub module are interconnected by transfer bus, communicate and work alone.
This system comprises following two kinds of working methods:
1) each single task calculating sub module performs multiple different task simultaneously;
2) task is converted into the pattern of applicable parallel computation, gives multiple single task calculating sub module and come.
Compared with prior art, the utility model has the following advantages:
1, extendability is strong, if system needs to promote calculated performance, only needs to add one or more single task calculating sub module again.
2, system maintenance and maintenance are conveniently, if there is a single task calculating sub module to break down, only needs to replace that single task calculating sub module of makeing mistakes, and do not need whole system to replace together.
3, the product life cycle is long, is especially applicable to the industrial products that needs use for a long time.
4, data rate is fast, adopts parallel mode effectively can improve the transmission speed of data.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in detail.
Embodiment
As shown in Figure 1, a kind of parallel computation multiplexing Mux, comprise transfer bus 1, central processing unit 21, internal memory 22, electrically-erasable memory 23, power management module 24, multibus controller 25, described central processing unit 21, internal memory 22, electrically-erasable memory 23, power management module 24, multibus controller 25 connect to form single task calculating sub module 2 successively, and described multiple single task calculating sub module 2 is articulated in multitask system transfer bus 1 being formed parallel computation successively.
Described central processing unit 21 adopts Intel 80486 type CPU.Described transfer bus 1 is Multibus bus.Described multiple single task calculating sub module 2 are interconnected by bus, communicate and work alone.
Utility model works flow process is as follows:
1) to system power supply;
2) internal memory is loaded into being stored in electricity erasing chip internal program;
3) program in internal memory is performed;
4) each single task calculating sub module is interconnected by bus, communicates and work alone.
This system comprises following two kinds of working methods:
1) each single task calculating sub module performs multiple different task simultaneously;
2) task is converted into the pattern of applicable parallel computation, gives multiple single task calculating sub module and come.
Claims (4)
1. a parallel computation multiplexing Mux, it is characterized in that, comprise multiple single task calculating sub module and transfer bus, described single task calculating sub module comprises central processing unit, internal memory, storer, power management module and multibus controller transfer bus, described central processing unit, internal memory, storer, power management module, multibus controller connect successively, and the multibus controller of each single task calculating sub module is connected with transfer bus respectively.
2. a kind of parallel computation multiplexing Mux according to claim 1, is characterized in that, described central processing unit adopts Intel 80486 type CPU.
3. a kind of parallel computation multiplexing Mux according to claim 1, is characterized in that, described transfer bus is Multibus bus.
4. a kind of parallel computation multiplexing Mux according to claim 1, is characterized in that, described storer is electrically-erasable memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520184406.XU CN204576487U (en) | 2015-03-30 | 2015-03-30 | Parallel computation multiplexing Mux |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520184406.XU CN204576487U (en) | 2015-03-30 | 2015-03-30 | Parallel computation multiplexing Mux |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204576487U true CN204576487U (en) | 2015-08-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520184406.XU Expired - Fee Related CN204576487U (en) | 2015-03-30 | 2015-03-30 | Parallel computation multiplexing Mux |
Country Status (1)
| Country | Link |
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| CN (1) | CN204576487U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107357646A (en) * | 2017-09-01 | 2017-11-17 | 长沙小卡机器人科技有限公司 | The equipment of multitask sequential parallel operation |
| CN111708636A (en) * | 2020-06-16 | 2020-09-25 | 西安微电子技术研究所 | CPCI parallel processing system and method based on multiprocessor |
-
2015
- 2015-03-30 CN CN201520184406.XU patent/CN204576487U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107357646A (en) * | 2017-09-01 | 2017-11-17 | 长沙小卡机器人科技有限公司 | The equipment of multitask sequential parallel operation |
| CN111708636A (en) * | 2020-06-16 | 2020-09-25 | 西安微电子技术研究所 | CPCI parallel processing system and method based on multiprocessor |
| CN111708636B (en) * | 2020-06-16 | 2024-03-08 | 西安微电子技术研究所 | CPCI parallel processing system and method based on multiple processors |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150819 Termination date: 20190330 |