CN204258748U

CN204258748U - A kind of ultrasonic echo duty cycle measurement circuit

Info

Publication number: CN204258748U
Application number: CN201420589282.9U
Authority: CN
Inventors: 桑涛; 邱德华; 单来成; 尚绪树; 李启龙; 宋金凤
Original assignee: Shandong Lichuang Science and Technology Co Ltd
Current assignee: Shandong Lichuang Science and Technology Co Ltd
Priority date: 2014-10-13
Filing date: 2014-10-13
Publication date: 2015-04-08
Anticipated expiration: 2024-10-13

Abstract

The utility model provides a kind of ultrasonic echo duty cycle measurement circuit, comprise echo counter U0, it is characterized in that: the CLK input port of described echo counter U0 connects outside echo impulse ECHO, described echo counter U0 connects ring oscillator U3, described ring oscillator U3 connects trailing edge detector U1, latch U2 and high-speed counter U4 respectively, the D input port of described trailing edge detector U1 connects outside echo impulse ECHO, described high-speed counter U4 connects described latch U2 and divider U5, and described latch U2 connects described divider U5.This circuit does not increase outside high-frequency clock, but have employed the scheme that inside circuit produces high-frequency clock, even if the clock of ring oscillator with factors vary such as voltage temperatures, also can not can impact the certainty of measurement of this circuit, be very suitable for realizing at IC interior.

Description

A kind of ultrasonic echo duty cycle measurement circuit

Technical field

The utility model relates to measuring ultrasonic wave flow field, concretely, relates to a kind of ultrasonic echo duty cycle measurement circuit.

Background technology

Measuring ultrasonic wave flow adopts Principles of Acoustics to measure the rate of flow of fluid flowing through pipeline: be arranged on flow conduit wall by a pair ultrasonic transducer, in flow measurement process, element on wiring board applies pumping signal to transmitting transducer makes it produce ultrasonic wave, receiving transducer is converted into the signal of telecommunication after receiving signal, measuring circuit can write down the time from being transmitted into reception, according to the principle of Kepler's effect, under co-current flow and counter-current flow situation, hyperacoustic propagation velocity can change, and utilizes the concurrent-countercurrent time difference measured can calculate the speed of fluid.In practical application, ultrasonic echo nonideal sine wave, especially the several waveform in foremost, after being converted to square wave, be not the square wave of duty ratio 50% yet, and transducer in use there will be aging, the phenomenons such as fouling, the amplitude of waveform is directly caused to die down gradually, experimentally, give up the waveform of foremost instability, utilize several ripples of amplitude stability can obtain reasonable measurement result, and the duty ratio of echo is the important evidence judging ultrasonic wave degree of stability, in general calorimeter, the frequency of ultrasonic echo is 1MHz, this means to carry out measuring the duty ratio that can obtain precision about 1% with the clock of 100Mhz, but generally can not provide so high-frequency clock source in actual heat table, for addressing this problem, the utility model provides a kind of ultrasonic echo duty cycle measurement circuit and method of measurement thereof.

Utility model content:

The technical problems to be solved in the utility model is to provide a kind of ultrasonic echo duty cycle measurement circuit, avoids the impact of the factors vary such as voltage temperature on circuit measuring.

The utility model adopts following technological means to realize utility model object:

A kind of ultrasonic echo duty cycle measurement circuit, comprise echo counter U0, it is characterized in that: the CLK input port of described echo counter U0 connects outside echo impulse ECHO, described echo counter U0 connects ring oscillator U3, described ring oscillator U3 connects trailing edge detector U1, latch U2 and high-speed counter U4 respectively, the D input port of described trailing edge detector U1 connects outside echo impulse ECHO, described high-speed counter U4 connects described latch U2 and divider U5, and described latch U2 connects described divider U5.

As the further restriction to the technical program, the EQ port of described echo counter U0 connects the OSC_EN port of described ring oscillator U3.

As the further restriction to the technical program, the CLK port of described ring oscillator U3 connects the CLK port of the described CLK port of trailing edge detector U1, the CLK port of latch U2 and high-speed counter U4 respectively.

As the further restriction to the technical program, the Q port of described trailing edge detector U1 connects the EN port of described latch U2.

As the further restriction to the technical program, the CNT port of described high-speed counter U4 connects the D1 port of described latch U2.

As the further restriction to the technical program, the DO port of described latch U2 connects described divider U5.

As the further restriction to the technical program, the CNT port of described high-speed counter U4 connects described divider U5.

Compared with prior art, advantage of the present utility model and good effect are: this circuit does not increase outside high-frequency clock, but have employed the scheme that inside circuit produces high-frequency clock, even if the clock of ring oscillator can with factors vary such as voltage temperatures, also can not impact the certainty of measurement of this circuit, be very suitable for realizing at IC interior.

Accompanying drawing explanation

Fig. 1 is the block diagram of the utility model preferred embodiment.

Fig. 2 is the working waveform figure of part key signal in the utility model preferred embodiment.

Embodiment:

Below in conjunction with embodiment, further illustrate the utility model.

See Fig. 1 and Fig. 2, the utility model comprises echo counter U0, trailing edge detector U1, latch U2, ring oscillator U3, high-speed counter U4, divider U5, the CLK input port of described echo counter U0 connects outside echo impulse ECHO, ECHO is the square wave exported after ultrasonic signal shaping, employing prior art obtains, do not repeat them here, the rising edge of echo counter U0 internal counter to ECHO counts, when count value reaches preset several N, output EQ is set to high level by U0, is low level in other situations; The input OSC_EN of described ring oscillator U3 connects the EQ output of described echo counter U0, and when the OSC_EN of ring oscillator U3 is high level, the CLK of ring oscillator U3 holds output clock pulse; The clock input CLK of described high-speed counter U4 connects the CLK output of described ring oscillator U3, and high-speed counter U4 counts CLK rising edge, and CNT is that count results exports; The input clock CLK of described trailing edge detector U1 connects the output clock CLK of described ring oscillator, the detection input signal D of trailing edge detector U1 is from outside ECHO signal, the output Q of trailing edge detector U1 connects the enable signal EN of described latch U2, trailing edge detector U1 detects that ECHO is by after high step-down, and output Q exports the high level continuing a CLK clock cycle; The latch clock of described latch U2 connects the clock output CLK of ring oscillator U3, the enable EN of latch signal of latch U2 connects the Q end of trailing edge detector U1, the data input DI of latch U2 connects the CNT output of high-speed counter U4, and the latch data of latch U2 exports at DO port; The dividend port of described divider U5 connects the DO end of described latch U2, and the divisor port of divider U5 is connected to the CNT port of described high-speed counter U4, and the business of divider directly exports, and as echo-signal duty ratio, is labeled as DUTY.

The technical program additionally provides a kind of ultrasonic echo duty cycle measurement method, comprises the following steps:

(2.1) circuit initializes: echo counter U0 count value resets, high-speed counter U4 count value resets, and trailing edge detector Q holds clearing, and setting completed for circuit input N, and the high level duty ratio of the N number of pulse of measurement is expected in representative.

(2.2) ultrasonic echo signal ECHO arrives with continuous print high level pulse form, echo counter U0 adds the incremental count of under ECHO rising edge of a pulse drives at every turn, when count value is to when equaling N, the EQ output of echo counter U0 becomes high level, ring oscillator U3 is enabled, and produces high-speed clock signal and is supplied to high-speed counter U4, trailing edge detector U1, latch U2.

(2.3), after high-speed counter U4 obtains clock, carry out at each rising edge clock the incremental count adding, count value is labeled as CNT.

(2.4) continue to sample to echo-signal ECHO after trailing edge detector U1 obtains clock, N number of ECHO pulse becomes after low level from high level, the trailing edge of echo-signal ECHO is detected, the Q end of U1 exports the high level of one-period, as the latch enable signal of latch U2, the current count value CNT of high-speed counter U1 is latched, as the divisor of divider U5.

After (2.5) N+1 ECHO rising edge of a pulse, the EQ of echo counter U0 end becomes 0, and it is invalid that the enable signal EN of ring oscillator U3 becomes, the CLK no longer clock signal of U3; High-speed counter U4 counts stopping, and current count value CNT is as the dividend of divider U3.

(2.6) latched value of latch U2 and the final count value of high-speed counter are divided by by divider U5, and the business obtained is the duty ratio of N number of echo impulse, is labeled as DUTY.

Certainly; above-mentioned explanation is not limitation of the utility model; the utility model is also not limited only to above-mentioned citing, the change that those skilled in the art make in essential scope of the present utility model, remodeling, interpolation or replacement, also belongs to protection range of the present utility model.

Claims

1. a ultrasonic echo duty cycle measurement circuit, comprise echo counter U0, it is characterized in that: the CLK input port of described echo counter U0 connects outside echo impulse ECHO, described echo counter U0 connects ring oscillator U3, described ring oscillator U3 connects trailing edge detector U1, latch U2 and high-speed counter U4 respectively, the D input port of described trailing edge detector U1 connects outside echo impulse ECHO, described high-speed counter U4 connects described latch U2 and divider U5, and described latch U2 connects described divider U5.

2. ultrasonic echo duty cycle measurement circuit according to claim 1, is characterized in that: the EQ port of described echo counter U0 connects the OSC_EN port of described ring oscillator U3.

3. ultrasonic echo duty cycle measurement circuit according to claim 1, is characterized in that: the CLK port of described ring oscillator U3 connects the CLK port of the described CLK port of trailing edge detector U1, the CLK port of latch U2 and high-speed counter U4 respectively.

4. ultrasonic echo duty cycle measurement circuit according to claim 1, is characterized in that: the Q port of described trailing edge detector U1 connects the EN port of described latch U2.

5. ultrasonic echo duty cycle measurement circuit according to claim 1, is characterized in that: the CNT port of described high-speed counter U4 connects the D1 port of described latch U2.

6. ultrasonic echo duty cycle measurement circuit according to claim 1, is characterized in that: the DO port of described latch U2 connects described divider U5.

7. ultrasonic echo duty cycle measurement circuit according to claim 1, is characterized in that: the CNT port of described high-speed counter U4 connects described divider U5.