CN204231390U - Based on the ARCNET-HDLC gateway of C8051F040 core microprocessor - Google Patents
Based on the ARCNET-HDLC gateway of C8051F040 core microprocessor Download PDFInfo
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- CN204231390U CN204231390U CN201420722369.9U CN201420722369U CN204231390U CN 204231390 U CN204231390 U CN 204231390U CN 201420722369 U CN201420722369 U CN 201420722369U CN 204231390 U CN204231390 U CN 204231390U
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Abstract
The utility model discloses a kind of ARCNET-HDLC gateway based on C8051F040 core microprocessor, adopts card insert type design, comprises ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232 and USB interface board, backboard.Described ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232 are all connected by backboard with USB interface board, and power supply board is ARCNET interface board, HDLC interface board, master control board card, RS232 and USB interface board provide operating voltage.Described ARCNET interface board is responsible for the input and output of ARCNET bus data; Described HDLC interface board is responsible for the input and output of HDLC bus; Described master control board card, based on a slice C8051F040 microprocessor, is responsible for the encoding and decoding of ARCNET agreement, HDLC protocol encoding and decoding, protocol function conversion, is realized ARCNET bus master, the function of HDLC bus master and data processing.This gateway meets ANSI878.1 ARCNET and ISO13239-2002 standard, has the features such as highly versatile, reliability are strong, solves bus interface problem, is adapted at promoting in railway systems.
Description
Technical field
The utility model relates to a kind of ARCNET-HDLC gateway based on C8051F040 core microprocessor.
Background technology
Along with the high speed development of domestic railway, external a lot of advanced technology pours in domestic market.China's train communication bus now mainly contains ARCNET, HDLC, MVB and WORLDFIP etc.A car only have a kind of bus form to exist.This just relates to a problem, and the external interface of some product is fixing, thus occurs interface disunity when being applied on other bus trains, the phenomenon that cannot use.So ARCNET-HDLC gateway just becomes the necessary key equipment of two kinds of bus interface, for the technology versatility important in inhibiting of railway locomotive industry.
ARCNET is that the one developed by Datapoint company for 1977 installs Local Area Network technology widely, adopt the share wires between work station and other equipment on token bus (tokenbus) project management LAN, wherein, lan server always transmission empty information frame of continuous circulation in a bus.When there being equipment will send message, it just inserts one " token " and corresponding message in empty frame.After target device or lan server receive this message, just " token " is re-set as 0, so that this frame can by other equipment administration.This scheme is highly effective, and particularly when network load is large, it provides equality to use the chance of Internet resources for each equipment in network.ARCNET can adopt coaxial cable or cable line.ARCNET is one of 4 main lan technologys, and other three is Ethernet, tokenring and FDDI.Meanwhile, ARCNET is also one of means of communication in present Industry Control.Other communications also have PROFIBUDP, a series of means of communication such as CANOPEN, DEVICENET, ETHERNET.The bus feature that ARCNET standard specifies is as shown in table 1:
Table 1
Early seventies, IBM Corporation takes the lead in proposing bit-oriented synchronous data link control SDLC(Synchronous Data Link Control).Subsequently, ANSI and ISO all adopts and has developed SDLC, propose the standard of oneself respectively: the high level communication control procedure ADCCP(Advanced Data Control Procedure of ANSI), the high-level data link control procedure HDLC(High-level Data Link Control of ISO).HDLC is the Typical Representative of bit-oriented data link control protocol, and this agreement does not rely on any one character set; Data message can transparent transmission, is easy to hardware implementing for " the 0 bit insertion " realizing transparent transmission; Full-duplex communication, has higher data link transmission efficiency; All frames adopt CRC check, and carry out serial number to information frame, transmission reliability is high; Transmission controlling functions is separated with processing capacity.The bus feature that HDLC standard specifies is as shown in table 2:
Table 2
At present, China railways industry temporarily also not this series products, brings inconvenience to sub-supplier.When the interface of this product and train bus-line are not inconsistent, can only select to abandon.
Utility model content
The purpose of this utility model is solve above-mentioned technical problem and provide a kind of ARCNET-HDLC gateway based on C8051F040 core microprocessor, be mainly used in subway, light rail train and high speed motor car and City Rail Transit System, realize the interconnected of ARCNET network control system and HDLC network control system, there is ARCNET bus and to advocate peace HDLC network host node or the function from node.
For achieving the above object, the utility model adopts following technical scheme:
Based on the ARCNET-HDLC gateway of C8051F040 core microprocessor, adopt card insert type design, comprise ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232 and USB board card and backboard; Described ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232-USB board are all connected by backboard and communicate, and described power supply board provides operating voltage for described ARCNET interface board, HDLC interface board, master control board card and RS232-USB board; Described ARCNET interface board is responsible for the input and output of ARCNET bus data; Described HDLC interface board is responsible for the input and output of HDLC bus; Described master control board card for cpu central processing unit with a slice C8051F040 microprocessor, is responsible for the encoding and decoding of ARCNET agreement, HDLC protocol encoding and decoding, protocol function conversion, is realized ARCNET bus master, the function of HDLC bus master and data processing; The data that described cpu central processing unit is received from HDLC interface board and ARCNET interface board by described backboard process, and resolve and process simultaneously to the sync message of ARCNET bus and HDLC bus.
Described ARCNET interface board comprises 232 level transferring chip, ARCNET bus light-coupled isolation driver, electric current loop interface circuit; Described 232 level transferring chip are connected with described ARCNET bus light-coupled isolation driver, described ARCNET bus light-coupled isolation driver is connected with described electric current loop interface circuit, described 232 level transferring chip are connected with described backboard, receive from the device data sent here after described master control board card encoding and decoding, and be sent in ARCNET bus through described ARCNET bus light-coupled isolation driver, electric current loop interface circuit; Described electric current loop interface circuit connects ARCNET bus, after can receiving the data in ARCNET bus, decodes by delivering to described master control board card by described backboard after ARCNET bus light-coupled isolation driver and processes.
Described electric current loop interface circuit adopts 20MA electric current loop interface circuit.
Described HDLC interface board comprises HDLC protocol integrated test system chip, RS485 bus driver; Described HDLC protocol integrated test system chip is connected with described RS485 bus driver, and described HDLC protocol integrated test system chip receives by connecting described backboard the data sent here from master control board card, by being sent in HDLC bus after described RS485 bus driver conversion; Described RS485 bus driver connects HDLC bus, can receive the data in HDLC bus, and delivers to described master control board card through described HDLC protocol integrated test system chip from described backboard and process data.
Described HDLC interface board comprises a protection device, and described protection device is connected with described RS485 bus driver, for when the disturbed generation of HDLC bus is fluctuated, absorbs the pulse that voltage is higher.
Described master control board card comprises the clock circuit, electric source monitoring circuit, the reset circuit that are connected with described cpu central processing unit; Described cpu central processing unit is linked by described backboard and described ARCNET interface board and connects, and realizes transmitting-receiving and the encoding and decoding work of data; Described cpu central processing unit is linked by described backboard and HDLC interface board and connects, the application layer realizing HDLC data is resolved, data in bus and heartbeat message are carried out resolving and receiving and dispatching, the ARCNET data collected and HDLC data export from RS232-USB interface board through described backboard, and application program is downloaded by described RS232-USB interface board card.
Exchanges data is carried out by RAM between described HDLC protocol integrated test system chip and cpu central processing unit, the data transformations of reception is HDLC signal by described HDLC protocol integrated test system chip, be sent in HDLC bus by described RS485 bus driver, described HDLC protocol integrated test system chip also can read being stored in after data decode in RAM for cpu central processing unit simultaneously.
The utility model meets ARCNET and HDLC two kinds of train bus-lines of ANSI878.1 ARCNET and ISO13239-2002 standard, ARCNET-HDLC is the gateway simultaneously with ARCNET and HDLC communication function, change between two kinds of train bus-lines, the industrial control fields such as subway, light rail and railway locomotive can be widely used in; This ARCNET-HDLC gateway, fill up domestic blank, the fusion of the multiple train bus-line of China is more gone a step further, a solution is provided to the Train Control of mixed type, the train communication technology of China is more stepped on a new stage, simultaneously owing to adopting card insert type design, be convenient to installation and removal.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the utility model ARCNET-HDLC gateway;
Fig. 2 is master control board card CPU of the present utility model and peripheral circuit diagram thereof;
Fig. 3 is that ARCNET interface board of the present utility model links map interlinking;
Fig. 4 is that HDLC interface board of the present utility model links map interlinking;
Fig. 5 is that power panel of the present utility model links map interlinking; Fig. 6 is network topological diagram of the present utility model.
Embodiment
Below, in conjunction with example, substantive distinguishing features of the present utility model and advantage are further described, but the utility model is not limited to listed embodiment.
Refer to Fig. 1, a kind of ARCNET-HDLC gateway based on C8051F040 core microprocessor, adopt the card insert type design being convenient to mount and dismount, comprise ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232_USB interface board, described ARCNET interface board, HDLC interface board and RS232_USB interface board 5 are all connected on master control board card by backboard, power supply board is ARCNET interface board, HDLC interface board, master control board card, RS232_USB interface board provide operating voltage, and described ARCNET interface board is responsible for the input and output of ARCNET bus data, described HDLC interface board is responsible for the input and output of HDLC bus, described master control board card is using a slice C8051F040 microprocessor as cpu central processing unit, be responsible for the encoding and decoding of ARCNET agreement, HDLC protocol encoding and decoding, protocol function is changed, realize ARCNET bus master, the function of HDLC bus master and data processing, described RS232_USB interface board is based on RS232 protocol controller and USB interface, realize conversion output and the download program of agreement, described RS232 protocol controller connects cpu central processing unit and 232 interfaces, realize 232 interfaces to communicate with cpu central processing unit, USB interface is connected with cpu central processing unit.
As shown in Figure 2, described master control board card comprises cpu central processing unit, clock circuit and electric source monitoring circuit, reset circuit; The cpu central processing unit of master control board card is the microprocessor of a C8051F040 core, and it is connected with core bus, and core bus and ARCNET interface board link and connect, and realizes the transmitting-receiving of data and the work of encoding and decoding; Core bus and HDLC interface board link and connect, and the application layer realizing HDLC data is resolved, and carries out resolving and receiving and dispatching for the data in bus and heartbeat message; Core bus and RS232-USB interface board link and connect, the ARCNET data collected and HDLC data all exportable by RS232-USB interface, application program is also downloaded by RS232-USB interface.Master control board card is the core of whole module, is responsible for the parsing of all upper layer communication agreements.
As shown in Figure 3, described ARCNET interface board comprises 232 level transferring chip, ARCNET bus light-coupled isolation driver, electric current loop interface circuit, device data is delivered to after ARCNET interface board from master control Computer card CPU central processing unit through core bus, is sent in ARCNET bus by ARCNET bus light-coupled isolation driver and electric current loop interface circuit; Described ARCNET interface board can receive the data in ARCNET bus equally, processing by delivering in master control board card cpu central processing unit through backboard after electric current loop interface circuit and ARCNET bus light-coupled isolation driver, ARCNET prime frame can be sent by ARCNET interface board equally by master control board card.This electric current loop interface circuit can adopt 20MA electric current loop interface circuit.
As shown in Figure 4, described HDLC interface board comprises HDLC protocol integrated test system chip, RS485 bus driver, protection device; Described device data is sent to HDLC protocol integrated test system chip from the cpu central processing unit of master control board card through backboard, be sent in HDLC bus by RS485 bus driver, described HDLC interface board can receive the data in HDLC bus equally, after RS485 bus driver, deliver to master control board card cpu central processing unit through HDLC protocol integrated test system chip and data are processed.All HDLC application layer protocols are all resolved in master control board card cpu central processing unit.Protection device major function is when the disturbed generation fluctuation of HDLC bus, absorbs the pulse that voltage is higher.
Exchanges data is carried out by RAM between described HDLC protocol integrated test system chip and cpu central processing unit.The data transformations of reception is HDLC signal by HDLC protocol integrated test system chip, is sent in HDLC bus by RS485 bus driver, and HDLC protocol integrated test system chip also can read being stored in after data decode in RAM for cpu central processing unit simultaneously.
The cpu central processing unit of master control board card will receive the data from HDLC interface board and ARCNET interface board, processes data, also will resolve the sync message of ARCNET bus and HDLC bus and process simultaneously.
Wherein, the CTM1050T of master control board card CPU to be C8051F040, ARCNET bus light-coupled isolation driver be ZLG, electric current loop interface circuit are the B82793 of EPCOS, SP202EEN, HDLC protocol conversion chip of protection device to be PESD5V0L2BT, RS232 protocol controller be SIPEX be PT7A6525, RS485 bus driver of PERICOM is the MAX1480BEPI of MAXIM.Module all hardware is responsible for the parsing of ARCNET, HDLC, RS232-USB physical layer and link layer data, the data after parsing is sent to the cpu central processing unit of master control board card by core bus.The all software function of module is all resolve in master control board card cpu central processing unit, and the message after resolving is sent to interface board, and HDLC protocol integrated test system chip is the core of HDLC interface board, realizes the parsing of HDLC agreement, completes data transaction.
Described RS485 bus driver realizes HDLC physical layer interface and electrical isolation, be sent to cpu central processing unit when receiving new data and cause interruption, ARCNET bus light-coupled isolation driver is the core of ARCNET interface board, and the 20MA current signal in ARCNET bus is converted into TTL signal and is sent to cpu central processing unit and carries out encoding and decoding by it.
Whole ARCNET-HDLC gateway is furnished with 24V power interface, EMC meets TB3021-2001 and is attached to and connects car vehicle electronics and EN50121-3-2 standard, link with described power panel and connect, shown in Figure 5, described power supply board can adopt normal power supplies to design, and comprises power module, choke, high pressure ceramic disc capacitor, TVS device (can adopt P6KE15CA); Described choke, high pressure ceramic disc capacitor, TVS device are connected with described power module respectively, and external power source input module inputs this power module by choke.Power supply board take power module as core, for all circuit provide 5V, 3.3V, 2.5V, 1.8V power supply, described power module adopts the VRA2405D-10W of domestic Jin Shengyang company, 24V externally fed is converted into 5V, and then transfers 5V electricity to 3.3V, 2.5V and 1.8V voltage for master control board card, ARCNET interface board, HDLC interface board, RS232-USB interface board by integrated circuit (IC) chip AMS1117-3.3, AMS1117-2.5 and AMS1117-1.8.
The ARCNET-HDLC gateway be made up of above-mentioned a few part, can be connected with ARCNET and the HDLC network on train, realizes the conversion of two kinds of heterogeneous networks communication protocols, and the equipment of often kind of different agreement interface all needs a this gateway.
The network topology of this ARCNET-HDLC gateway as shown in Figure 6, master control board card is sent to by after the packet parsing in ARCNET bus by ARCNET interface board, master control board card processes for this message, is sent in HDLC bus by the message that HDLC needs by HDLC interface board.Equally, also process in master control board card for the message in HDLC bus, the effective message after process is sent in ARCNET bus.If train bus-line is HDLC network, ARCNET-HDLC gateway as ARCNET bus master, can also carry out ARCNET with needing the equipment changed and communicates, as traction electric machine, broadcast system etc., thus realize the compatibility of multiple bus.Equally, if train bus-line is ARCNET network, this equipment equally can as HDLC bus master.
The above is only preferred implementation of the present utility model; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (7)
1. based on the ARCNET-HDLC gateway of C8051F040 core microprocessor, it is characterized in that, adopt card insert type design, comprise ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232 and USB board card and backboard; Described ARCNET interface board, HDLC interface board, master control board card, power supply board, RS232-USB board are all connected by backboard and communicate, and described power supply board provides operating voltage for described ARCNET interface board, HDLC interface board, master control board card and RS232-USB board; Described ARCNET interface board is responsible for the input and output of ARCNET bus data; Described HDLC interface board is responsible for the input and output of HDLC bus; Described master control board card for cpu central processing unit with a slice C8051F040 microprocessor, is responsible for the encoding and decoding of ARCNET agreement, HDLC protocol encoding and decoding, protocol function conversion, is realized ARCNET bus master, the function of HDLC bus master and data processing; The data that described cpu central processing unit is received from HDLC interface board and ARCNET interface board by described backboard process, and resolve and process simultaneously to the sync message of ARCNET bus and HDLC bus.
2. the ARCNET-HDLC gateway based on C8051F040 core microprocessor according to claim 1, is characterized in that, described ARCNET interface board comprises 232 level transferring chip, ARCNE bus light-coupled isolation driver, electric current loop interface circuit; Described 232 level transferring chip are connected with described ARCNE bus light-coupled isolation driver, described ARCNE bus light-coupled isolation driver is connected with described electric current loop interface circuit, described 232 level transferring chip are connected with described backboard, receive from the device data sent here after described master control board card encoding and decoding, and be sent in ARCNET bus through described ARCNE bus light-coupled isolation driver, electric current loop interface circuit; Described electric current loop interface circuit connects ARCNET bus, after can receiving the data in ARCNET bus, decodes by delivering to described master control board card by described backboard after described ARCNET bus light-coupled isolation driver and processes.
3. the ARCNET-HDLC gateway based on C8051F040 core microprocessor according to claim 2, is characterized in that, described electric current loop interface circuit adopts 20MA electric current loop interface circuit.
4. the ARCNET-HDLC gateway based on C8051F040 core microprocessor according to Claims 2 or 3, is characterized in that, described HDLC interface board comprises HDLC protocol integrated test system chip, RS485 bus driver; Described HDLC protocol integrated test system chip is connected with described RS485 bus driver, and described HDLC protocol integrated test system chip receives by connecting described backboard the data sent here from master control board card, by being sent in HDLC bus after described RS485 bus driver conversion; Described RS485 bus driver connects HDLC bus, can receive the data in HDLC bus, and delivers to described master control board card through described HDLC protocol integrated test system chip from described backboard and process data.
5. the ARCNET-HDLC gateway based on C8051F040 core microprocessor according to claim 4; it is characterized in that; described HDLC interface board comprises a protection device; described protection device is connected with described RS485 bus driver; for when the disturbed generation of HDLC bus is fluctuated, absorb the pulse that voltage is higher.
6. the ARCNET-HDLC gateway based on C8051F040 core microprocessor according to claim 4, is characterized in that, described master control board card comprises the clock circuit, electric source monitoring circuit, the reset circuit that are connected with described cpu central processing unit; Described cpu central processing unit is linked by described backboard and described ARCNET interface board and connects, and realizes transmitting-receiving and the encoding and decoding work of data; Described cpu central processing unit is linked by described backboard and HDLC interface board and connects, the application layer realizing HDLC data is resolved, data in bus and heartbeat message are carried out resolving and receiving and dispatching, the ARCNET data collected and HDLC data export from described RS232-USB interface board through described backboard, and application program is downloaded by described RS232-USB interface board card.
7. the ARCNET-HDLC gateway based on C8051F040 core microprocessor according to claim 6, it is characterized in that, exchanges data is carried out by RAM between described HDLC protocol integrated test system chip and cpu central processing unit, the data transformations of reception is HDLC signal by described HDLC protocol integrated test system chip, be sent in HDLC bus by described RS485 bus driver, described HDLC protocol integrated test system chip also can read being stored in after data decode in RAM for cpu central processing unit simultaneously.
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| CN201420722369.9U CN204231390U (en) | 2014-11-27 | 2014-11-27 | Based on the ARCNET-HDLC gateway of C8051F040 core microprocessor |
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| CN201420722369.9U CN204231390U (en) | 2014-11-27 | 2014-11-27 | Based on the ARCNET-HDLC gateway of C8051F040 core microprocessor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107395478A (en) * | 2017-08-23 | 2017-11-24 | 上海兰宝传感科技股份有限公司 | A kind of network control system and network communication module for high speed cigarette packaging facilities |
| CN107689913A (en) * | 2017-08-04 | 2018-02-13 | 北京蓝普锋科技有限公司 | A kind of gateway device, data interactive method and device |
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2014
- 2014-11-27 CN CN201420722369.9U patent/CN204231390U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107689913A (en) * | 2017-08-04 | 2018-02-13 | 北京蓝普锋科技有限公司 | A kind of gateway device, data interactive method and device |
| CN107395478A (en) * | 2017-08-23 | 2017-11-24 | 上海兰宝传感科技股份有限公司 | A kind of network control system and network communication module for high speed cigarette packaging facilities |
| CN107395478B (en) * | 2017-08-23 | 2022-08-05 | 上海兰宝传感科技股份有限公司 | Network control system and network communication module for high-speed cigarette packaging equipment |
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