CN202183782U - MVB (multifunction vehicle bus)-CANOPEN gateway based on ARM seven nuclear microprocessor - Google Patents
MVB (multifunction vehicle bus)-CANOPEN gateway based on ARM seven nuclear microprocessor Download PDFInfo
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- CN202183782U CN202183782U CN2011200917008U CN201120091700U CN202183782U CN 202183782 U CN202183782 U CN 202183782U CN 2011200917008 U CN2011200917008 U CN 2011200917008U CN 201120091700 U CN201120091700 U CN 201120091700U CN 202183782 U CN202183782 U CN 202183782U
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Abstract
The utility model discloses an MVB (multifunction vehicle bus)-CANOPEN gateway based on an ARM seven nuclear microprocessor, which comprises a main control circuit, and an MVB interface circuit and a CANOPEN interface circuit which are respectively connected with the main control circuit, as well as a power circuit which can provide working voltage for the main control circuit, the MVB interface circuit and the CANOPEN interface circuit, wherein the main control circuit comprises a CPU (central processing unit), an FPGA (field programmable gate array) coding and decoding device which is connected with the CPU, an RS232 protocol controller, a USB interface and an RS232 interface which is connected with the RS232 protocol controller, the MVB interface circuit is connected with the FPGA coding and decoding device, and the CANOPEN interface circuit is connected with the CPU. The gateway can realize communication protocol conversion of MVB and CANOPEN train buses, can be widely applied in the industrial control field that which is not unified in train buses, such as subways, light railways, railway locomotives and the like.
Description
Technical field
The utility model is specifically related to a kind of MVB-CANOPEN gateway based on ARM7; Meet IEC61375-1:2007, ISO11898 and CIA DS-301 Ver.4.02 standard; Have characteristics such as highly versatile, good reliability; Be fit to the present situation of China's subway, light rail multibus, solved bus interface problem, be adapted at promoting in the railway systems.
Background technology
Along with the high speed development of domestic railway, external a lot of advanced technology pour in the domestic market.The train communication bus of the present usefulness of China mainly contains MVB, CANOPEN, HDLC and WORLDFIP etc.On a car, have only a kind of bus form to exist.This just relates to a problem, and the external interface of some product is fixed, thereby occurs interface disunity, the phenomenon that can't use on being applied to other bus trains the time.So the MVB-CANOPEN gateway just becomes two kinds of key equipments that EBI is necessary, significance is arranged for the technological versatility of railway locomotive industry.
The MVB bus is a kind of train special bus, follows IEC61375-1:2007 " TCN " (be called for short TCN standard) standard, and it is the communication system of an opening, is used for being connected between railway car and distinct device.The TCN standard comprises two kinds of bus forms: two kinds of wired train bus WTB and MVB MVB.Former definition WTB is used for connecting between the compartment, and MVB is used in the compartment equipment and connects, but all adopts the MVB bus to be connected in producer compartment and the compartment mostly now, has simplified design process.The MVB bus communication speed is 1.5Mbit/s, and physical layer is divided into three kinds: (1) be used for short-distance transmission dielectric ESD (RS485,20.0m); (2) be used for middle distance transmission dielectric EMD (transformer coupled, 200.0m); (3) be used for long Distance Transmission the light medium (optical fiber, 2.0km).MVB bus characteristics are as shown in table 1.
CANOPEN is a kind of framework, and (Control Area Network, the high-rise communications protocol on CAN) is used widely at industrial control field at the control area net network.Follow ISO11898 standard and CIA DS-301 Ver.4.02 standard.The CAN bus has only defined physical layer and data link layer, does not have the given application layer, and itself is imperfect.The CAL agreement is present a kind of based on the high-rise communications protocol of CAN, and CAL provides 4 kinds of application layer services function: CMS, NMT, DBT and LMT.And during the CANOPEN agreement based on expanding on the CAL agreement basis.CANOPEN provides all network management services and insulation transportation protocol, and a kind of implementation of dcs is provided.CANOPEN allows the function of node arbitrarily to expand when guaranteeing the network node interoperability.The bus characteristics of CANOPEN standard code are as shown in table 2.
At present temporary transient this series products not also of China railways industry brings inconvenience for sub-supplier.When the interface of this product and train bus-line are not inconsistent, can only select to abandon.And domestic blank has been filled up in the success of MVB-CANOPEN gateway research and development, and the fusion of the multiple train bus-line of China is more gone a step further, and a solution is provided for the Train Control of mixed type, and the train communication technology of China is more stepped on a new stage.
The utility model content
The utility model is to solve the problems of the technologies described above a kind of MVB-CANOPEN gateway based on ARM7 nuclear microprocessor is provided; Be mainly used in subway, light rail train and City Rail Transit System; Realize the interconnected of MVB network control system and CANOPEN network control system, have the MVB bus function of CANOPEN network of advocating peace from node.
For solving the problems of the technologies described above, the technical scheme that the utility model adopts is following:
A kind of MVB-CANOPEN gateway based on ARM7 nuclear microprocessor, MVB interface circuit and the CANOPEN interface circuit that comprise governor circuit, is connected with described governor circuit respectively and be the power circuit that described governor circuit, MVB interface circuit and CANOPEN interface circuit provide operating voltage; Described governor circuit comprises CPU, the FPGA codec that is connected with described CPU, RS232 protocol controller, USB interface and the RS232 interface that is connected with described RS232 protocol controller; Described MVB interface circuit is connected with described FPGA codec, and described CANOPEN interface circuit is connected with described CPU.
Described MVB interface circuit comprises MVB bus driver, the isolating transformer that is connected with said MVB bus driver; Described MVB interface circuit is connected with described FPGA codec through described MVB bus driver.Device data sends on the MVB bus through MVB bus driver and isolating transformer after governor circuit CPU delivers to the FPGA codec encodes; Described MVB interface circuit receives the data on the MVB bus equally, delivers to the CPU that delivers to governor circuit after the FPGA codec is decoded through isolating transformer and MVB bus driver.
Described CANOPEN interface circuit comprises CANOPEN isolation protocol control module, conjugation inductance and the protection device that connects successively; Described CANOPEN interface circuit is connected with described CPU through described CANOPEN isolation protocol control module; Device data is sent to CANOPEN isolation protocol control module from governor circuit CPU, through being sent to behind the conjugation inductor filter on the CANOPEN bus; Described CANOPEN interface circuit receives the data on the CANOPEN bus equally, behind the conjugation inductance, delivers to the CPU of governor circuit through CANOPEN isolation protocol control module.
Carry out exchanges data through dual port RAM between described FPGA codec and the CPU; Described FPGA codec will be stored in after the data decode that described MVB interface circuit transmits and supply CPU to read in the dual port RAM; The storage that CPU will be sent to described MVB interface circuit supplies described FPGA codec to read in dual port RAM.
Described device data is delivered to described FPGA codec from governor circuit CPU and is converted into Manchester signal, converts differential signal into after isolating transformer sends on the MVB bus through the MVB bus driver; Described MVB bus driver will be converted into the UART signal through the differential signal on the MVB bus that described isolating transformer transmits and be sent to and be sent to governor circuit CPU after the FPGA codec carries out encoding and decoding.
The utility model adopts modularized design; Its interface meets MVB and two kinds of train bus-line interface standards of CANOPEN of IEC61375-1:2007, ISO11898 and CIA DS-301 Ver.4.02 standard; Have MVB and CANOPEN communication function simultaneously; Novel in design, be convenient to install, have very high promotional value in railway, subway and light rail field.Its beneficial effect is following:
(1) the utility model meets IEC61375-1:2007, ISO11898 and CIA DS-301 Ver.4.02 standard, has filled up domestic blank in this technical field.
(2) the utility model has adopted modularized design, reduced the complexity of product assembling, has reduced the probability that manual operation causes fault.
(3) the utility model has passed through the routine test of MVB and CANOPEN, and has passed through the interface uniformity test with external like product.
(4) the utility model has been expanded the compatibility issue of network control system, for different manufacturers, distinct interface provide a solution easily.
Description of drawings
The structural representation of the MVB-CANOPEN gateway that Fig. 1 provides for the utility model embodiment;
The structural representation of the governor circuit that Fig. 2 provides for the utility model embodiment;
The structural representation of the MVB interface circuit that Fig. 3 provides for the utility model embodiment;
The structural representation of the CANOPEN interface circuit that Fig. 4 provides for the utility model embodiment;
The network topological diagram that Fig. 5 provides for the utility model embodiment.
The MVB-CANOPEN gateway that Fig. 6 provides for the utility model embodiment is sent to the structural representation of governor circuit after with the packet parsing on the MVB bus through the MVB interface circuit.
Embodiment
For the purpose, technical scheme and the advantage that make the utility model is clearer,, the utility model is further elaborated below in conjunction with accompanying drawing.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Referring to Fig. 1, shown in 2; A kind of MVB-CANOPEN gateway based on ARM7 nuclear microprocessor, MVB interface circuit and the CANOPEN interface circuit that comprise governor circuit, is connected with described governor circuit respectively and be the power circuit that described governor circuit, MVB interface circuit and CANOPEN interface circuit provide operating voltage; Described governor circuit comprises CPU, the FPGA codec that is connected with described CPU, RS232 protocol controller, USB interface and the RS232 interface that is connected with described RS232 protocol controller; Described CPU is the microprocessor of ARM7 nuclear, and described MVB interface circuit is connected with described FPGA codec, and described CANOPEN interface circuit is connected with described CPU.
Described MVB interface circuit is responsible for the input and output of data on the MVB bus; Described CANOPEN interface circuit is responsible for the input and output of data on the CANOPEN bus; Described governor circuit is the core of whole M VB-CANOPEN gateway; Be responsible for the parsing of all upper layer communication agreements, comprise encoding and decoding, CANOPEN protocol encoding and decoding, protocol function conversion, the function that realizes MVB bus master and the processing of data of being responsible for the MVB agreement; The CPU of governor circuit receives the data from CANOPEN interface circuit and MVB interface circuit, and data are handled, and also will resolve and handle the sync message of MVB bus and CANOPEN bus simultaneously.
The CPU of governor circuit is connected with the MVB interface circuit through connected described FPGA codec, realizes the transmitting-receiving of data on the MVB bus and the work of encoding and decoding; CPU is connected with the CANOPEN interface circuit, realizes that the application layer of data on the CANOPEN bus is resolved, and resolves and receives and dispatches for data on the bus and heartbeat message; MVB data that collect and CANOPEN data are all exportable through RS232 interface and USB interface, and application program also can be downloaded through the RS232 interface.
Carry out exchanges data through dual port RAM between FPGA codec and the CPU, prevent loss of data.The FPGA codec can supply CPU to read with being stored in after the data decode in the dual port RAM; The storage that CPU will send supplies the FPGA codec to read in dual port RAM.The transmission of prime frame is independently accomplished by the FPGA codec.
Referring to Fig. 3, described MVB interface circuit comprises the MVB interface that MVB bus driver, the isolating transformer that is connected with said MVB bus driver and described isolating transformer connect; Described MVB interface circuit is connected with the FPGA codec of described governor circuit through described MVB bus driver.
Device data is converted into Manchester signal after governor circuit CPU is sent to the FPGA codec encodes, send on the MVB bus through described MVB interface through MVB bus driver and isolating transformer; Described MVB interface circuit can receive the data on the MVB bus equally, through delivering to the decoding of FPGA codec behind MVB interface, isolating transformer and the MVB bus driver, in the CPU of governor circuit, handles.Equally can be through governor circuit through the MVB prime frame of MVB interface circuit transmission.
Described device data is delivered to described FPGA codec from governor circuit CPU and is converted into Manchester signal, converts differential signal into after isolating transformer sends on the MVB bus through the MVB bus driver; Described MVB bus driver will be converted into the UART signal through the differential signal on the MVB bus that described isolating transformer transmits and be sent to and be sent to governor circuit CPU after the FPGA codec carries out encoding and decoding.
Referring to Fig. 4, described CANOPEN interface circuit comprises CANOPEN isolation protocol control module, conjugation inductance and the protection device that connects successively; Described CANOPEN interface circuit is connected with described CPU through described CANOPEN isolation protocol control module.
Device data is sent to CANOPEN isolation protocol module from governor circuit CPU, through being sent to behind the conjugation inductor filter on the CANOPEN bus; Described CANOPEN interface circuit can receive the data on the CANOPEN bus equally, and behind the conjugation inductor filter, the CPU that delivers to governor circuit through CANOPEN isolation protocol module handles data; All CANOPEN application layer protocols are all resolved in the CPU of governor circuit; When the protection device is implemented in the disturbed generation of CANOPEN bus fluctuation, absorb the higher pulse of voltage.
Among the utility model embodiment; Wherein the CPU of governor circuit adopts the LPC2378 of NXP, the EP1K50TC144-3N that the FPGA codec adopts ALTERA, the SP202EEN that the RS232 protocol controller adopts SIPEX, and the MVB bus driver adopts the MA3292ESD of MAXIM, the T60403-Y4021-X123 that isolating transformer adopts VAC, the CTM1050T that CANOPEN isolation protocol control module adopts ZLG, B82793, the protection device that the conjugation inductance adopts EPCOS to adopt PESD5V0L2BT.
The gateway all hardware is responsible for the parsing of MVB, CANOPEN, RS232 and USB physical layer and link layer data, the data after resolving is sent to the CPU or the FPGA codec of governor circuit.The all software functions of module all are in governor circuit CPU and FPGA codec, to resolve, and the message after resolving is sent to interface circuit.CANOPEN isolation protocol control module is the core of CANOPEN interface circuit, is used to realize CANOPEN circuit physical layer interface and electrical isolation, when receiving new data, is sent to CPU and causes interruption.The MVB bus driver is the core of MVB interface circuit, and it is converted into the UART signal with the differential signal on the MVB bus and is sent to FPGA and carries out encoding and decoding.
Referring to Fig. 5, described power circuit comprises power module, the choke that is connected with described power module respectively, high pressure ceramic disc capacitor, TVS device; Power circuit is core with the power module, for governor circuit, MVB interface circuit and CANOPEN interface circuit provide 3.3V, 2.5V, 1.8V voltage.
The utility model MVB-CANOPEN gateway is furnished with the 24V power interface, and EMC satisfies TB3021-2001 rolling stock electronic installation and EN50155 standard.Power module adopts the VRA2405D-10W of homemade Jin Shengyang company; The 24V externally fed is converted into 5V, transfers 5V voltage to 3.3V, 2.5V and 1.8V voltage through AMS1117-3.3, AMS1117-2.5 and AMS1117-1.8 and supply governor circuit, MVB interface circuit and CANOPEN interface circuit to use.
The described MVB-CANOPEN gateway of the utility model embodiment can be connected with the CANOPEN network with the MVB on the train, realizes the conversion of two kinds of heterogeneous networks communication protocols.The equipment of every kind of different agreement interface all needs a this MVB-CANOPEN gateway.
Referring to shown in Figure 6; The MVB-CANOPEN gateway is sent to governor circuit through the MVB interface circuit after with the packet parsing on the MVB bus; Governor circuit is handled to this message, and the message that the CANOPEN circuit is needed is sent on the CANOPEN bus through the CANOPEN interface circuit.Equally, also in governor circuit, handle to the message on the CANOPEN bus, the effective message after the processing is sent on the MVB bus.If train bus-line is the CANOPEN network, the MVB-CANOPEN gateway can also be as MVB bus master, carries out MVB with the equipment of needs conversion such as traction electric machine, broadcast system etc. and communicates by letter, thereby realize the compatibility of multiple bus.
The utility model meets MVB and two kinds of train bus-lines of CANOPEN of IEC61375-1:2007, ISO13239-2002 standard; Have MVB and CANOPEN communication function simultaneously; Can realize the conversion of MVB and two kinds of train bus-line communication protocols of CANOPEN, be widely used in the skimble-scamble industrial control fields of train bus-line such as subway, light rail and railway locomotive.
More than the disclosed specific embodiment that is merely this patent, but this patent is not limited thereto, for the person of ordinary skill of the art, under the prerequisite that does not break away from the utility model principle, the distortion of making should be regarded as belonging to the utility model protection range.
Claims (5)
1. MVB-CANOPEN gateway based on ARM7 nuclear microprocessor; It is characterized in that MVB interface circuit that comprises governor circuit, is connected respectively and communicates by letter and CANOPEN interface circuit and the power circuit that operating voltage is provided for described governor circuit, MVB interface circuit and CANOPEN interface circuit with described governor circuit; Described governor circuit comprises CPU, the FPGA codec that is connected with described CPU, RS232 protocol controller, USB interface and the RS232 interface that is connected with described RS232 protocol controller; Described MVB interface circuit is connected with described FPGA codec, and described CANOPEN interface circuit is connected with described CPU.
2. the MVB-CANOPEN gateway based on ARM7 nuclear microprocessor according to claim 1 is characterized in that described MVB interface circuit comprises MVB bus driver, the isolating transformer that is connected with said MVB bus driver; Described MVB interface circuit is connected with described FPGA codec through described MVB bus driver; Device data sends on the MVB bus through MVB bus driver and isolating transformer after governor circuit CPU delivers to the FPGA codec encodes; Described MVB interface circuit receives the data on the MVB bus equally, delivers to the CPU that delivers to governor circuit after the FPGA codec is decoded through isolating transformer and MVB bus driver.
3. the MVB-CANOPEN gateway based on ARM7 nuclear microprocessor according to claim 1 is characterized in that, described CANOPEN interface circuit comprises CANOPEN isolation protocol control module, conjugation inductance and the protection device that connects successively; Described CANOPEN interface circuit is connected with described CPU through described CANOPEN isolation protocol control module; Device data is sent to CANOPEN isolation protocol control module from governor circuit CPU, through being sent to behind the conjugation inductor filter on the CANOPEN bus; Described CANOPEN interface circuit receives the data on the CANOPEN bus equally, behind the conjugation inductance, delivers to the CPU of governor circuit through CANOPEN isolation protocol control module.
4. the MVB-CANOPEN gateway based on ARM7 nuclear microprocessor according to claim 1 is characterized in that, carries out exchanges data through dual port RAM between described FPGA codec and the CPU; Described FPGA codec will be stored in after the data decode that described MVB interface circuit transmits and supply CPU to read in the dual port RAM; The storage that CPU will be sent to described MVB interface circuit supplies described FPGA codec to read in dual port RAM.
5. the MVB-CANOPEN gateway based on ARM7 nuclear microprocessor according to claim 2; It is characterized in that; Described device data is delivered to described FPGA codec from governor circuit CPU and is converted into Manchester signal, converts differential signal into after isolating transformer sends on the MVB bus through the MVB bus driver; Described MVB bus driver will be converted into the UART signal through the differential signal on the MVB bus that described isolating transformer transmits and be sent to and be sent to governor circuit CPU after the FPGA codec carries out encoding and decoding.
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| CN2011200917008U CN202183782U (en) | 2011-03-31 | 2011-03-31 | MVB (multifunction vehicle bus)-CANOPEN gateway based on ARM seven nuclear microprocessor |
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| CN2011200917008U CN202183782U (en) | 2011-03-31 | 2011-03-31 | MVB (multifunction vehicle bus)-CANOPEN gateway based on ARM seven nuclear microprocessor |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103685003A (en) * | 2013-11-27 | 2014-03-26 | 唐山轨道客车有限责任公司 | Gateway equipment for train |
| CN103997455A (en) * | 2014-05-30 | 2014-08-20 | 南车南京浦镇车辆有限公司 | Method for controlling multi-protocol converting communication gateway of locomotives |
| CN104144026A (en) * | 2013-05-06 | 2014-11-12 | 中国科学院软件研究所 | MVB network card module based on embedded processor and data transmission method |
| CN104850097A (en) * | 2015-03-31 | 2015-08-19 | 青岛四方车辆研究所有限公司 | Current loop gateway suitable for monorail car traction inverter and data transmission method |
| CN105785833A (en) * | 2014-12-17 | 2016-07-20 | 中车大连电力牵引研发中心有限公司 | Bus analysis apparatus and system for railway vehicles |
| CN112684780A (en) * | 2021-01-29 | 2021-04-20 | 郑州铁路职业技术学院 | Control panel interface assembly for railway locomotive |
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2011
- 2011-03-31 CN CN2011200917008U patent/CN202183782U/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104144026A (en) * | 2013-05-06 | 2014-11-12 | 中国科学院软件研究所 | MVB network card module based on embedded processor and data transmission method |
| CN103685003A (en) * | 2013-11-27 | 2014-03-26 | 唐山轨道客车有限责任公司 | Gateway equipment for train |
| CN103997455A (en) * | 2014-05-30 | 2014-08-20 | 南车南京浦镇车辆有限公司 | Method for controlling multi-protocol converting communication gateway of locomotives |
| CN103997455B (en) * | 2014-05-30 | 2017-05-17 | 中车南京浦镇车辆有限公司 | Method for controlling multi-protocol converting communication gateway of locomotives |
| CN105785833A (en) * | 2014-12-17 | 2016-07-20 | 中车大连电力牵引研发中心有限公司 | Bus analysis apparatus and system for railway vehicles |
| CN104850097A (en) * | 2015-03-31 | 2015-08-19 | 青岛四方车辆研究所有限公司 | Current loop gateway suitable for monorail car traction inverter and data transmission method |
| CN104850097B (en) * | 2015-03-31 | 2017-06-16 | 中车青岛四方车辆研究所有限公司 | Suitable for the data transmission method of the electric current loop gateway of gyrocar traction invertor |
| CN112684780A (en) * | 2021-01-29 | 2021-04-20 | 郑州铁路职业技术学院 | Control panel interface assembly for railway locomotive |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120404 Termination date: 20180331 |
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| CF01 | Termination of patent right due to non-payment of annual fee |