CN204228884U - A kind of Distributed power net fault recovery controller - Google Patents
A kind of Distributed power net fault recovery controller Download PDFInfo
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- CN204228884U CN204228884U CN201420522717.8U CN201420522717U CN204228884U CN 204228884 U CN204228884 U CN 204228884U CN 201420522717 U CN201420522717 U CN 201420522717U CN 204228884 U CN204228884 U CN 204228884U
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Abstract
The utility model relates to a kind of Distributed power net fault recovery controller.This Distributed power net fault recovery controller comprises dsp chip, power supply unit, communication unit, host computer, storage unit, AD processing unit and reset circuit; Wherein, power supply unit is connected with dsp chip, is connected with communication unit; Communication unit is connected with dsp chip, is connected with host computer; Host computer is connected with communication unit, is connected with power supply unit; Storage unit is connected with dsp chip; AD processing unit is connected with dsp chip, is connected with host computer; Reset circuit is connected with dsp chip, is connected with power supply unit.The beneficial effects of the utility model are: 1. plant factor is high, and distributed modular accesses, compatible good; 2. software is with strong points and execution efficiency is high; 3. at a high speed, processing capability in real time is strong for processor calculating; 4. peripheral outer device structure is simple, and technology maturation is stablized, and is easy to realize and control.
Description
Technical field
The utility model relates to power distribution network and runs control field, especially a kind of Distributed power net fault recovery controller and method of work thereof.
Background technology
Need efficiently to recover fault fast after the more and more high factor of the requirement of complicated and user to the quality of power supply of current electric network composition and scale makes grid collapses, reduce power off time and scope, and then reduce loss of outage.Along with data acquisition in electrical power distribution automatization system DAS (Distribution Automation System) and monitoring function SCADA (the Supervisory Control And Data Acquisition) application in operation of power networks, the functions such as its monitoring, state instruction, warning, data telemetry can carry out fast failure location and recovery operation under power grid accident state yardman's Real-Time Switch information and protection information etc. then.At present, the functional module that electrical power distribution automatization system realizes fault recovery towards whole power distribution network realizes not yet completely, along with power distribution network node increase, popularization, structure become increasingly complex, need during fault handling to consider multiple constraint condition and different recovery target, the information that now dispatcher is difficult to provide according to SCADA in is in short-term carried out analyzing and processing and makes rational recovery scheme, and the time of now manual analysis process and ability produce larger limitation.
At present; distributed type open and the Object-oriented Technique of electrical power distribution automatization system are comparatively fast developed; measuring and controlling equipment in electrical network and primary equipment be can be used as expanding element and are connected with system by network interface, and then realize connecing a series of intelligent functions such as the protection entering object, monitoring, charging, operation, lockings.Transformer station as the power center of zone user, upper level power supply by transformer station by many feeder lines under it by feeding electric energy to user side.Distribution network failure mostly occurs region, user side between transformer station and user, transformer station and power supply area thereof are considered as minimum autonomous system and are solved by the process of local fault recovery device, this distributing treatment in situ mode can reduce centralized data processing amount and the difficulty of electrical power distribution automatization system greatly.Therefore, how in conjunction with prior art and appointed condition, study a kind of reliable and with the Distributed power net fault recovery control device of power distribution automation platform compatibility, to improve distribution network failure processing power and operational efficiency, reduce dispatcher's workload and decision-making assistant information is accurately and timely provided, becoming the current demand of power distribution network traffic control.
Utility model content
The purpose of this utility model is to provide a kind of Distributed power net fault recovery controller and method of work thereof, it is for the deficiency of existing distribution network failure recovery operation, after can overcoming distribution network failure, dispatcher manually solves the larger circumscribed problem of recovery scheme existence according to the data that SCADA system provides, be considered as minimum system by DAS platform and by transformer station and power supply area thereof and adopt distributing treatment in situ scheme, recovery scheme can be provided fast after fault occurs, that to have dirigibility good, the Distributed power net fault recovery controller that reliability is high and applied widely, the method of work that operational efficiency is high.
A kind of Distributed power net fault recovery controller, is characterized in that it comprises DSP (DigitalSignal Processor) chip, power supply unit, communication unit, host computer, storage unit, AD processing unit and reset circuit; Wherein, described power supply unit and dsp chip are unidirectional connection, are unidirectional connection with communication unit; Described communication unit and dsp chip in being bi-directionally connected, with host computer in being bi-directionally connected; Described host computer and communication unit, in being bi-directionally connected, are unidirectional connection with power supply unit; Described storage unit and dsp chip are in being bi-directionally connected; Described AD processing unit and dsp chip, in being bi-directionally connected, are unidirectional connection with host computer; Described reset circuit and dsp chip, in being bi-directionally connected, are unidirectional connection with power supply unit.
Described dsp chip is TI company model is the low-power consumption of TMS320C5402, high performance fixed-point DSP chip, adopt and revise Harvard structure, instruction cycle is 10ns, arithmetic capability is 100MIPS, there is the ALU of 1 40 inside, the totalizer of 2 40, 2 40 totalizers, the barrel shifter of the multiplier of 1 17 × 17 and 1 40, there are 4 internal buss and 2 address generators, be integrated with Viterbi accelerator, operating voltage is 3.3/1.8V, ram in slice (random accessmemory) is 16KB, in sheet, ROM (read only memory) is 4KB, and 2 automatic buffer serial port BSP (auto-Buffered Serial Port) and 1 HPI communicated with ppu (Host Port Interface) interface are provided.
Described power supply unit is made up of power input interface circuit, power output interface circuit and power supply control chip, and its operating voltage is 5V, and output voltage is 3.3V and 1.8V; Described power input interface circuit is connected with host computer 5V power output interface; The CV of the 1.8V delivery outlet dsp chip of described power output interface circuit
dDinterface is connected; The 3.3V delivery outlet of described power output interface circuit respectively with the DV of dsp chip
dDthe MAX3111 power interface of interface, communication unit is connected with the power end of reset circuit.
Described power input interface electricity routing resistance R, R1, R2 and electric capacity C, C1, C2 are formed; Wherein, 5V power end is through resistance R ground connection; C, C1 termination 5V power input in parallel is connected with the 1IN (pin 5) of TPS73HD318, other end ground connection; Resistance R1 one end is connected with the 1EN (pin 4) of TPS73HD318, other end ground connection; Electric capacity C2 one end is connected with the 2IN (pin 11) of TPS73HD318 with 5V power input, other end ground connection; Resistance R2 mono-section is connected with the 2EN (pin 10) of TPS73HD318, other end ground connection.
Described power output interface electricity routing capacitance C3, C4, C5, C6 are formed; Wherein, electric capacity C3, C4 one end in parallel is connected with 1.8V power output end with the 1OUT (pin 23) of TPS73HD318, other end ground connection; Electric capacity C5, C6 one end in parallel is connected with 3.3V power output end with the 2OUT (pin 17) of TPS73HD318, other end ground connection.
Described power supply control chip is TI company model is TPS73HD318 dual-output power supply circuit; Wherein, 1IN (pin 5) is connected with C1 after being connected with 1IN (pin 6); 2IN (pin 11) is connected with C2 after being connected with 2IN (pin 12); 1GND, 1GND, 1FB/SENSE be ground connection respectively; 1OUT (pin 23) is connected with C3 after being connected with 1OUT (pin 24); 2OUT (pin 17), 2OUT (pin 18) are connected with C5 after being connected with 2SENSE;
The general serial asynchronism transceiver of described communication unit to be MAXIM company model be MAX3111; Wherein, VCC and the output voltage of power supply unit are that 3.3V power output interface circuit is connected; T1IN and TX is connected; R1OUT and RX is connected; DIN, DOUT, SCLK, CS, IRQ are connected with BDX, BDR, BCLKX, BFSX, INT of TMS320VC5402 respectively; T1OUT with R1IN is connected with host computer I/O interface; X1 and X2 crystal oscillator in parallel; X1 is through electric capacity C7 ground connection; X2 is through electric capacity C8 ground connection.
Described host computer is integrated automation of transformation stations platform, including but not limited to 5V power output interface, I/O interface and 8 electric distribution network data collection modules; Described 5V power output interface is connected with the power input interface circuit of power supply unit; T1OUT with R1IN of the MAX3111 of described I/O interface and commmunication unit is connected.
Described electric distribution network data collection module is made up of input end, output terminal, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, electric capacity C8, electric capacity C9, operational amplifier OM, diode VD1, diode VD2 summation current transformer CT, its input end gathers the failure message in transformer station or power distribution network, and its output terminal is connected with the analog input interface of AD conversion chip; Wherein, the two ends of Current Transmit are connected with resistance R5 respectively after R6 with R7 parallel connection; Diode VD1 and VD2 connects ground connection; Electric capacity C9 one end is connected with resistance R5, other end ground connection; The positive input terminal of operational amplifier OM is connected with resistance R5, and negative input end to be connected with its output terminal through resistance R8 and to form feedback element, and output terminal is connected with output terminal through resistance R3; One end ground connection of electric capacity C8, the other end is connected with the output terminal of operational amplifier OM; Resistance R4 one end is connected with output terminal, other end ground connection.
Described storage unit is made up of Flash (Flash Electrically Erasable ProgrammableRead-Only Memory, flash memory) and SRAM (Static Random Access Memory, static RAM); Wherein said Flash and SRAM respectively with dsp chip in being bi-directionally connected.
The two-forty flash memory of described Flash to be atmel corp's model be 1M (64K word × 16) capacity of AT29LV1024; Wherein, I/O15 ~ 0 of DB and the AT29LV1024 of TMS320C5402 connects in two-phase; The AB of TMS320C5402,
respectively with A15 ~ 0 of AT29LV1024,
in unidirectional connection; AT29LV1024's
ground connection.
The two-forty SRAM of described SRAM to be ISSI company model be 1M (64K word × 16) capacity of IS61LV6416; Wherein, I/O15 ~ 0 of DB and the IS61LV6416 of TMS320C5402 connects in two-phase; The AB of TMS320C5402,
respectively with A15 ~ 0 of IS61LV6416,
in unidirectional connection; AT29LV1024's
ground connection.
Described AD processing unit by or gate logic and AD conversion chip form; The 8 passage 16 bit parallel synchronized sampling AD conversion chip of described AD conversion chip to be TI company model be ADS8568; Wherein, 8 road analog input ends of described AD conversion chip are connected with the electric distribution network data collection module of host computer; The A10 of TMS320C5402 and
connect respectively or gate logic input end after export termination ADS8568's
r/W, the XF of TMS320C5402,
with ADS8568's
unidirectional connection; D9 ~ the D0 of D9 ~ D0 and the ADS8568 of TMS320C5402 is in being bi-directionally connected; REEM, CSTART ground connection of ADS8568.
Described reset circuit is made up of trigger switch SW, resistance R9, resistance R10 and electric capacity C10; Wherein, trigger switch SW goes out to make a start and to be connected with the A16 of TMS320C5402, input end ground connection and being connected with R9 respectively; Resistance R10 and electric capacity C10 series connection ground connection; Resistance R9 meets the RS of TMS320C5402 after being connected with the common port of electric capacity C10 with resistance R10.
A method of work for Distributed power net fault recovery controller, is characterized in that comprising the following steps:
(1), after the start of distribution network failure recovery controller, the 5V Power convert of host computer becomes 1.8V and 3.3V to be that dsp chip and communication unit are powered by power supply unit;
(2) fault recovery control program is downloaded to the Flash of storage unit by host computer by the serial communication interface of communication unit;
(3) failure message of 8 electric distribution network data collection modules to transformer station and power distribution network of host computer is sampled, and failure message is delivered to SRAM through AD processing unit by analog input signal;
(4) dsp chip reads the failure message in SRAM, calls fault recovery control program and failure judgement type;
(5) according to fault type, dsp chip to be sent to host computer by the serial communication interface of communication unit and calls the request of data such as transformer station and power supply area power distribution network topological structure, Power Flow Information, on off state, and by the information temporary storage that receives to the SRAM of storage unit;
(6) electric network data in SRAM is called in by dsp chip, by calling the fault recovery scheme of the switching manipulation that the computing of fault recovery control program obtains, and keeps in Flash by recovery scheme;
(7) recovery scheme be temporarily stored in Flash is uploaded to host computer by communication unit, analyzes reference for dispatcher;
(8) when dsp chip detects that the operation of distribution network failure controller makes mistakes, send trigger pip to reset circuit, after restart controller, repeat step (1) ~ (7) work.
Transformer station in described step (3) and the failure message of power distribution network refer to transformer high-voltage side bus power supply monitoring information, running state of transformer monitoring information, transformer low voltage side bus power supply monitoring information, transformer station direct current system status monitoring information, transformer station's outlet status monitoring information, feeder line block switch monitoring information, on-load switch status monitoring information and circuit breaker position that 8 electric distribution network data collection modules gather respectively and malfunctioning monitoring information.
Fault recovery control program in described step (2) is the specific program of fault type for single transformer station and power supply area thereof and feature design, comprises the following steps:
Step 1, distribution network initialization after fault, forms all fault zones according to the situation of power distribution network after fault, and adds up responsible consumer load and the dead electricity total load of each fault zone, according to the system state after the result determination electric network fault of Load flow calculation;
Step 2, in all interconnection switches be connected with fault zone, if when there is the interconnection switch be connected with the former feed line of power supply in this fault zone, this interconnection switch that directly closes utilizes former feeder line to restore electricity, if there is not such interconnection switch, goes to step 3;
Step 3, fault zone is connected and the margin capacity interconnection switch that is greater than zero, if do not exceed voltage or current limit after Load flow calculation, realizes the power supply of fault zone, otherwise goes to step 4;
Step 4, excision inferior grade load, until voltage and current is not out-of-limit, exports recovery scheme.
The beneficial effects of the utility model are: 1. based on integrated automation of transformation stations platform development, effectively can utilize existing equipment, can realize distributed modular access, have good compatibility; 2. computer software programming combines with hardware support kit device, and software programming has stronger specific aim and easy-to-understand, and execution efficiency is high; 3. processor adopts high performance TMS320C5402DSP to realize high-speed computation, and processing capability in real time is strong; 4. peripheral outer device structure is simple, and technology maturation is stablized, and is easy to realize and control; 5. can according to fault type rapid solving recovery scheme after fault, realize localization and run and control, and provide reference for dispatcher, reduce power off time and loss.。
Accompanying drawing explanation
Fig. 1 is a kind of Distributed power net fault recovery controller architecture block diagram involved by the utility model.
Fig. 2 is the power supply unit structural drawing of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 3 is the communication unit structural drawing of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 4 is the host computer structural drawing of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 5 is electric distribution network data collection function structure chart in the host computer of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 6 is the memory cell structure block diagram of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 7 is Flash connection layout in the storage unit of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 8 is SRAM connection layout in the storage unit of a kind of Distributed power net fault recovery controller involved by the utility model.
Fig. 9 is the AD processing unit structural drawing of a kind of Distributed power net fault recovery controller involved by the utility model.
Figure 10 is the reset circuit figure of a kind of Distributed power net fault recovery controller involved by the utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is described in further detail.
A kind of Distributed power net fault recovery controller principle of work that the utility model relates to is: when power distribution network normally runs, the fault status information in the Flash of the regular reading cells of distribution network failure recovery controller.When power distribution network breaks down, corresponding failure message is uploaded to storage unit by electric distribution network data collection module.Dsp chip is by calling fault recovery control program failure judgement type, send to host computer and read the request of data such as transformer station and power supply area power distribution network topological structure, Power Flow Information, on off state, and its buffer memory is called to SRAM medium pending fault recovery control program.Distribution network failure recovers control program and carries out computing according to the logical algorithm preset to the power distribution network data in SRAM, solves and obtains fault recovery scheme and to be stored in Flash being uploaded to host computer confession dispatcher through communication unit simultaneously and analyzing reference.
Embodiment: a kind of Distributed power net fault recovery controller (see Fig. 1), is characterized in that it comprises DSP (Digital Signal Processor) chip, power supply unit, communication unit, host computer, storage unit, AD processing unit and reset circuit; Wherein, described power supply unit and dsp chip are unidirectional connection, are unidirectional connection with communication unit; Described communication unit and dsp chip in being bi-directionally connected, with host computer in being bi-directionally connected; Described host computer and communication unit, in being bi-directionally connected, are unidirectional connection with power supply unit; Described storage unit and dsp chip are in being bi-directionally connected; Described AD processing unit and dsp chip, in being bi-directionally connected, are unidirectional connection with host computer; Described reset circuit and dsp chip, in being bi-directionally connected, are unidirectional connection with power supply unit.
Described dsp chip is TI company model is the low-power consumption of TMS320C5402, high performance fixed-point DSP chip, adopt and revise Harvard structure, instruction cycle is 10ns, arithmetic capability is 100MIPS, there is the ALU of 1 40 inside, the totalizer of 2 40, 2 40 totalizers, the barrel shifter of the multiplier of 1 17 × 17 and 1 40, there are 4 internal buss and 2 address generators, be integrated with Viterbi accelerator, operating voltage is 3.3/1.8V, ram in slice (random accessmemory) is 16KB, in sheet, ROM (read only memory) is 4KB, and 2 automatic buffer serial port BSP (auto-Buffered Serial Port) and 1 HPI communicated with ppu (Host Port Interface) interface are provided.
Described power supply unit is made up of (see Fig. 2) power input interface circuit, power output interface circuit and power supply control chip, and its operating voltage is 5V, and output voltage is 3.3V and 1.8V; Described power input interface circuit is connected with host computer 5V power output interface; The CV of the 1.8V delivery outlet dsp chip of described power output interface circuit
dDinterface is connected; The 3.3V delivery outlet of described power output interface circuit respectively with the DV of dsp chip
dDthe MAX3111 power interface of interface, communication unit is connected with the power end of reset circuit.
Described power input interface circuit (see Fig. 2) is made up of resistance R, R1, R2 and electric capacity C, C1, C2; Wherein, 5V power end is through resistance R ground connection; C, C1 termination 5V power input in parallel is connected with the 1IN (pin 5) of TPS73HD318, other end ground connection; Resistance R1 one end is connected with the 1EN (pin 4) of TPS73HD318, other end ground connection; Electric capacity C2 one end is connected with the 2IN (pin 11) of TPS73HD318 with 5V power input, other end ground connection; Resistance R2 mono-section is connected with the 2EN (pin 10) of TPS73HD318, other end ground connection.
Described power output interface electricity routing capacitance C3, C4, C5, C6 are formed; Wherein, electric capacity C3, C4 one end in parallel is connected with 1.8V power output end with the 1OUT (pin 23) of TPS73HD318, other end ground connection; Electric capacity C5, C6 one end in parallel is connected with 3.3V power output end with the 2OUT (pin 17) of TPS73HD318, other end ground connection.
Described power supply control chip is TI company model is TPS73HD318 dual-output power supply circuit; Wherein, 1IN (pin 5) is connected with C1 after being connected with 1IN (pin 6); 2IN (pin 11) is connected with C2 after being connected with 2IN (pin 12); 1GND, 1GND, 1FB/SENSE be ground connection respectively; 1OUT (pin 23) is connected with C3 after being connected with 1OUT (pin 24); 2OUT (pin 17), 2OUT (pin 18) are connected with C5 after being connected with 2SENSE;
The general serial asynchronism transceiver of described communication unit (see Fig. 3) to be MAXIM company model be MAX3111; Wherein, VCC and the output voltage of power supply unit are that 3.3V power output interface circuit is connected; T1IN and TX is connected; R1OUT and RX is connected; DIN, DOUT, SCLK, CS, IRQ are connected with BDX, BDR, BCLKX, BFSX, INT of TMS320VC5402 respectively; T1OUT with R1IN is connected with host computer I/O interface; X1 and X2 crystal oscillator in parallel; X1 is through electric capacity C7 ground connection; X2 is through electric capacity C8 ground connection.
Described host computer (see Fig. 4) is integrated automation of transformation stations platform, including but not limited to 5V power output interface, I/O interface and 8 electric distribution network data collection modules; Described 5V power output interface is connected with the power input interface circuit of power supply unit; T1OUT with R1IN of the MAX3111 of described I/O interface and commmunication unit is connected.
Described electric distribution network data collection module (see Fig. 5) is made up of input end, output terminal, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, electric capacity C8, electric capacity C9, operational amplifier OM, diode VD1, diode VD2 summation current transformer CT, its input end gathers the failure message in transformer station or power distribution network, and its output terminal is connected with the analog input interface of AD conversion chip; Wherein, the two ends of Current Transmit are connected with resistance R5 respectively after R6 with R7 parallel connection; Diode VD1 and VD2 connects ground connection; Electric capacity C9 one end is connected with resistance R5, other end ground connection; The positive input terminal of operational amplifier OM is connected with resistance R5, and negative input end to be connected with its output terminal through resistance R8 and to form feedback element, and output terminal is connected with output terminal through resistance R3; One end ground connection of electric capacity C8, the other end is connected with the output terminal of operational amplifier OM; Resistance R4 one end is connected with output terminal, other end ground connection.
Described storage unit (see Fig. 6) is by Flash (Flash Electrically Erasable ProgrammableRead-Only Memory, flash memory) and SRAM (Static Random Access Memory, static RAM) formation; Wherein said Flash and SRAM respectively with dsp chip in being bi-directionally connected.
The two-forty flash memory of described Flash (see Fig. 7) to be atmel corp's model be 1M (64K word × 16) capacity of AT29LV1024; Wherein, I/O15 ~ 0 of DB and the AT29LV1024 of TMS320C5402 connects in two-phase; The AB of TMS320C5402,
respectively with A15 ~ 0 of AT29LV1024,
in unidirectional connection; AT29LV1024's
ground connection.
The two-forty SRAM of described SRAM (see Fig. 8) to be ISSI company model be 1M (64K word × 16) capacity of IS61LV6416; Wherein, I/O15 ~ 0 of DB and the IS 61LV6416 of TMS320C5402 connects in two-phase; The AB of TMS320C5402,
respectively with A15 ~ 0 of IS61LV6416,
in unidirectional connection; AT29LV1024's
ground connection.
Described AD processing unit (see Fig. 9) by or gate logic and AD conversion chip form; The 8 passage 16 bit parallel synchronized sampling AD conversion chip of described AD conversion chip to be TI company model be ADS8568; Wherein, 8 road analog input ends of described AD conversion chip are connected with the electric distribution network data collection module of host computer; The A10 of TMS320C5402 and
connect respectively or gate logic input end after export termination ADS8568's
r/W, the XF of TMS320C5402,
with ADS8568's
unidirectional connection; D9 ~ the D0 of D9 ~ D0 and the ADS8568 of TMS320C5402 is in being bi-directionally connected; REEM, CSTART ground connection of ADS8568.
Described reset circuit (see Figure 10) is made up of trigger switch SW, resistance R9, resistance R10 and electric capacity C10; Wherein, trigger switch SW goes out to make a start and to be connected with the A16 of TMS320C5402, input end ground connection and being connected with R9 respectively; Resistance R10 and electric capacity C10 series connection ground connection; Resistance R9 meets the RS of TMS320C5402 after being connected with the common port of electric capacity C10 with resistance R10.
The utility model provides a kind of method of work of Distributed power net fault recovery controller, comprises the following steps:
(1), after the start of distribution network failure recovery controller, the 5V Power convert of host computer becomes 1.8V and 3.3V to be that dsp chip and communication unit are powered by power supply unit;
(2) fault recovery control program is downloaded to the Flash of storage unit by host computer by the serial communication interface of communication unit;
(3) failure message of 8 electric distribution network data collection modules to transformer station and power distribution network of host computer is sampled, and failure message is delivered to SRAM through AD processing unit by analog input signal;
(4) dsp chip reads the failure message in SRAM, calls fault recovery control program and failure judgement type;
(5) according to fault type, dsp chip to be sent to host computer by the serial communication interface of communication unit and calls the request of data such as transformer station and power supply area power distribution network topological structure, Power Flow Information, on off state, and by the information temporary storage that receives to the SRAM of storage unit;
(6) electric network data in SRAM is called in by dsp chip, by calling the fault recovery scheme of the switching manipulation that the computing of fault recovery control program obtains, and keeps in Flash by recovery scheme;
(7) recovery scheme be temporarily stored in Flash is uploaded to host computer by communication unit, analyzes reference for dispatcher; Recovery controller can provide multiple recovery scheme for dispatcher and analyze reference, but has in the end most and select a kind of scheme to recover by dispatcher, is performed according to recovery scheme instruction by automation equipment
(8) when dsp chip detects that the operation of distribution network failure controller makes mistakes, send trigger pip to reset circuit, after restart controller, repeat step (1) ~ (7) work.
Transformer station in described step (3) and the failure message of power distribution network refer to transformer high-voltage side bus power supply monitoring information, running state of transformer monitoring information, transformer low voltage side bus power supply monitoring information, transformer station direct current system status monitoring information, transformer station's outlet status monitoring information, feeder line block switch monitoring information, on-load switch status monitoring information and circuit breaker position that 8 electric distribution network data collection modules gather respectively and malfunctioning monitoring information.
Fault recovery control program in described step (2) is the specific program of fault type for single transformer station and power supply area thereof and feature design, comprises the following steps:
Step 1, distribution network initialization after fault, forms all fault zones according to the situation of power distribution network after fault, and adds up responsible consumer load and the dead electricity total load of each fault zone, according to the system state after the result determination electric network fault of Load flow calculation; Responsible consumer load and dead electricity total load can read from database; System state can comprise standby electricity source point capacity, standby power supply point voltage and current limit, interconnection switch break-make situation etc.;
Step 2, in all interconnection switches be connected with fault zone, if when there is the interconnection switch be connected with the former feed line of power supply in this fault zone, this interconnection switch that directly closes utilizes former feeder line to restore electricity, if there is not such interconnection switch, goes to step 3;
Step 3, fault zone is connected and the margin capacity interconnection switch that is greater than zero, if do not exceed voltage or current limit after Load flow calculation, realizes the power supply of fault zone, otherwise goes to step 4;
Step 4, excision inferior grade load, until voltage and current is not out-of-limit, exports recovery scheme.
Those skilled in the art, under the condition not departing from the spirit and scope of the present utility model that claims are determined, can also carry out various amendment to above content.Therefore scope of the present utility model is not limited in above explanation, but determined by the scope of claims.
Claims (16)
1. a Distributed power net fault recovery controller, is characterized in that, this Distributed power net fault recovery controller comprises dsp chip, power supply unit, communication unit, host computer, storage unit, AD processing unit and reset circuit; Wherein, described power supply unit and dsp chip are unidirectional connection, are unidirectional connection with communication unit; Described communication unit and dsp chip in being bi-directionally connected, with host computer in being bi-directionally connected; Described host computer and communication unit, in being bi-directionally connected, are unidirectional connection with power supply unit; Described storage unit and dsp chip are in being bi-directionally connected; Described AD processing unit and dsp chip, in being bi-directionally connected, are unidirectional connection with host computer; Described reset circuit and dsp chip, in being bi-directionally connected, are unidirectional connection with power supply unit.
2. Distributed power net fault recovery controller according to claim 1, is characterized in that, the chip of described dsp chip to be model be TMS320C5402.
3. a kind of Distributed power net fault recovery controller according to claim 1, it is characterized in that, described power supply unit comprises power input interface circuit, power output interface circuit and power supply control chip, and its operating voltage is 5V, and output voltage is 3.3V and 1.8V; Described power input interface circuit is connected with host computer 5V power output interface; The CV of the 1.8V delivery outlet dsp chip of described power output interface circuit
dDinterface is connected; The 3.3V delivery outlet of described power output interface circuit respectively with the DV of dsp chip
dDthe power interface of interface, communication unit is connected with the power end of reset circuit.
4. Distributed power net fault recovery controller according to claim 3, is characterized in that, described power input interface circuit comprises resistance R, resistance R1 and resistance R2 and electric capacity C, electric capacity C1 and electric capacity C2; Wherein, 5V power end is through resistance R ground connection; Electric capacity C is connected with the pin 1IN end of power supply control chip TPS73HD318 with an electric capacity C1 termination 5V power input in parallel, the other end ground connection of electric capacity C and electric capacity C1 parallel connection; Resistance R1 one end is held with the 1EN of TPS73HD318 and is connected, resistance R1 other end ground connection; Electric capacity C2 one end and 5V power input are held with the 2IN of TPS73HD318 and are connected, electric capacity C2 other end ground connection; Resistance R2 one end is held with the 2EN of TPS73HD318 and is connected, resistance R2 other end ground connection.
5. Distributed power net fault recovery controller according to claim 3, it is characterized in that, described power output interface circuit comprises electric capacity C3, electric capacity C4, electric capacity C5 and electric capacity C6; Wherein, electric capacity C3 and electric capacity C4 one end in parallel are held with the 1OUT of power supply control chip TPS73HD318 and are connected with 1.8V power output end, the other end ground connection of electric capacity C3 and electric capacity C4 parallel connection; Electric capacity C5 and electric capacity C6 one end in parallel are held with the 2OUT of TPS73HD318 and are connected with 3.3V power output end, the other end ground connection of electric capacity C5 and electric capacity C6 parallel connection.
6. Distributed power net fault recovery controller according to claim 3, is characterized in that, described power supply control chip is dual-output power supply circuit TPS73HD318; Wherein, 1IN end is connected with electric capacity C1 after being connected with 1IN end; 2IN end is connected with electric capacity C2 after being connected with 2IN end; 1GND end and 1FB/SENSE end ground connection respectively; 1OUT end is connected with electric capacity C3; 2OUT end is connected with electric capacity C5 after being connected with 2SENSE end.
7. Distributed power net fault recovery controller according to claim 1, is characterized in that, described communication unit is general serial asynchronism transceiver MAX3111; Wherein, VCC end is that 3.3V power output interface circuit is connected with the output voltage of power supply unit; T1IN end is held with TX and is connected; R1OUT end is held with RX and is connected; DIN end, DOUT end, SCLK end, CS hold, IRQ end is held with the BDX of dsp chip TMS320VC5402 respectively, BDR holds, BCLKX holds, BFSX holds, IN holds T-phase to connect; T1OUT end is connected with host computer I/O interface with R1IN end; X1 end and X2 hold crystal oscillator in parallel; X1 end is through electric capacity C7 ground connection; X2 end is through electric capacity C8 ground connection.
8. Distributed power net fault recovery controller according to claim 1, it is characterized in that, described host computer is integrated automation of transformation stations platform, comprises 5V power output interface, I/O interface and 8 electric distribution network data collection modules; Described 5V power output interface is connected with the power input interface circuit of power supply unit; The T1OUT end of described I/O interface and commmunication unit MAX3111 is connected with R1IN end.
9. Distributed power net fault recovery controller according to claim 8, it is characterized in that, described electric distribution network data collection module is made up of input end, output terminal, resistance R3, resistance R4, resistance R5, resistance R6, resistance R7, resistance R8, electric capacity C8, electric capacity C9, operational amplifier OM, diode VD1, diode VD2 summation current transformer CT, its input end gathers the failure message in transformer station or power distribution network, and its output terminal is connected with the analog input interface of AD conversion chip; Wherein, the two ends of Current Transmit are connected with resistance R5 after resistance R7 parallel connection through resistance R6 respectively; Diode VD1 connects with diode VD2 ground connection; Electric capacity C9 one end is connected with resistance R5, electric capacity C9 one end other end ground connection; The positive input terminal of operational amplifier OM is connected with resistance R5, and the negative input end of operational amplifier OM to be connected with its output terminal through resistance R8 and to form feedback element, and the output terminal of operational amplifier OM is connected with output terminal through resistance R3; One end ground connection of electric capacity C8, the electric capacity C8 other end is connected with the output terminal of operational amplifier OM; Resistance R4 one end is connected with output terminal, resistance R4 other end ground connection.
10. Distributed power net fault recovery controller according to claim 1, it is characterized in that, described storage unit comprises flash memory FLASH and static RAM SRAM; Wherein said flash memory and static RAM respectively with dsp chip in being bi-directionally connected.
11. Distributed power net fault recovery controllers according to claim 10, is characterized in that the model of described flash memory is the flash memory of AT29LV1024; Wherein, the DB end of dsp chip TMS320C5402 is that two-phase is connected with I/O15 ~ 0 interface of flash memory AT29LV1024; The AB of dsp chip TMS320C5402 holds,
end,
end respectively with A15 ~ 0 end of AT29LV1024,
end,
end is in unidirectional connection; AT29LV1024's
end,
end,
end ground connection.
12. Distributed power net fault recovery controllers according to claim 11, it is characterized in that, the model of described static RAM is IS61LV6416; Wherein, the DB end of dsp chip TMS320C5402 is that two-phase is connected with I/O15 ~ 0 interface of static RAM IS 61LV6416; The AB of dsp chip TMS320C5402 holds,
end,
end respectively with A15 ~ 0 end of static RAM IS61LV6416,
end,
end is in unidirectional connection; Flash memory AT29LV1024's
end,
end,
end ground connection.
13. Distributed power net fault recovery controllers according to claim 1, is characterized in that, described AD processing unit comprises or gate logic and AD conversion chip; The AD conversion chip of described AD conversion chip to be model be ADS8568; Wherein, 8 road analog input ends of described AD conversion chip are connected with the electric distribution network data collection module of host computer; Dsp chip TMS320C5402 A10 end and
end connect respectively or gate logic input end after export termination AD conversion chip ADS8568's
end; The R/W end of dsp chip TMS320C5402, XF hold,
end is with AD conversion chip ADS8568's
end,
end,
hold unidirectional connection; D9 ~ D0 end of dsp chip TMS320C5402 is held in being bi-directionally connected with the D9 ~ D0 of AD conversion chip ADS8568; The REEM end of AD conversion chip ADS8568, CSTART hold ground connection.
14. Distributed power net fault recovery controllers according to claim 1, it is characterized in that, described reset circuit comprises trigger switch SW, resistance R9, resistance R10 and electric capacity C10; Wherein, trigger switch SW trigger end is connected with the A16 of dsp chip TMS320C5402, and trigger switch SW input end is distinguished ground connection and is connected with resistance R9; Resistance R10 and electric capacity C10 series connection ground connection; Resistance R9 meets dsp chip TMS320C5402 RS after being connected with the common port of electric capacity C10 with resistance R10 holds.
15. Distributed power net fault recovery controllers according to claim 1, is characterized in that, described DSP is used for the failure message in reading cells, calls fault recovery control program and failure judgement type; According to fault type, sent the request of data calling transformer station and power supply area power distribution network topological structure thereof, Power Flow Information, on off state to host computer by the serial communication interface of communication unit, and by the information temporary storage that receives to storage unit; Electric network data in storage unit being called in, by calling the fault recovery scheme of the switching manipulation that the computing of fault recovery control program obtains, and recovery scheme being kept in storage unit.
16. Distributed power net fault recovery controllers according to claim 1, is characterized in that, temporary recovery scheme is in the memory unit uploaded to host computer by communication unit.
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| CN201420522717.8U CN204228884U (en) | 2014-09-11 | 2014-09-11 | A kind of Distributed power net fault recovery controller |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104316828A (en) * | 2014-09-11 | 2015-01-28 | 国家电网公司 | Distributed power grid fault recovery controller and working method thereof |
| CN109298283A (en) * | 2018-09-11 | 2019-02-01 | 国网山东省电力公司莱芜供电公司 | A kind of SCM Based distribution line failure detection device |
| CN111885431A (en) * | 2020-08-03 | 2020-11-03 | 北京环境特性研究所 | Communication control method and device |
-
2014
- 2014-09-11 CN CN201420522717.8U patent/CN204228884U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104316828A (en) * | 2014-09-11 | 2015-01-28 | 国家电网公司 | Distributed power grid fault recovery controller and working method thereof |
| CN109298283A (en) * | 2018-09-11 | 2019-02-01 | 国网山东省电力公司莱芜供电公司 | A kind of SCM Based distribution line failure detection device |
| CN111885431A (en) * | 2020-08-03 | 2020-11-03 | 北京环境特性研究所 | Communication control method and device |
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