CN204130548U - A kind of thin-film transistor, array base palte, display unit - Google Patents

A kind of thin-film transistor, array base palte, display unit Download PDF

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CN204130548U
CN204130548U CN201420631439.XU CN201420631439U CN204130548U CN 204130548 U CN204130548 U CN 204130548U CN 201420631439 U CN201420631439 U CN 201420631439U CN 204130548 U CN204130548 U CN 204130548U
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thin
film transistor
active layer
broken line
curve
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永山和由
宋松
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Abstract

The utility model embodiment provides a kind of thin-film transistor, array base palte, display unit, relate to flexible display technologies field, the probability that pattern fracture occurs this thin-film transistor when bending can be reduced, make display unit also can ensure normal display in the bent state.This thin-film transistor, comprises and is positioned at active layer, gate insulation layer, grid, interlayer insulating film and source electrode on flexible substrate and drain electrode successively; Described thin-film transistor also comprises at least 1 the first via hole and at least 1 second via hole of through described interlayer insulating film and described gate insulation layer respectively; Described source electrode, described drain electrode contact with described active layer respectively by described first via hole, described second via hole; Wherein, the figure of the figure of described active layer, the figure of described grid, the figure of described source electrode and described drain electrode is anti-fracture structure graph.The preparation of the thin-film transistor of pattern fracture during for reducing bending.

Description

A kind of thin-film transistor, array base palte, display unit
Technical field
The utility model relates to flexible display technologies field, particularly relates to a kind of thin-film transistor, array base palte, display unit.
Background technology
Along with the development of Display Technique, research staff have developed flexible display apparatus that is collapsible or that roll, compared with traditional rigidity display unit (being namely produced on the display unit on the inflexible base materials such as glass), flexible display apparatus has many advantages, as lightweight, volume is little, it is more convenient to carry; Higher resistance to impact and stronger anti-seismic performance.
As shown in Figure 1, the subject matter that flexible display apparatus faces at present is when bending, thin-film transistor (Thin Film Transistor in pixel cell or peripheral driving circuit, be called for short TFT) the 01 easy fracture that patterns occur in active layer 20, source electrode 61 and drain electrode 62 corresponding regions, cause the source electrode 61 of TFT and drain electrode 62 cannot conducting, corresponding signal voltage cannot be transferred in pixel electrode or corresponding circuit structure, to such an extent as to show bad.
Therefore, how making the pattern of TFT not easily fracture occur in the bent state is technological difficulties urgently to be resolved hurrily at present.
Utility model content
Embodiment of the present utility model provides a kind of thin-film transistor, array base palte, display unit, can reduce the probability that pattern fracture occurs this thin-film transistor when bending, make display unit also can ensure normal display in the bent state.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
On the one hand, the utility model embodiment provides a kind of thin-film transistor, comprises and is positioned at active layer, gate insulation layer, grid, interlayer insulating film and source electrode on flexible substrate and drain electrode successively; Described thin-film transistor also comprises at least 1 the first via hole and at least 1 second via hole of through described interlayer insulating film and described gate insulation layer respectively; Described source electrode, described drain electrode contact with described active layer respectively by described first via hole, described second via hole; Wherein, the figure of the figure of described active layer, the figure of described grid, the figure of described source electrode and described drain electrode is anti-fracture structure graph.
Optionally, described anti-fracture structure graph comprises at least one figure in annular, curve, broken line.
Preferably, described annular comprises square loop, rectangle ring, rhombus ring, circular rings.
Optionally, the figure of described active layer is made up of 1 described annular.
Optionally, the 8 font dicyclos that the figure of described active layer is made up of 2 described annulars are formed, or the figure of described active layer is made up of 1 described annular and the curve crossing with described annular or broken line.
Optionally, the figure of described grid is made up of curve or broken line or 1 described annular.
Optionally, the figure of described source electrode is made up of curve or broken line; The figure of described drain electrode is made up of curve or broken line.
Optionally, the figure of described active layer is formed by N number of unit figure is arranged in parallel; The 8 font dicyclos that described unit figure is made up of 2 described annulars are formed, or described unit figure is made up of 1 described annular and the curve crossing with described annular or broken line; The figure of described grid is arranged by N number of described endless parallel and forms, or the figure of described grid is made up of N section curve or N section broken line; The figure of described source electrode is made up of N section curve or N section broken line; The figure of described drain electrode is made up of N section curve or N section broken line; Wherein, N be more than or equal to 2 positive integer.
Preferred on the basis of the above, it is characterized in that, described active layer is low-temperature polysilicon silicon active layer.
On the other hand, the utility model embodiment still provides a kind of array base palte, comprises above-mentioned thin-film transistor.
One side, the utility model embodiment provide again a kind of display unit again, comprise above-mentioned array base palte.
In the utility model embodiment, because the figure of the figure of the figure of the described active layer in described thin-film transistor, described grid, the figure of described source electrode and described drain electrode is anti-fracture structure graph, such figure can make tension force part disperse when entirety bends, thus reduce the probability causing the figure in thin-film transistor to rupture when flexible display apparatus bends, ensure that flexible display apparatus can normally show.
Accompanying drawing explanation
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of thin-film transistor that Fig. 1 provides for prior art;
The structural representation one of a kind of thin-film transistor that Fig. 2 provides for the utility model embodiment;
Fig. 3 is the cross-sectional view along A-A ' direction in Fig. 2;
Structural representation two in a kind of thin-film transistor that Fig. 4 provides for the utility model embodiment;
Structural representation three in a kind of thin-film transistor that Fig. 5 provides for the utility model embodiment;
Structural representation four in a kind of thin-film transistor that Fig. 6 provides for the utility model embodiment;
Structural representation five in a kind of thin-film transistor that Fig. 7 provides for the utility model embodiment;
Structural representation six in a kind of thin-film transistor that Fig. 8 provides for the utility model embodiment;
Structural representation seven in a kind of thin-film transistor that Fig. 9 provides for the utility model embodiment.
Reference numeral:
01-thin-film transistor; 10-flexible substrate; 20-active layer; 20a-unit figure; 30-gate insulation layer; 40-grid; 50-interlayer insulating film; 61-source electrode; 62-drains; 71-first via hole; 72-second via hole.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
The utility model embodiment provides a kind of thin-film transistor 01, as Figure 2-3, comprise and be arranged in active layer 20, gate insulation layer 30 (Fig. 2 does not indicate), grid 40, interlayer insulating film 50 (Fig. 2 does not indicate) and source electrode 61 on flexible substrate 10 and drain electrode 62 successively; Described thin-film transistor 01 also comprises at least 1 the first via hole 71 and at least 1 the second via hole 72 of through described interlayer insulating film 50 and described gate insulation layer 30 respectively; Described source electrode 61, described drain electrode 62 contact with described active layer 20 respectively by described first via hole 71, described second via hole 72; Wherein, the figure of the figure of described active layer 20, the figure of described grid 40, the figure of described source electrode 61 and described drain electrode 62 is anti-fracture structure graph.
Here, Fig. 2 only illustrates one of shape of described anti-fracture structure graph, and described anti-fracture structure graph is not limited thereto, and not easily ruptures in the bent state as long as meet.
Wherein, above-mentioned flexible substrate 10 can be such as at the bottom of plastic, stainless steel lining, have the ultra-thin glass substrate of flexing, the paper substrate of modification and laminated film substrate etc.
In the utility model embodiment, because the figure of the figure of the described active layer 20 in described thin-film transistor, the figure of described grid 40, the figure of described source electrode 61 and described drain electrode 62 is anti-fracture structure graph, the pattern with such figure can make tension force part disperse when entirety bends, thus reduce the probability causing the figure in thin-film transistor to rupture when flexible display apparatus bends, ensure that flexible display apparatus can normally show.
On the basis of the above, in order to decompose better described thin-film transistor 01 completely time the pattern inner tensions that is subject to, described anti-fracture structure graph comprises at least one figure in annular, curve, broken line.
Herein, described annular is not limited to annulus, as long as the area part limited between a figure with larger area and another figure having compared with small size can be referred to as annular.
So, for above-mentioned this annular, or curve, or the figure of meander line structure, when bending, thin-film transistor with prior art is compared, although total bending force that described thin-film transistor 01 is subject to is the same, but due in the figure of this anti-fracture structure, stress point is far away compared with the position of the point of application, therefore at the figure of described active layer 20, the figure of described grid 40, the figure of described source electrode 61, and on stress point in the figure of described drain electrode 62, come from the component that folding force occurs just relatively to diminish, thus the figure that the inner tensions in described thin-film transistor 01 is just scattered in each anti-fracture structure is central, thus reduce the probability that fracture occurs corresponding patterned layer when bending, ensure that the normal display of flexible display apparatus.
Here, consider the simplicity of patterning processes and the Resisting fractre effect of figure, described annular comprises square loop, rectangle ring, rhombus ring, circular rings.
It should be noted that, under thin-film transistor conducting state, between source-drain electrode in opposed area, the overlapping region of active layer and grid is channel region, size due to channel region directly affects the electrical property under thin-film transistor conducting state, therefore, each above-mentioned figure should be tried one's best and be carried out combination overlap in a symmetrical manner.
Further, as shown in Figure 4, when considering that thin-film transistor is applied in the pixel cell of array base palte, because the size of pixel cell is usually less, in order to reduce the difficulty of patterning processes, optionally, the figure of described active layer 20 is made up of 1 described annular.
Certainly, as shown in Figure 5, the 8 font dicyclos that the figure of described active layer 20 also can be made up of 2 described annulars that Resisting fractre effect is more excellent are formed.Or as shown in Figure 6, the figure of described active layer 20 is made up of 1 described annular and the curve crossing with described annular or broken line.
Same, the figure of described grid 40 can be made up of curve or broken line or 1 described annular.The figure of described source electrode 61 can be made up of curve or broken line; The figure of described drain electrode 62 is made up of curve or broken line.
It should be noted that, Fig. 4-Fig. 6 only illustrates the possible compound mode between the figure of the figure of described active layer 20, the figure of described grid 40, the figure of described source electrode 61 and described drain electrode 62, the utility model embodiment is not limited thereto, the figure of each layer can also be other compound modes, does not repeat them here.
Further, when considering that thin-film transistor is applied in the drive circuit (as horizontal drive circuit GOA) of array base palte, thin-film transistor is generally needed to have larger channel region area in the on-state, to increase the electrical property of thin-film transistor, thus make the operation of drive circuit more quick, therefore, as shown in figs. 7 to 9, the figure of described active layer 20 is formed by N number of unit figure 20a is arranged in parallel; The 8 font dicyclos that described unit figure is made up of 2 described annulars are formed, or described unit figure 20a is made up of 1 described annular and the curve crossing with described annular or broken line; The figure of described grid 40 is arranged by N number of described endless parallel and forms, or the figure of described grid 40 is made up of N section curve or N section broken line; The figure of described source electrode 61 is made up of N section curve or N section broken line; The figure of described drain electrode 62 is made up of N section curve or N section broken line; Wherein, N be more than or equal to 2 positive integer.
So, because the figure of the figure of described active layer 20, the figure of described grid 40, the figure of described source electrode 61 and described drain electrode 62 is all form by the figure repeated is arranged in parallel, even if one curve or one section of broken line rupture when bending, the curve can also do not ruptured by other or broken line transmit corresponding signal.
It should be noted that, although do not illustrate described first via hole 71 and described second via hole 72 in Fig. 7-Fig. 9, but those skilled in the art are to be understood that, because the figure of the figure of above-mentioned described active layer 20, the figure of described source electrode 61 and described drain electrode 62 is be similar to figure that is netted or continuous print broken line, therefore, abundant with the contact of described active layer 20 in order to ensure described source electrode 61, described drain electrode 62, the quantity of described first via hole 71 and described second via hole 72 can be multiple, and its arrangement mode does not limit.
On the basis of the above, the described active layer 20 in described thin-film transistor 01 preferably has higher carrier mobility (100cm 2/ Vs) low temperature polycrystalline silicon (Low Temperature Poly-Silicon, be called for short LTPS) active layer, to make described thin-film transistor 01 entirety, there is more excellent electrical property.
The above-mentioned thin-film transistor that the utility model embodiment provides is intended to the shape by changing active layer, grid, source electrode and drain patterns, to make the pattern of flexible display apparatus when bending in thin-film transistor not easy fracture, the preparation method of above-mentioned thin-film transistor can continue to use prior art, the mask plate with different openings regional graphics only need be adopted to make active layer, grid, source electrode and drain electrode form corresponding figure, and preparation process repeats no more herein.
The utility model embodiment still provides a kind of array base palte, comprises above-mentioned thin-film transistor 01.
Further, the utility model embodiment still provides a kind of display unit, comprises above-mentioned array base palte.
Above-mentioned display unit is flexible display apparatus, such as, can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
It should be noted that, the utility model institute drawings attached is the simple schematic diagram of above-mentioned thin-film transistor, only for the clear this programme that describes embodies the structure relevant to inventive point, the structure irrelevant with inventive point for other is existing structure, in the accompanying drawings not embodiment or only realizational portion.
The above; be only embodiment of the present utility model; but protection range of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; change can be expected easily or replace, all should be encompassed within protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of described claim.

Claims (11)

1. a thin-film transistor, is characterized in that, comprises and is positioned at active layer, gate insulation layer, grid, interlayer insulating film and source electrode on flexible substrate and drain electrode successively;
Described thin-film transistor also comprises at least 1 the first via hole and at least 1 second via hole of through described interlayer insulating film and described gate insulation layer respectively; Described source electrode, described drain electrode contact with described active layer respectively by described first via hole, described second via hole;
Wherein, the figure of the figure of described active layer, the figure of described grid, the figure of described source electrode and described drain electrode is anti-fracture structure graph.
2. thin-film transistor according to claim 1, is characterized in that, described anti-fracture structure graph comprises at least one figure in annular, curve, broken line.
3. thin-film transistor according to claim 2, is characterized in that, described annular comprises square loop, rectangle ring, rhombus ring, circular rings.
4. thin-film transistor according to claim 2, is characterized in that, the figure of described active layer is made up of 1 described annular.
5. thin-film transistor according to claim 2, it is characterized in that, the 8 font dicyclos that the figure of described active layer is made up of 2 described annulars are formed, or the figure of described active layer is made up of 1 described annular and the curve crossing with described annular or broken line.
6. thin-film transistor according to claim 2, is characterized in that, the figure of described grid is made up of curve or broken line or 1 described annular.
7. thin-film transistor according to claim 2, is characterized in that, the figure of described source electrode is made up of curve or broken line; The figure of described drain electrode is made up of curve or broken line.
8. thin-film transistor according to claim 2, is characterized in that, the figure of described active layer is formed by N number of unit figure is arranged in parallel;
The 8 font dicyclos that described unit figure is made up of 2 described annulars are formed, or described unit figure is made up of 1 described annular and the curve crossing with described annular or broken line;
The figure of described grid is arranged by N number of described endless parallel and forms, or the figure of described grid is made up of N section curve or N section broken line;
The figure of described source electrode is made up of N section curve or N section broken line; The figure of described drain electrode is made up of N section curve or N section broken line;
Wherein, N be more than or equal to 2 positive integer.
9. the thin-film transistor according to any one of claim 1 to 8, is characterized in that, described active layer is low-temperature polysilicon silicon active layer.
10. an array base palte, is characterized in that, comprises the thin-film transistor as described in any one of claim 1 to 9.
11. 1 kinds of display unit, is characterized in that, comprise array base palte as claimed in claim 10.
CN201420631439.XU 2014-10-28 2014-10-28 A kind of thin-film transistor, array base palte, display unit Active CN204130548U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018218547A1 (en) * 2017-05-31 2018-12-06 深圳市柔宇科技有限公司 Metal oxide thin film transistor and display panel
CN111129125A (en) * 2019-12-18 2020-05-08 武汉华星光电半导体显示技术有限公司 TFT array substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018218547A1 (en) * 2017-05-31 2018-12-06 深圳市柔宇科技有限公司 Metal oxide thin film transistor and display panel
CN111129125A (en) * 2019-12-18 2020-05-08 武汉华星光电半导体显示技术有限公司 TFT array substrate
CN111129125B (en) * 2019-12-18 2022-07-12 武汉华星光电半导体显示技术有限公司 TFT array substrate

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