CN204068692U - A kind of RFID EEPROM charge pump - Google Patents
A kind of RFID EEPROM charge pump Download PDFInfo
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- CN204068692U CN204068692U CN201420431474.7U CN201420431474U CN204068692U CN 204068692 U CN204068692 U CN 204068692U CN 201420431474 U CN201420431474 U CN 201420431474U CN 204068692 U CN204068692 U CN 204068692U
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Abstract
A kind of RFID EEPROM charge pump, comprise the two-stage charge pump of first order charge pump and second level charge pump composition, level translator and clock generator, first order charge pump is powered by chip power supply voltage Vdd and is produced the low-voltage output signal higher than supply power voltage Vdd, first order charge pump outputs connects second level charge pump, the output of clock generator connects first order charge pump, the output of clock generator connects second level charge pump by level translator, and level translator connects first order electric charge delivery side of pump.RFID EEPROM charge pump of the present utility model, twin-stage charge pump is adopted to obtain the erasable required voltage of EEPROM, the high pressure clock needed for the charge pump of the second level is obtained by level translator, body effect is not obvious, the required high-voltage signal of EEPROM programming can be produced from low voltage, peak-current consumption can also be reduced to greatest extent simultaneously, thus improve sensitivity and the reading/writing distance of label chip.
Description
Technical field
The utility model relates to EEPROM field, particularly relates to a kind of a kind of EEPROM charge pump be applied in RFID integrated circuit.
Background technology
Radio frequency identification (Radio Frequency Identification, abbreviation RFID) system comprises RFID reader and one group of RFID label tag usually.RFID reader and label wirelessly complete and communicate, and for transmitting ID and data, these data all store on embedded EEPROM in the rfid chip usually.RFID label tag is all passive usually, the energy needed for being obtained by the radiofrequency field sent from RFID reader.Due to the retrievable finite energy of RFID label tag, and increase along with the distance with RFID reader and reduce, so the power consumption reducing RFID label tag just becomes very important as far as possible, particularly just all the more so for UHF rfid system.Under usual RFID label tag is operated in the even lower power of-20dBm, operating voltage is generally 1V.
RFID label tag adopts EEPROM to store ID and data usually, in EEPROM, is by executing to floating boom as 16V high-voltage signal thus forcing iunjected charge and realize the storage of data bit.Electric charge is transferred on floating boom by quantum tunneling effect, and after high-voltage signal disappears, electric charge still can retain.This just makes transistor be in " ON " state, on the contrary, is in " OFF " state when floating boom not having electric charge.
Charge pump normally first gives capacitor charging until power supply electrical level, then switched capacitor two terminals, to make the electric capacity bottom being in ground potential in charging process be in supply power voltage electromotive force after conversion, so just make other one end be in and double supply power voltage level.Then electric charge in electric capacity can transfer to next electric capacity, and repeats said process.By a series of like this process, the voltage signal more much higher than input voltage just can be obtained." Dixon " charge pump is a kind of typical charge pump configuration, as shown in Figure 1, for discrete component implementation, diode 1 is used for preventing electric charge by reverse leakage, and a diphasic clock output 2 provides bidirectional clock signal to be used for switched capacitor in order to be produced the high pressure Vout of high-pressure side 4 by the low pressure Vin of low-pressure end 5.The major defect of this scheme is the restriction that voltage transfer effect is subject to diode forward voltage.
Fig. 2 is the structure principle chart of a kind of Dixon charge pump for integrated circuit, the mode adopting transistor 2 to connect into diode instead of the mode of original diode 1, have employed diphasic clock the same as discrete component mode is for driving charge pump, its bi-phase clock signal as shown in Figure 3, this circuit is the same with discrete component, owing to being subject to nmos pass transistor threshold voltage V
threstriction, voltage transfer efficiency is not very good.Another one problem is commonly referred to " body effect ", i.e. the V of CMOS transistor
thvoltage signal increases along with the voltage between source electrode and drain electrode and increases.Often increase one-level, the efficiency of charge pump is just lower than upper level.This effect is more obvious when the progression boosted is more.
Fig. 4 is the charge pump circuit that one overcomes " body effect ", the grid voltage of each transistor 6 realizes " bootstrapping " by extra transistor, bootstrap transistor adds the voltage being applied to main transistor, at this moment just need a kind of non-superimposed four-phase clock circuit, its signal waveforms as shown in Figure 5.Even if having employed the boostrap circuit of this mode, be also difficult to produce the 16V high pressure needed for programming from the voltage signal lower than 1.8V.Therefore, present most RFID label tag all can only realize the asymmetric operation read and write, this is because read operation needs the voltage signal of about 1V usually, writes, needs higher voltage, usually about 1.5V.This just causes the asymmetric of read-write operation distance, writes distance and usually only has the half reading distance.
Under quiescent conditions, after output voltage has reached maximum and entered stable state, the current sinking of charge pump has depended primarily on load value.The output impedance of charge pump, such as electrical current ability, depend primarily on the frequency of the driving clock of charge pump.Except attempting improving except the efficiency of charge pump, improving room for improvement not too many in charge pump quiescent current consumption.
But at the initial charging phase of charge pump, current sinking is than much high under static state.Initial current drain is the emphasis that passive RFID tag chip needs to consider.Passive RFID tag chip obtains energy from the electromagnetic wave that reader is launched, and incoming signal level may be very low, usually needs to use radio frequency charge pump to be used for producing sufficiently high operating voltage.Charge pump generally has a lot of level, causes output resistance very high.In addition, label antenna is all tuned at high Q state usually to mate the input stage of charge pump.All these factors above-mentioned all can the ability providing larger current of limit RFI D input stage.In addition, the decoupling capacitance increasing a larger capacity also can bring many problems, as volume and cost increase etc.So the initial current size of the reduction EEPROM charge pump of maximum possible just becomes very important, this most critical factor also becoming restriction tag sensitivity and read distance.
Utility model content
The purpose of this utility model is to provide a kind of EEPROM charge pump for RFID label chip, while the supply power voltage needed for reducing, reduces the consumption of peak current to greatest extent, thus improves sensitivity and the reading/writing distance of label chip.
The technical scheme that the utility model is adopted for achieving the above object is: a kind of RFID EEPROM charge pump, comprise the two-stage charge pump of first order charge pump and second level charge pump composition, level translator and clock generator, first order charge pump connects chip power supply voltage (Vdd), first order charge pump outputs connects second level charge pump, the output of clock generator connects first order charge pump, the output of clock generator connects second level charge pump by level translator, and level translator connects first order electric charge delivery side of pump.
Described clock generator comprise at least one-level Clock dividers, in order to select different fractions frequently device output signal multiplexer and be used for controlling multiplexer to select the counter of different output, frequency divider is connected in series, master clock only connects the input of first order Clock dividers, and the output of the first order is as the input of second level Clock dividers; Multiplexer connects master clock and Clock dividers output at different levels, and counter connects master clock and multiplexer.
Described clock generator is voltage controlled oscillator.
Described first order charge pump is low voltage transistor circuit, adopts low pressure intrinsic NMOS transistor.
Described second level charge pump is high voltage transistor circuit, adopts high voltage intrinsic NMOS transistor.
Described first order charge pump and second level charge pump all adopt Dixon charge pump circuit or the charge pump with body effect compensating circuit.
Described chip power supply voltage Vdd is 16V lower than the erasable required voltage Vo2 of 1.5V, EEPROM.
RFID EEPROM charge pump of the present utility model, twin-stage charge pump is adopted to obtain the erasable required voltage of EEPROM, the high pressure clock needed for the charge pump of the second level is obtained by level translator, body effect is not obvious, can be integrated in the RFID chip simultaneously with low voltage transistor (as 1.8V) and high pressure (as 16V) semiconductor processes flow process, the required high-voltage signal of EEPROM programming can be produced from low voltage, peak-current consumption can also be reduced to greatest extent simultaneously, thus improve sensitivity and the reading/writing distance of label chip.
Accompanying drawing explanation
Fig. 1 is the Dixon charge pump schematic diagram of discrete component composition.
Fig. 2 is the Dixon charge pump schematic diagram in integrated circuit.
Fig. 3 is the diphasic clock figure of the Dixon charge pump in integrated circuit.
Fig. 4 is with the charge pump schematic diagram of body effect compensating circuit.
Fig. 5 is with four phase clock figure of the charge pump of body effect compensating circuit.
Fig. 6 is the utility model RFID EEPROM charge pump schematic diagram.
Fig. 7 is the input and output signal oscillogram of the utility model level translator.
Fig. 8 is that the utility model is for driving the clock generator schematic diagram of charge pump.
Fig. 9 is the output waveform figure of the utility model clock generator.
Figure 10 is the current drain figure of charge pump.
The output voltage waveform of Figure 11 charge pump.
In figure: 1, diode, 2, diphasic clock output, 3, electric capacity, 4, high-voltage output end, 5, low pressure input, 6, transistor.
Embodiment
Charge pump principle for RFID chip of the present utility model as shown in Figure 6, comprises two-stage charge pump, a level translator and a clock generator of a first order charge pump and second level charge pump composition.The present invention can be integrated in the RFID chip simultaneously with low voltage transistor (as 1.8V) and high pressure (as 16V) semiconductor processes flow process.
The first order of twin-stage charge pump is powered by chip power supply voltage Vdd, in order to produce the voltage output signal higher than Vdd, but simultaneously also enough low, thus this charge pump can all adopt low voltage transistor circuit realiration.First order charge pump outputs connects second level charge pump, and second level charge pump is powered by the output voltage Vo1 of first order charge pump and produced the erasable required voltage Vo2 of EEPROM, adopts high voltage transistor design.Chip power supply voltage Vdd can lower than 1.5V, is minimumly low to moderate 1V or lower.The final output voltage of charge pump, up to 16V, also suitably can change needed for the EEPROM technology adopted.Two-stage charge pump can adopt Dixon charge pump circuit or the charge pump with body effect compensating circuit, and wherein one or two also can adopt the charge pump of other form.
Clock generator can be driven by outside or inside master clock crystal oscillator, comprise one or more levels Clock dividers, in order to select the multiplexer of different fractions frequency device output signal and to be used for controlling multiplexer to select the counter of different output, different frequency dividers can connect with tandem, such master clock is only connected to the input of first order Clock dividers, the output of the first order is as the input of the second level, and by that analogy, the output of next stage frequency divider is the half of upper level clock frequency.Clock generator also can have a counter in order to record the different time periods, and counter can be used for controlling multiplexer to select different output.Such as, the counter first stage selects the output of last frequency divider, and second stage selects the output of penultimate frequency divider, the like, like this along with per a period of time increases, the output of multiplexer just increases or doubles.
Can also by other means in order to produce the cumulative clock frequency needed for charge pump.Crystal oscillator can also be a voltage controlled oscillator, by increasing voltage signal in order to increase the frequency of output signal.
The output of clock generator can be diphasic clock, and one of them clock phase is another inverted phase, also can be non-overlapped diphasic clock, and namely two clock phases can not be high simultaneously.Output signal can also be four phase clocks, or other form that above-mentioned twin-stage charge pump needs.Clock generator can all be realized by the low voltage logic circuit identical with chip power supply voltage Vdd.The output of clock generator can be directly connected to first order charge pump.The output of clock generator is by the high pressure clock needed for the charge pump of the level translator generation second level, and this level translator can have the output of first order charge pump to power.Clock generator output frequency increases generation by the mode of going forward one by one or continuation mode.Clock generator exports as bi-phase clock signal, non-overlapped bi-phase clock signal or four clock signal.
Specific embodiment:
RFID EEPROM charge pump of the present utility model can be used for the situation having low pressure (1.8V), middle pressure (3.3V) and high pressure (16V) transistor in production process of semiconductor, and RFID EEPROM charge pump comprises a clock generator, low pressure first charge pump stage, high pressure second charge pump stage and a level translator.
The input voltage of first order charge pump is Vdd, is 1V in typical case, but also can be more low-voltage.The low pressure diphasic clock that this grade is generated by clock generator drives.The output of first order charge pump is as the input Vo1 of second level charge pump, and voltage is about 3.3V.Vo1 returns level translator and powers, and its input is two low-voltage diphasic clock φ
l1and φ
l2, output is two middle pressure diphasic clock φs consistent with Vo1
h1and φ
h2, as shown in Figure 7.φ
h1and φ
h2be used as the clock signal of second level charge pump, the output signal Vo2 of second level charge pump can reach 16V.
First order charge pump only needs to produce about 3.3V voltage, and only need 4 grades of booster circuits, body effect is not obvious, can adopt common Dixon charge pump construction shown in Fig. 2, and low pressure (1.8V) intrinsic NMOS transistor also can be used to use as diode.
Second level charge pump needs to boost to 16V from 3.3V, and because clock at the corresponding levels adopts 3.3V, so only need 6 grades of booster circuits, same body effect is also not obvious.The usual Dixon charge pump construction shown in Fig. 1 can be adopted, high pressure (16 V) intrinsic NMOS transistor can be adopted to be used as diode to use.
Fig. 8 is the schematic diagram of clock generator, clock generator comprises two-stage frequency divider, i.e. first order Clock dividers and second level Clock dividers, a multiplexer and a counter, the input clock signal of clock generator is produced by inner or external crystal-controlled oscillation, clock signal frequency is all removed 2 by each grade of frequency divider, so produce output waveform figure a as shown in Figure 9, output waveform figure b, output waveform figure c, counter is used for three time period countings, first period, multiplexer selects oscillogram c as output, second time period, multiplexer selects oscillogram b as output, last time period, multiplexer selects oscillogram a as output, so final output waveform d is exactly the frequency increased progressively step by step.Such as, when clock input is 1MHz, the output of the first period is exactly 250KHz, and the output of the second time period is 500KHz, and in the remaining period, output is exactly 1MHz.
Figure 10 gives the circuitry consumes comparison diagram of charge pump.Only adopt the charge pump current of single clock frequency to consume e, actual current of the present invention consumes f and has lower peak value.Figure 11 gives actual output voltage oscillogram g in single-frequency clock output voltage waveforms h comparison diagram.Diagram waveform shows output voltage almost linearly, and the design of single clock frequency signal will increase in logarithmic form.As can be seen here, EEPROM charge pump of the present invention, while the supply power voltage needed for reducing, reduces the consumption of peak current to greatest extent.
The utility model is described by embodiment, and those skilled in the art know, without departing from the spirit and scope of the present invention, can carry out various change or equivalence replacement to these characteristic sum embodiments.In addition, under the teachings of the present invention, can modify to adapt to concrete situation and material to these characteristic sum embodiments and can not the spirit and scope of the present invention be departed from.Therefore, the present invention is not by the restriction of specific embodiment disclosed herein, and the embodiment in the right of all the application of falling into all belongs to protection scope of the present invention.
Claims (7)
1. a RFID EEPROM charge pump, it is characterized in that: comprise the two-stage charge pump of first order charge pump and second level charge pump composition, level translator and clock generator, first order charge pump connects chip power supply voltage (Vdd), first order charge pump outputs connects second level charge pump, the output of clock generator connects first order charge pump, the output of clock generator connects second level charge pump by level translator, and level translator connects first order electric charge delivery side of pump.
2. a kind of RFID EEPROM charge pump according to claim 1, it is characterized in that: described clock generator comprise at least one-level Clock dividers, in order to select different fractions frequently device output signal multiplexer and be used for controlling multiplexer to select the counter of different output, frequency divider is connected in series, master clock only connects the input of first order Clock dividers, and the output of the first order is as the input of second level Clock dividers; Multiplexer connects master clock and Clock dividers output at different levels, and counter connects master clock and multiplexer.
3. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described clock generator is voltage controlled oscillator.
4. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described first order charge pump is low voltage transistor circuit, adopts low pressure intrinsic NMOS transistor.
5. a kind of RFID EEPROM charge pump according to claim 4, is characterized in that: described second level charge pump is high voltage transistor circuit, adopts high voltage intrinsic NMOS transistor.
6. a kind of RFID EEPROM charge pump according to claim 5, is characterized in that: described first order charge pump and second level charge pump all adopt Dixon charge pump circuit or the charge pump with body effect compensating circuit.
7. a kind of RFID EEPROM charge pump according to claim 1, is characterized in that: described chip power supply voltage (Vdd) is 16V lower than the erasable required voltage (Vo2) of 1.5V, EEPROM.
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| CN201420431474.7U CN204068692U (en) | 2014-08-01 | 2014-08-01 | A kind of RFID EEPROM charge pump |
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| CN201420431474.7U CN204068692U (en) | 2014-08-01 | 2014-08-01 | A kind of RFID EEPROM charge pump |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106372711A (en) * | 2016-08-31 | 2017-02-01 | 爱康普科技（大连）有限公司 | Radio frequency power supply circuit and ultrahigh frequency passive electronic tag |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106372711A (en) * | 2016-08-31 | 2017-02-01 | 爱康普科技（大连）有限公司 | Radio frequency power supply circuit and ultrahigh frequency passive electronic tag |
| CN106372711B (en) * | 2016-08-31 | 2024-03-29 | 爱康普科技（大连）有限公司 | Radio frequency power supply circuit and ultrahigh frequency passive electronic tag |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210311 Address after: 116000 room 212, No.18, Software Park Road, Dalian hi tech park, Liaoning Province Patentee after: ICOMP TECHNOLOGY (DALIAN) Co.,Ltd. Patentee after: GUANGZHOU SYSUR MICROELECTRONICS, Inc. Address before: 116000 room 212, No.18, Software Park Road, Dalian hi tech park, Liaoning Province Patentee before: ICOMP TECHNOLOGY (DALIAN) Co.,Ltd. |
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| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211008 Address after: 116000 room 212, No.18, Software Park Road, Dalian hi tech park, Liaoning Province Patentee after: ICOMP TECHNOLOGY (DALIAN) Co.,Ltd. Address before: 116000 room 212, No.18, Software Park Road, Dalian hi tech park, Liaoning Province Patentee before: ICOMP TECHNOLOGY (DALIAN) Co.,Ltd. Patentee before: GUANGZHOU SYSUR MICROELECTRONICS, Inc. |