CN113903385A - Low-power-consumption programming voltage generation circuit for non-volatile memory in Internet of things security chip and working method - Google Patents
Low-power-consumption programming voltage generation circuit for non-volatile memory in Internet of things security chip and working method Download PDFInfo
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- CN113903385A CN113903385A CN202111371873.XA CN202111371873A CN113903385A CN 113903385 A CN113903385 A CN 113903385A CN 202111371873 A CN202111371873 A CN 202111371873A CN 113903385 A CN113903385 A CN 113903385A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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Abstract
A low-power consumption programming voltage generation circuit for a non-volatile memory in an Internet of things security chip comprises: the voltage regulator comprises an oscillator, a boosting charge pump, a voltage stabilizing diode and a voltage stabilizing capacitor, and further comprises a programmable non-overlapping clock generation circuit arranged between the oscillator and the boosting charge pump; the output end of the boosting charge pump is connected with a voltage detection circuit in parallel. The working time of the boosting charge pump in each clock cycle is reduced from tper-2 × td to tper-2 × N × td; the dynamic power consumption of the boosted charge pump 30 due to the dominant power consumption of the programming voltage generation circuit in the non-volatile memory is CfV2*(Duty_clka+Duty_clkb) And the Duty _ clka and the Duty _ clkb are reduced from (th-td)/tper to (th-N td)/tper, so that the dynamic power consumption of the booster charge pump is reduced to the original value of (th-N td)/(th-td) after the VPP end programming voltage reaches the set value.
Description
Technical Field
The invention relates to a low-power-consumption programming voltage generation circuit for a non-volatile memory in an Internet of things security chip and a working method, and belongs to the technical field of design of the Internet of things security chip.
Background
With the development of the application of the Internet of things in China, the safety of the Internet of things receives more and more attention. The internet of things security chip is used as an important component for protecting information acquisition, storage and transmission security in the application of the internet of things, and is also rapidly developed and applied. An important application field of the internet of things security chip is a Radio Frequency Identification (RFID) system, which performs non-contact bidirectional data communication in a radio frequency manner, and reads and writes a recording medium (a radio frequency tag or a radio frequency card, etc.) in the radio frequency manner, so as to achieve the purposes of identifying a target and exchanging data. The low power consumption design and the non-volatile memory design for storing data are important design links of the Internet of things security chip.
The complete RFID system is shown in FIG. 1 and is composed of an RFID card reader, an RFID chip and a background software system. The working principle is that the background software system controls the RFID card reader to transmit a radio signal with a certain frequency to the RFID chip so as to read data stored in the electronic tag. After receiving the signal sent by the RFID card reader, the RFID chip reads out the stored data of the RFID chip and returns the data to the RFID card reader by generating a radio signal with the same frequency. And the RFID card reader puts the data into a background software system for processing after obtaining the returned data so as to identify the correctness of the label.
The structure of the radio frequency identification tag is shown in fig. 2:
1. the coupling coil (01) has the function of receiving a radio signal sent by an RFID card reader or sending a radio signal to the RFID card reader.
And 2, the RF circuit (02) has the function of converting the radio signal received by the coupling coil into a digital signal which can be identified by the central processing unit or converting the digital signal sent by the central processing unit into a radio signal and sending the radio signal to the coupling coil for transmission.
3. The rectifying circuit (03) has the function of converting the received radio signal into a power supply used by the RFID chip through rectification and supplying power to the whole label.
4. The encryption module (04) has the functions of encrypting and decrypting data, ensuring the safety of processed information and being called by a central processing unit CPU (08).
5. The RAM (05) is a system memory for the CPU (08) to use.
6. Fixed data written by a label according to a client requirement before leaving a factory is placed in the read-only memory ROM (06), and can only be read by a central processing unit CPU (08), and the data content cannot be changed.
7. The data stored in the non-volatile memory (07) is written or modified according to the user requirement, wherein the data can be erased or written according to the instruction, and the central processing unit CPU (08) can read or modify the data stored in the non-volatile memory.
8. And the central processing unit CPU (08) is responsible for scheduling the use and operation of each module in the RFID chip and is the brain of the whole RFID chip.
The non-volatile memory used in the RFID chip is a programmable memory which can be modified by electric signals, and mainly comprises: the electrically programmable read-only memory EEPROM and Flash memory Flash can keep data from losing after power failure, and has the characteristics of high programming speed, strong reliability, long service life and the like.
The non-volatile memory used in the RFID chip stores electrons in the floating gate of the MOS tube, and the electrons on the floating gate in the MOS tube can be kept after the chip is powered off, so that the storage and the storage of data are realized. And a high voltage is needed to realize the attraction of electrons to the floating gate of the MOS tube or the elimination of the electrons in the floating gate of the MOS tube (EEPROM requires 15.5V voltage, and Flash requires 10V voltage). However, in order to achieve low power consumption, the RFID tag generally has only 1.8V or even 1.2V or 1V, and therefore the high voltage required for programming needs to be implemented by a programming voltage generating circuit with a boosting function.
The basic principle of a charge pump booster cell is shown in fig. 3: the circuit comprises a charging and discharging capacitor C, switches S1, S2, S3 and S4. When the phi 1 is a high level phi 2 and a low level phi 2, the voltage at two ends of the charge and discharge capacitor is VDD, that is, V + is VDD, and V ═ 0V; when Φ 2 is high Φ 1 is low, V-is connected to the VDD terminal, V + is connected to the output terminal Vout, and at this time, the voltage V-is VDD, and since the charge at both ends of the capacitor cannot change abruptly, the difference between the voltages of V + and V-is not VDD, the voltage of V + is 2 times VDD at this time, thereby boosting the voltage. The voltage can be further increased by using a cascade of a plurality of charge pump boosting units as shown in fig. 3.
The programming voltage generation circuit for generating the programming voltage by the nonvolatile memory used in the internet-of-things security chip is shown in fig. 4: including oscillator 10(OSC), Non-Overlap clock generation circuit 20(Non Overlap), boost Charge Pump 30(Charge Pump), Zener Diode 40(Zener Diode) and Zener capacitor 50, the basic principle is: the oscillator 10 outputs a clock signal clk with a certain frequency, the non-overlapping clock generation circuit 20 converts the input clk signal into two non-overlapping clock signals clka and clkb, the boost charge pump 30 raises the power supply voltage VDD to a voltage higher than the programming high voltage VPP of the non-volatile memory under the control of the non-overlapping clock signals clka and clkb, the programming high voltage VPP is limited within a voltage range (15.5V or 10V) required for programming the non-volatile memory by the zener diode 40, and the zener capacitor 50 is used for keeping the programming voltage stable during the programming process. The voltage stabilizing diode is a semiconductor device with high resistance until the critical reverse breakdown voltage, when the voltage applied to the two ends of the voltage stabilizing diode is higher than the conducting voltage of the voltage stabilizing diode, the voltage stabilizing diode is conducted, redundant charges can be discharged through the voltage stabilizing diode, and therefore the voltage at the two ends of the voltage stabilizing diode is kept at a certain voltage.
The circuit for generating the non-overlap clock required by the boost charge pump 30 is called a non-overlap clock generating circuit 20, the input of the circuit is the clock signal clk generated by the oscillator 10, and the output is two paths of non-overlap clocks clka and clkb, which include a delay unit 100(DLY), an inverter 200 and a nand gate 300. The non-overlap clock generator 20 converts the input clock signal clk generated by the oscillator 10 into two non-overlap clock signals clka and clkb, which are not simultaneously high. As shown in fig. 6, the input and output signals of the non-overlap clock generating circuit 20 are clock signals with a duty ratio of 50%, that is, a high level time th and a low level clock tl each occupy half of one clock cycle, and one cycle tper of the clock clk is the sum of the times th and tl, and usually th and tl each occupy 50% of tper; there is a delay td between the rising edge and the falling edge of the output clka and clkb signals, i.e. clka and clkb are not both high, because the clock period tper of clka and clkb is unchanged, and the proportion of high level in one clock period tper is less than 50%, the Duty ratio of clka is Duty _ clka, the Duty ratio of clkb is Duty _ clkb, and the delay td is mainly realized by the delay of the delay unit 100 of the non-overlapping clock generation circuit in fig. 5.
Fig. 4 is a waveform diagram of the programming voltage generated by the non-volatile memory programming voltage used in the security chip of the internet of things, as shown in fig. 5, after the programming voltage is generated and started, the boost charge pump 30 gradually raises the VPP terminal voltage under the control of the non-overlapping clocks clka and clkb, and during the generation of the programming voltage, in order to boost the charge pump 30 to realize fast boosting, although the Duty ratios of clka and clkb are lower than 50%, the Duty ratios, i.e., Duty _ clka and Duty _ clkb, are smaller than but close to 50%, so that the boost charge pump 30 is ensured to raise the VPP terminal voltage to the voltage required for programming as soon as possible.
After the boosting time T1, the voltage at the VPP terminal of the boosted charge pump 30 reaches the voltage required for programming the non-volatile memory, at this time, the voltage at the VPP terminal is stabilized by the voltage stabilizing capacitor 50 of the voltage stabilizing diode 40, the excess charge at the VPP terminal is discharged through the voltage stabilizing diode 40, the voltage at the VPP terminal is stabilized at the voltage (15.5V or 10V) required for programming the non-volatile memory, the time T2 required for programming is maintained, after the programming of the non-volatile memory is finished, the programming voltage generation circuit is turned off, and the programming voltage at the VPP terminal is discharged. Generally, the time T2 required for programming is much longer than the boosting time T1 and the drain time of the VPP programming voltage, and is the main generation time of the programming power consumption of the nonvolatile memory, and the power consumption consumed in the time is also the main power consumption ratio of the programming voltage generation circuit.
Because the application environment of the internet of things security chip is mainly portable and miniaturized, the internet of things security chip is usually powered by a battery or remotely wirelessly coupled, and belongs to a low-power-consumption application environment, the low-power-consumption design of the internet of things security chip is one of the most important links. When the non-volatile memory of the internet-of-things security chip is programmed, a boost circuit is required to generate a high voltage required by programming, so that large power consumption is generated, and the power consumption comprises dynamic power consumption of a clock generated by the oscillator 10, dynamic power consumption of the non-overlapping clock circuit 20, dynamic power consumption of the boost charge pump 30 and the like. The boosted charge pump 30 uses multi-stage charge pump boosting units to boost the VPP voltage by charging stage by stage, and when the voltage generated at the VPP terminal by the boosted charge pump 30 exceeds the voltage (15.5V or 10V) required by the programming of the non-volatile memory, the redundant charge is discharged through the Zener diode 40, so that the main power consumption of the programming process of the non-volatile memory comes from the dynamic power consumption of the boosted charge pump 30, and the redundant charge discharged by the Zener diode 40 and generated by the boosted charge pump 30 is also included.
The boost charge pump 30 dynamic power consumption is about CfV2(Duty _ clka + Duty _ clkb), where C is the sum of the capacitances of each stage in the boosted charge pump 30, f is the clock frequency at which the boosted charge pump 30 operates, V is the supply voltage VDD of the charge pump 30, Duty _ clka + Duty _ clkb is the Duty cycle ratio of the boosted charge pump 30, both Duty _ clka and Duty _ clkb are (th-td)/tper, and in the case where clka and clkb are both low, the boosted charge pump 30 is in the hold state and no power consumption is generated.
As described above, the dynamic power consumption of the programming voltage generation circuit accounts for a major part of the programming power consumption of the nonvolatile memory, and therefore, the low power consumption design of the nonvolatile memory is realized, and the dynamic power consumption of the boost charge pump 30 of the programming voltage generation circuit in the nonvolatile memory is mainly optimized when operating.
Disclosure of Invention
In order to solve the technical problem, the invention discloses a low-power-consumption programming voltage generation circuit for a non-volatile memory in an internet-of-things security chip.
The invention also discloses a working method of the circuit.
The detailed technical scheme of the invention is as follows:
a low-power consumption programming voltage generation circuit for a non-volatile memory in an Internet of things security chip comprises: the voltage regulator comprises an oscillator, a boosting charge pump, a voltage stabilizing diode and a voltage stabilizing capacitor, and is characterized by further comprising a programmable non-overlapping clock generation circuit arranged between the oscillator and the boosting charge pump; the output end of the boosting charge pump is connected with a voltage detection circuit in parallel;
the voltage detection circuit is configured to: the voltage detection circuit is used for detecting that the programming voltage generated by the programming voltage generation circuit, namely the VPP terminal voltage reaches the voltage (15.5V or 10V) required by the programming of the nonvolatile memory:
when the voltage at the VPP terminal is lower than the voltage required by programming the nonvolatile memory, the Vdet at the output end is logic 0;
when the voltage at the VPP node is higher than the voltage required for programming the non-volatile memory, the output terminal Vdet is logic 1.
According to a preferred embodiment of the present invention, the programmable non-overlap clock generation circuit includes: the input end is an oscillator, an output signal clk and a voltage detection circuit output control signal Vdet; the output terminals are non-overlapping clock signals clka and clkb; the multi-stage delay circuit also comprises a multi-stage delay unit, an inverter, a NAND gate and a multiplexer; the input ends of the multiplexer are input signals vi1 and vi2, a control end vt is input, and a signal end vo is output; an input signal vi2 is connected to the output of the first-stage delay unit, and an input signal vi1 is connected to the output of the nth-stage delay unit, where N is the number of delay units between the output of the nand gate and the input signal vi1, and the value of N can be modified according to circuit requirements; when the input control terminal vt is logic 0, the input signal vi2 is communicated to the output signal terminal vo; when the input control terminal vt is logic 1, the input signal vi1 is connected to the output signal terminal vo.
The operating method of the low power consumption programming voltage generating circuit is characterized by comprising the following steps:
when the programming voltage generating circuit generates programming voltage, the voltage of the VPP terminal is gradually increased, when the voltage does not reach the voltage required by the programming of the nonvolatile memory, the output Vset of the voltage detection circuit is logic 0, the programmable non-overlapping clock generator generates two paths of non-overlapping clock signals clka and clkb, the delay is td, the duty ratio of clka and clkb is higher (close to 50 percent), so that the boosting charge pump works in most of clocks (tper-2 td) in each clock period, and the voltage of the VPP terminal is rapidly increased;
after the voltage of the VPP terminal reaches the voltage (15.5V or 10V) required by the programming of the non-volatile memory, the voltage detection circuit outputs Vset to be logic 1, the programmable non-overlapping clock generator generates two paths of non-overlapping clock signals clka and clkb, the delay is N × td, the duty ratio of clka and clkb is reduced, the boosting charge pump only works in a small part of time of each clock cycle, and the voltage of the VPP terminal is guaranteed to be not lower than the voltage required by the programming of the non-volatile memory.
According to the present invention, preferably, after the VPP terminal voltage reaches the voltage (15.5V or 10V) required for programming the nonvolatile memory, the non-overlap delay time due to the input non-overlapping clocks clka and clkb of the boost charge pump increases to N × td; the boost charge pump will only work when clka and clkb are high, i.e. the boost operation is performed in the time tper-2 × N × td, to prevent the boost charge pump from generating the extra charge at the VPP terminal and discharging through the zener diode to realize the VPP voltage stabilization.
According to the invention, the operation method of the programmable non-overlapping clock generator is preferably as follows:
in the VPP terminal voltage boosting process, the Vdet signal is logic 0, the vi2 end of the multiplexer is connected to the output vo, the delay td for generating two paths of non-overlapping clock signals clka and clkb is the same as the delay generated by the non-overlapping clock generation circuit 20, and therefore the programming voltage generated by the boosting charge pump at the VPP end is boosted quickly;
when the voltage at the VPP end is higher than the voltage required by programming a non-volatile memory, the Vdet signal is changed into logic 1, the vi1 end of the multiplexer is connected to the output vo, and due to the fact that N stages of delay units are connected in series, the delay of two paths of non-overlapping clock signals clka and clkb is changed into the original N times, namely N × td, so that the duty ratio of clka and clkb is reduced.
According to the invention, preferably, the number of delay units in the programmable non-overlapping clock generator, namely the value of N, is set, so that after the voltage at the VPP end reaches the voltage required by the programming of the non-volatile memory, the working time of the boosted charge pump is shortened to tper-2N td, and the voltage at the VPP end is kept at the voltage required by the programming of the non-volatile memory under the action of the voltage stabilizing capacitor 50;
when the nonvolatile memory finishes programming, the control signal Vdet output by the voltage detection circuit is changed to 0 again in the process of discharging the VPP programming voltage, and since the oscillator 10 is turned off by the programming control signal at this time and no clock is output, the voltage detection circuit 60 and the programmable non-overlapping clock generator 21 do not affect the discharging process of the VPP terminal voltage.
The technical advantages of the invention are as follows:
in the invention, a Voltage detection circuit 60(Voltage Detector) is added in a Non-volatile memory programming Voltage generation circuit used in a traditional internet of things security chip shown in fig. 4, a Non-overlapping clock generation circuit 20 is replaced by a Programmable Non-overlapping clock generation circuit 21(Programmable Non Overlap), so that after the Non-volatile memory programming Voltage generation circuit used in the internet of things security chip generates a Voltage (15.5V or 10V) required by programming, the working time of a boost charge pump in each clock cycle is reduced from tper-2 td to tper-2N td; the dynamic power consumption of the boosted charge pump 30 due to the dominant power consumption of the programming voltage generation circuit in the non-volatile memory is CfV2*
And (Duty _ clka + Duty _ clkb), wherein the Duty _ clka and the Duty _ clkb are reduced from (th-td)/tper to (th-N td)/tper, so that the dynamic power consumption of the booster charge pump is reduced to the original (th-N td)/(th-td) after the VPP end programming voltage reaches a set value.
Drawings
FIG. 1 is a schematic diagram of a prior art RFID system;
FIG. 2 is a schematic diagram of an internal circuit structure of a passive RFID chip;
in fig. 2, 01, a coupling coil; 02. an RF circuit; 03. a power supply circuit; 04. an encryption module; 05. a Random Access Memory (RAM); 06. a read only memory ROM; 07. an electrically programmable read-only memory (EEPROM); 08. a central processing unit CPU;
FIG. 3 is a schematic diagram of a charge pump boost unit circuit;
FIG. 4 is a schematic diagram of a programming voltage generation circuit of a nonvolatile memory used in an Internet of things security chip;
in fig. 4, 10, an Oscillator (OSC); 20. a Non-Overlap clock generation circuit (Non overlay); 30. a boost Charge Pump (Charge Pump); 40. a Zener Diode (Zener Diode); 50. a voltage stabilizing capacitor;
FIG. 5 is a schematic diagram of a non-overlapping clock generation circuit;
in fig. 5, 100, delay element 100 (DLY); 200. an inverter; 300. a NAND gate;
FIG. 6 is a waveform diagram of input and output signals of the non-overlap clock generation circuit shown in FIG. 5;
FIG. 7 is a schematic diagram of a low-power programming voltage generation circuit of a non-volatile memory used in an Internet of things security chip according to the present invention;
in fig. 7, an oscillator; 21. a programmable non-overlapping clock generation circuit; 30. a boost charge pump; 40. a voltage regulator diode; 50. a voltage stabilizing capacitor; 60. a voltage detection circuit;
FIG. 8 is a schematic diagram of a programmable non-overlap clock generation circuit in the circuit of FIG. 7;
in fig. 8, 100, a multi-stage delay cell 100 (DLY); 200. an inverter; 300. a NAND gate; 400. a multiplexer;
FIG. 9 is a voltage waveform of a VPP terminal of a nonvolatile memory used in an Internet of things security chip in the circuit shown in FIG. 4 during programming.
Detailed Description
The present invention will be described in detail with reference to the following examples and drawings, but is not limited thereto.
Examples 1,
As shown in fig. 7.
A low-power consumption programming voltage generation circuit for a non-volatile memory in an Internet of things security chip comprises: the circuit comprises an oscillator 10, a boosting charge pump 30, a voltage stabilizing diode 40 and a voltage stabilizing capacitor 50, and further comprises a programmable non-overlapping clock generation circuit 21 arranged between the oscillator 10 and the boosting charge pump 30; the method further comprises the step of arranging a voltage detection circuit 60 in parallel at the output end of the boosting charge pump 30;
the voltage detection circuit 60 is configured to: the voltage detection circuit 60 is used for detecting that the programming voltage generated by the programming voltage generation circuit, namely the VPP voltage, reaches the voltage (15.5V or 10V) required by the programming of the nonvolatile memory:
when the voltage at the VPP terminal is lower than the voltage required by programming the nonvolatile memory, the Vdet at the output end is logic 0;
when the voltage at the VPP node is higher than the voltage required for programming the non-volatile memory, the output terminal Vdet is logic 1.
As shown in fig. 8.
The programmable non-overlap clock generation circuit 21 includes: the input end is an oscillator 10, an output signal clk, and a voltage detection circuit 60 to output a control signal Vdet; the output terminals are non-overlapping clock signals clka and clkb; the multi-stage delay circuit further comprises a multi-stage delay unit 100, an inverter 200, a NAND gate 300 and a multiplexer 400; the input ends of the multiplexer 400 are input signals vi1 and vi2, the control end vt is input, and the signal end vo is output; an input signal vi2 is connected to the output of the first-stage delay unit, and an input signal vi1 is connected to the output of the nth-stage delay unit, where N is the number of delay units between the output of the nand gate 300 and the input signal vi1, and the value of N can be modified according to circuit requirements; when the input control terminal vt is logic 0, the input signal vi2 is communicated to the output signal terminal vo; when the input control terminal vt is logic 1, the input signal vi1 is connected to the output signal terminal vo.
Examples 2,
The operating method of the low power consumption programming voltage generating circuit according to embodiment 1 includes:
when the programming voltage generating circuit generates the programming voltage, the VPP terminal voltage gradually rises, and when the voltage does not reach the voltage required by the programming of the nonvolatile memory, the output Vset of the voltage detection circuit 60 is logic 0, the programmable non-overlapping clock generator 21 generates two paths of non-overlapping clock signals clka and clkb, the delay is td, the duty ratio of clka and clkb is higher (close to 50%), so that the boosting charge pump works in most of clocks (tper-2 atd) in each clock period, and the VPP terminal voltage quickly rises;
after the VPP terminal voltage reaches the voltage (15.5V or 10V) required by the programming of the non-volatile memory, the voltage detection circuit 60 outputs Vset to be logic 1, the programmable non-overlapping clock generator 21 generates two non-overlapping clock signals clka and clkb, the delay is N × td, the duty ratio of clka and clkb is reduced, the boosting charge pump only works in a small part of time of each clock cycle, and the VPP terminal voltage is guaranteed to be not lower than the voltage required by the programming of the non-volatile memory.
After the VPP terminal voltage reaches the voltage (15.5V or 10V) required for programming the nonvolatile memory, the non-overlap delay time due to the input non-overlapping clocks clka and clkb of the boost charge pump 30 is increased to N × td; the boost charge pump 30 will only operate when clka and clkb are high, i.e. will operate for the time tper-2 × N × td, to prevent the boost charge pump 30 from generating extra charge at the VPP end and discharging the extra charge through the zener diode 40 to realize VPP voltage stabilization.
Examples 3,
The working method of the programmable non-overlap clock generator described in the embodiments 1 and 2 is as follows:
in the VPP terminal voltage boosting process, the Vdet signal is logic 0, the vi2 end of the multiplexer is connected to the output vo, the delay td for generating two paths of non-overlapping clock signals clka and clkb is the same as the delay generated by the non-overlapping clock generation circuit 20, and therefore the programming voltage generated by the boosting charge pump 30 at the VPP end is boosted quickly;
when the voltage at the VPP end is higher than or equal to the voltage required by the programming of the non-volatile memory, the Vdet signal is changed into logic 1, the vi1 end of the multiplexer 400 is connected to the output vo, and due to the fact that N stages of delay units are connected in series, the delay of two paths of non-overlapping clock signals clka and clkb is changed into the original N times, namely N × td, so that the duty ratio of clka and clkb is reduced.
By setting the number of delay units in the programmable non-overlapping clock generator 21, that is, the value of N, the operating time of the boost charge pump 30 is shortened to tper-2 × N × td after the VPP terminal voltage reaches the voltage required by the programming of the non-volatile memory, and the VPP terminal voltage is maintained at the voltage required by the programming of the non-volatile memory under the action of the voltage stabilizing capacitor 50;
when the nonvolatile memory finishes programming, the control signal Vdet output by the voltage detection circuit is changed to 0 again in the process of discharging the VPP programming voltage, and since the oscillator 10 is turned off by the programming control signal at this time and no clock is output, the voltage detection circuit 60 and the programmable non-overlapping clock generator 21 do not affect the discharging process of the VPP terminal voltage.
Claims (6)
1. A low-power consumption programming voltage generation circuit for a non-volatile memory in an Internet of things security chip comprises: the voltage regulator comprises an oscillator, a boosting charge pump, a voltage stabilizing diode and a voltage stabilizing capacitor, and is characterized by further comprising a programmable non-overlapping clock generation circuit arranged between the oscillator and the boosting charge pump; the output end of the boosting charge pump is connected with a voltage detection circuit in parallel;
the voltage detection circuit is configured to: the voltage detection circuit is used for detecting that the programming voltage generation circuit generates the programming voltage, namely the VPP terminal voltage reaches the voltage required by the programming of the nonvolatile memory:
when the voltage at the VPP terminal is lower than the voltage required by programming the nonvolatile memory, the Vdet at the output end is logic 0;
when the voltage at the VPP node is higher than the voltage required for programming the non-volatile memory, the output terminal Vdet is logic 1.
2. The low-power consumption programming voltage generation circuit for the non-volatile memory in the security chip of the internet of things according to claim 1, wherein the programmable non-overlapping clock generation circuit comprises: the input end is an oscillator, an output signal clk and a voltage detection circuit output control signal Vdet; the output terminals are non-overlapping clock signals clka and clkb; the multi-stage delay circuit also comprises a multi-stage delay unit, an inverter, a NAND gate and a multiplexer; the input ends of the multiplexer are input signals vi1 and vi2, a control end vt is input, and a signal end vo is output; an input signal vi2 is connected to the output of the first-stage delay unit, and an input signal vi1 is connected to the output of the nth-stage delay unit, where N is the number of delay units between the output of the nand gate and the input signal vi 1; when the input control terminal vt is logic 0, the input signal vi2 is communicated to the output signal terminal vo; when the input control terminal vt is logic 1, the input signal vi1 is connected to the output signal terminal vo.
3. The operating method of the low power consumption programming voltage generating circuit is characterized by comprising the following steps:
when the programming voltage generating circuit generates programming voltage, the voltage of the VPP terminal is gradually increased, when the voltage does not reach the voltage required by the programming of the nonvolatile memory, the output Vdet of the voltage detection circuit is logic 0, and the programmable non-overlapping clock generator generates two paths of non-overlapping clock signals clka and clkb with the time delay of td, so that the voltage of the VPP terminal is quickly increased;
when the voltage of the VPP terminal reaches the voltage required by the programming of the non-volatile memory, the voltage detection circuit outputs Vset to be logic 1, the programmable non-overlapping clock generator generates two paths of non-overlapping clock signals clka and clkb, the delay is N × td, and the voltage of the VPP terminal is not lower than the voltage required by the programming of the non-volatile memory.
4. The method of claim 3, wherein the low power consumption programming voltage generation circuit comprises a first voltage generation circuit,
after the voltage at the VPP terminal reaches the voltage required by programming the nonvolatile memory, the non-overlapping delay of input non-overlapping clocks clka and clkb of the boosting charge pump is increased to N × td; the boost charge pump will only work when clka and clkb are high, i.e. the boost operation is performed in the time tper-2 × N × td, to prevent the boost charge pump from generating the extra charge at the VPP terminal and discharging through the zener diode to realize the VPP voltage stabilization.
5. The method of claim 3, wherein the programmable non-overlap clock generator is operated by:
in the VPP terminal voltage boosting process, the Vdet signal is logic 0, the vi2 end of the multiplexer is connected to the output vo, and two paths of non-overlapping clock signals clka and clkb are delayed td, so that the programming voltage generated by the boosting charge pump at the VPP terminal is boosted quickly;
when the voltage at the VPP end is higher than the voltage required by programming a non-volatile memory, the Vdet signal is changed into logic 1, the vi1 end of the multiplexer is connected to the output vo, and due to the fact that N stages of delay units are connected in series, the delay of two paths of non-overlapping clock signals clka and clkb is changed into the original N times, namely N × td, so that the duty ratio of clka and clkb is reduced.
6. The operating method of the low-power consumption programming voltage generating circuit according to claim 3, wherein the number of delay units in the programmable non-overlapping clock generator, that is, the value of N, is set such that the operating time of the boosted charge pump is shortened to tper-2 × N × td after the VPP terminal voltage reaches the voltage required for programming the non-volatile memory, and the VPP terminal voltage is maintained at the voltage required for programming the non-volatile memory by the voltage stabilizing capacitor 50;
when the non-volatile memory finishes programming, the control signal Vdet output by the voltage detection circuit is changed to 0 again in the process of the VPP programming voltage leakage.
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| CN117079694A (en) * | 2023-09-11 | 2023-11-17 | 荣耀终端有限公司 | Chip and electronic equipment |
| CN117079694B (en) * | 2023-09-11 | 2024-02-23 | 荣耀终端有限公司 | Chip and electronic equipment |
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