KR100909838B1 - Low power and low area nonvolatile memory device - Google Patents

Abstract

The present invention is directed to a low power and low area nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a separate data input / output port, a bit line sense amplifier, and a DC-DC converter. The memory cell array includes a plurality of nonvolatile memory cells arranged in rows and columns, and a data input port receives data to be written into the nonvolatile memory cell. The bitline sense amplifier senses the data in the nonvolatile memory cell and outputs it to the data output port. The DC-DC converter generates first and second boost voltages for programming write data into a nonvolatile memory cell, the first and second using a Dickson charge pump circuit consisting of a plurality of Schottky diodes and pumping diodes connected in series. Generate second boosted voltages.

Nonvolatile Memory Devices, Bitline Sense Amplifiers, Dickson Charge Pumps, Schottky Diodes, Power Switching Circuits

Description

Non-volatile memory device for implementing low power consumption and small chip area

TECHNICAL FIELD The present invention relates to nonvolatile memory devices, and more particularly to low power and low area EEPROM.

Radio Frequency Identification (RFID) is a radio frequency identification technology that provides various services by collecting, storing, modifying, and tracking information of an object and surrounding information by using radio waves from a tag attached to the object. As RFID is widely used, efforts are being made to develop passive tag chips, which are advantageous for low-cost, small-sized, battery-less than active batteries. Among the RFID tag specifications, Generation2 of Class1 is a passive tag, which has advantages in miniaturization and price. In addition, it is equipped with additional functions such as read and write functions, as well as lock functions for enhanced security by users, and kills to prevent the use of tag chips. Applications in the field are expected.

The passive UHF RFID tag is composed of an antenna and a tag chip as shown in FIG. The tag chip 10 is composed of an analog circuit 11, a logic circuit 12, and a memory circuit 13. The analog circuit 11 uses the demodulator for converting the frequency received from the antenna into usable data, the modulator for converting the data into a frequency signal, and the energy supplied to the antenna by the reader as a supply voltage. The main consists of a voltage multiplier. The logic circuit 12 regulates protocols, cyclic redundancy check (CRC) checks, error checks, and operating modes of analog circuits. The memory circuit 13 may be read / write, and EEPROM, which is a nonvolatile memory capable of retaining stored information at power-down, is used. The memory capacity is 96 bits and 128/256 bits, but 1Kb EEPROM is required to store additional functions and information.

The passive tag chip 10 receives a UHF signal and checks the ID with a power supply voltage (VDD), which is a power generated by the voltage multiplier of the analog circuit 11, and design a low power circuit to transmit data to the reader. A small area IP is required to reduce the cost of the tag chip.

An object of the present invention is to provide a low power and low area EEPROM.

In order to achieve the above object, a nonvolatile memory device according to an aspect of the present invention, a memory cell array in which a plurality of nonvolatile memory cells are arranged in rows and columns; A data input port for receiving data to be written into the nonvolatile memory cell; A bit line sense amplifier configured to sense data of the nonvolatile memory cell and output the data to a data output port; And generating first and second boost voltages for programming write data into the nonvolatile memory cell, using a Dickson charge pump circuit composed of a plurality of Schottky diodes and pumping diodes connected in series. And a DC-DC converter for generating them.

According to embodiments of the present invention, a bit line sense amplifier comprises: a first inverter for inputting a precharge signal; A first PMOS transistor configured to precharge the data line to which the data of the nonvolatile memory cell is transferred to a power supply voltage level in response to an output of the first inverter; A second PMOS transistor driving the data line to a power supply voltage level in response to the data line load signal; A clocked inverter for inverting data of a data line in response to a sensing enable signal; And it may include a latch for latching the output of the clocked inverter to output to the data output port.

According to embodiments of the present invention, a clocked inverter includes: a second inverter configured to input a sensing enable signal; A third PMOS transistor having a power supply voltage connected to its source and a data line connected to its gate; A fourth PMOS transistor having a drain of a third inverter connected to a source thereof, a sensing enable signal connected to a gate thereof, and a drain of the third inverter being an output of the clocked inverter; A first NMOS transistor having an output of the second inverter connected to a gate thereof, and a drain of the fourth PMOS transistor connected to the drain thereof; The second NMOS transistor may include a ground voltage connected to its source, a data line connected to its gate, and a source of the first NMOS transistor connected to the drain thereof.

According to embodiments of the present invention, a DC-DC converter includes: a bandgap reference voltage generator for generating a reference voltage; A boosted voltage level detector for comparing the reference voltage with the first boosted voltage; A ring oscillator for outputting an oscillation signal in response to the output of the boosted voltage level detector; A boosted voltage control logic to generate first and second clock signals in response to an output of the ring oscillator; Charges for inputting a power supply voltage, and a plurality of first and second unit charge pump units responsive to the first and second clock signals are connected in series, and generating first and second node voltages and a first boosted voltage. A pump unit; And a power switching circuit configured to generate the first node voltage or the second node voltage as the second boosted voltage.

According to embodiments of the present invention, the DC-DC converter may include a first diode configured to input a power supply voltage to a first unit charge pump unit; A second diode for inputting an output of the first diode; A first pumping capacitor coupled between the output of the first diode and the inverted first clock signal; And a second pumping capacitor between the output of the second diode and the first clock signal. The second unit charge pump unit includes a third diode for inputting a power supply voltage; A fourth diode for inputting an output of the third diode; A third pumping capacitor connected between the output of the third diode and the second clock signal; And a fourth pumping capacitor between the output of the fourth diode and the inverted second clock signal.

According to embodiments of the present disclosure, a power supply switching circuit may include: a programming power supply selection signal generation unit driven by a first boosted voltage and configured to generate a programming power supply selection signal in response to a programming control signal; A clearing power selection signal generator driven by the first boosted voltage and generating a clearing power selection signal in response to the clearing control signal; A first switching unit transferring the first node voltage to the second boosted voltage in response to the programming power selection signal; And a second switching unit transferring the second node voltage to the second boosted voltage in response to the erase power selection signal.

According to embodiments of the present invention, the programming power supply selection signal generator includes: a first NMOS transistor having a programming control signal connected to a gate thereof and a ground voltage connected to a source thereof; A first inverter for inputting a programming control signal; A second NMOS transistor having an output of the first inverter connected to its gate and a ground voltage connected to the source thereof; A first PMOS transistor having a first boosted voltage connected to its source, a drain of the second NMOS transistor connected to its gate, and a drain of the first NMOS transistor connected to the drain thereof; A second PMOS transistor connected to a source of the first boosted voltage, a drain of the first NMOS transistor to a gate thereof, and a drain of the second NMOS transistor connected to the drain thereof; And a second inverter having a drain of the second PMOS transistor connected to an input thereof and outputting a programming power supply selection signal.

According to embodiments of the present disclosure, the erasing power selection signal generation unit may include: a first NMOS transistor having a clear control signal connected to a gate thereof, and a ground voltage connected to a source thereof; A first inverter for inputting a clear control signal; A second NMOS transistor having an output of the first inverter connected to its gate and a ground voltage connected to the source thereof; A first PMOS transistor having a first boosted voltage connected to its source, a drain of the second NMOS transistor connected to its gate, and a drain of the first NMOS transistor connected to the drain thereof; A second PMOS transistor connected to a source of the first boosted voltage, a drain of the first NMOS transistor to a gate thereof, and a drain of the second NMOS transistor connected to the drain thereof; And a second inverter having a drain of the second PMOS transistor connected to an input thereof and outputting a clear power selection signal.

According to embodiments of the present invention, the first switching unit includes a first PMOS having a first node voltage connected to a source thereof, a programming power supply selection signal connected to the gate thereof, and a second boosted voltage connected to the drain thereof. transistor; A second PMOS transistor having a programming power supply selection signal coupled to its source, a second boosted voltage coupled to its gate, and a first node voltage coupled to the drain; And a third PMOS transistor connected to a source of the programming power supply selection signal, a first node voltage connected to the gate thereof, and a second boosted voltage connected to the drain.

According to embodiments of the present invention, the second switching unit may include a first PMOS having a second node voltage connected to a source thereof, a clear power supply selection signal connected to the gate thereof, and a second boosted voltage connected to the drain thereof transistor; A second PMOS transistor having a clear power supply selection signal coupled to its source, a second boosted voltage coupled to its gate, and a second node voltage coupled to the drain; And a third PMOS transistor connected to the source thereof, the second node voltage connected to the gate thereof, and the second boosted voltage connected to the drain thereof.

The nonvolatile memory device of the present invention is designed as an asynchronous EEPROM to remove the command buffer and address buffer required by the synchronous EEPROM. In addition, the separate I / O (Separate I / O) method is used to remove the tra-state data output buffer used in the common I / O_ method and the low voltage supply voltage (VDD). In order to reliably supply the first and second step-up voltages (VPP, VPPL), which are the high voltages required by the EEPROM cell, the Dickson charge pump is designed using Schottky diodes instead of conventional PN junction diodes. Thus, the number of pumping stages of the charge pump is reduced to reduce the area occupied by the charge pump, and the Dixon charge pump is used to make the first boosted voltage VPP, and the arbitrary node voltage of the Dickson charge pump is reduced. The step-up voltage power supply switching circuit selects the first node voltage VPPL_PGM and the second node voltage VPPL_ERS, which are required in the program and erase modes, respectively. A low power EEPROM is realized by reducing the program current rather than making the required high voltage first and second boost voltages VPP and VPPL independent.

DETAILED DESCRIPTION In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings that describe exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram illustrating an EEPROM according to an embodiment of the present invention. Referring to FIG. 2, the EEPROM 20 may include, for example, an EEPROM cell array 21 having a 128 row by 8 column, a row decoder 22, a control logic unit 23 generating control signals according to an operation mode, and input data. A bit line sense amplifier and a write driver 24 for driving the cell to the cell and sensing and reading data from the cell, and a DC-DC converter 25 for supplying the high voltages necessary to perform the write function of the EEPROM.

The interface signal of the EEPROM 20 is largely a control signal, an address signal, input data, and output data. Control signals include Chip Enable (CE), ERASE, PROGRAM, READ, and RSTb (Reset) signals. In the address signal, one byte of 128 bytes is selected by the 7-bit address of ADD [6: 0], and DIN [7: 0] and DOUT [7: 0] are separated by Separate I / O. The operation mode includes an erase mode, a program mode, a read mode, a reset mode, and a standby mode, and an operation mode is determined according to control signals. Typically, write modes include erase and program modes. Read and write modes operate in synchronization with the rising edge of the clock signal.

The cells used in the EEPROM cell array 21 are arranged with flash EEPROM cells of 0.88 × 1.135 μm 2 and use a Fowler-Nordheim tunneling scheme in the erase mode and the program mode.

3 and 4 are diagrams for explaining an operation timing diagram of the EEPROM. FIG. 3 is a write mode timing diagram of the EEPROM 20 of FIG. 2. First, a 1 byte cell is erased in an erase period, and then data to be written is programmed. 4 is an EEPROM 20 read mode timing diagram. After a read command is applied, data is read on the rising edge of the next clock CLK.

On the other hand, in the case of the synchronous EEPROM, a command buffer for latching a control signal entering the rising edge of the clock signal CLK and a control state machine for decoding the command are required. In contrast, asynchronous EEPROMs do not require these circuits. The synchronous EEPROM has an address buffer that uses a positive-edge triggered D F / F to maintain a valid address only during each mode of operation. Asynchronous EEPROMs, on the other hand, eliminate address buffers by keeping the address until the operating mode is changed.

5 is a diagram illustrating a write timing diagram of an asynchronous EEPROM. Referring to FIG. 5, first, data of one byte cell of an address to be programmed is erased in an erase period, and then data to be programmed is written. The erase operation first applies an address to be written, activates the control signals CE and ERASE to logic high, and erases data of one byte cell of the selected address. In the program operation after erasing, the control signals CE and PROGRAM are activated to logic high while the address and the input data are first applied, and the input data is written in the 1 byte cell of the selected address.

6 is a diagram illustrating a read timing diagram of an asynchronous EEPROM. Referring to FIG. 6, when an address to be read is first applied, and then the control signals CE and READ are activated to logic high, the byte data of the selected cell has passed the data output port (TACC) after the access time tACC. DOUT). At this time, the control signals ERASE and PROGRAM must all maintain a logic low, and the data input DIN is in a don't care state.

In FIG. 2, the EEPROM 20 uses a separate I / O (Separate I / O) method that divides the data input port DIN and the data output port DOUT. As a result, the tri-state data output buffer can be removed, thereby reducing the layout area.

FIG. 7 is a circuit diagram illustrating the bitline sense amplifier of FIG. 2. Referring to FIG. 7, the bit line sense amplifier 24 supplies a data voltage DLINE to a power supply voltage in response to an output of the first inverter 71 and the first inverter 71 that inputs a precharge signal PRECHARGE. The first PMOS transistor 72 for precharging to the (VDD) level and the second PMOS transistor 73 for driving the data line DLINE to the power supply voltage VDD level in response to the data line load signal DLINE_LOADb. ), A latch for latching the output of the clocked inverter 74 and the output of the clocked inverter 74 to the data output port DOUT in response to the sensing enable signal SAENb. And 80. The output of the bit line sense amplifier 24 is the data output port DOUT.

The clocked inverter 74 includes a second inverter 75 for inputting a sensing enable signal SAENb and third and fourth PMOS transistors connected in series between the power supply voltage VDD and the ground voltage VSS. (76, 77) and the first and second NMOS transistors (78, 79). Gates of the third PMOS transistor 76 and the second NMOS transistor 79 are connected to the data line DLINE, and the gate of the fourth PMOS transistor 77 is connected to the sensing enable signal SAENb. The gate of the second NMOS transistor 79 is connected to the output of the second inverter 75.

The bias voltage levels of the EEPROM cells according to the operation mode of the EEPROM 20 (FIG. 2) are shown in Table 1. In the program mode, the VPP and VPPL voltages are 16V and 10V (= VPP-6V), respectively. In the erase mode, the VPP and VPPL voltages are 14V and 11V (= VPP-3V), respectively.

Program Erase Read Stand-by Cell Cell Cell All Control gate 16 V 0 V 1.8 V 0 V Bit-line 0V / 10V 14V / 11V 1.8 V Floating Source-Line Floating Floating 0 V 0 V HV-Pwell 0 V 14 V 0 V 0 V Deep-nwell 1.8 V 14 V 1.8 V 1.8 V

FIG. 8 is a block diagram illustrating the DC-DC converter of FIG. 2. Referring to FIG. 8, the DC-DC converter 25 generates a high voltage using a Dickson Charge Pump in a write mode. The DC-DC converter 25 includes a bandgap reference voltage generator 81, a boosted voltage (VPP) level detector 82, a ring oscillator 83, a boosted voltage (VPP) control logic unit 84, and a charge pump unit ( 85, and a second boosted voltage (VPPL) power supply switching circuit 86. The first boosted voltage VPP is provided to the first boosted voltage VPP level detector 82 and the charge pump unit 85. Each of the first boosted voltage VPP and the second boosted voltage VPPL is charged in the capacitors 87 and 88.

When the first boosted voltage VPP is lower than the target voltage, the output signal VPP_EN of the boosted voltage VPP level detector 82 becomes logic high to oscillate the ring oscillator 83. The positive charge is pumped to the first boosted voltage VPP node by the charge pump unit 85 so that the first boosted voltage VPP is increased. When the first boosted voltage VPP is equal to or higher than the target voltage, the output signal VPP_EN of the boosted voltage VPP level detector 82 becomes logic low, and the pumping is stopped using a negative feedback method. One boosted voltage VPP maintains a target voltage. The first boosted voltage (VPP) level detector circuit 82 uses a voltage divider in which 13 high voltage NMOS diodes are connected in series to divide the voltage VPP / 13 and the reference voltage VREF. Control the pump by comparing it. Therefore, the reference voltage VREF requires a voltage of 1.231 V in program mode and 1.077 V in Erase mode, as shown in Table 2.

Program [V] Erase [V] Read [V] Stand-by [V] VREF 1.231 1.077 0 0 VPP 16 14 1.8 1.8 VPPL 10 11 1.8 1.8

9 is a view for explaining the charge pump unit 85 of FIG. Referring to FIG. 9, the charge pump unit 85 is composed of a Dickson charge pump circuit and includes a plurality of series connected diodes for inputting a power supply voltage VDD, outputs of the diodes, clock signals CLK0, CLK0b, Pumping capacitors connected between CLK1 and CLK1b, respectively.

In the charge pump unit 85, the first and second diodes 91 and 92 and the first and second pumping capacitors 93 and 94 constitute one unit charge pump unit 95, and the unit charge pump Multiple portions 95 are connected in series. The first diode 91 inputs a power supply voltage VDD, and the second diode 92 inputs an output of the first diode 91. The first pumping capacitor 93 is connected between the output of the first diode 91 and the inverted first clock signal CLK0b, and the first pumping capacitor 93 is connected between the output of the second diode 92 and the first clock signal CLK0. Two pumping capacitors 94 are connected. The output of the first path 90 composed of the unit charge pump units 95 connected in series becomes a VPP voltage.

Similar to the first path 90, the charge pump unit 85 receives a power supply voltage VDD, and a second path in which a plurality of unit charge pump units 95 are connected in series and whose output is a VPP voltage. It may further include (100). However, the second path 100 differs in that the other end of the pumping capacitors is connected to the second clock signal CLK1b and the inverted second clock signal CLK1b.

The pumping capacitor of the charge pump unit 85 uses a metal-insulator-metal (MIM). The charge pump unit 85 uses a diode instead of a PN junction diode to reduce the area by reducing the number of pumping stages at low voltage. An N-type Schottky diode with low cut-in voltage is used.

10 is a cross-sectional view of the Schottky diode used in the charge pump section 85. Referring to FIG. 10, an anode is connected to CoSi2, which is a metallic material, and a cathode is connected to a high-voltage N-well to operate as an N-type Schottky diode.

As shown in Table 2, the voltage of the second boosted voltage VPPL is VPP-6V in the program mode and the voltage of the second boosted voltage VPPL in the erase mode is VPP-3V. In order to implement the VPPL for each operation mode, the arbitrary first node voltage VPPL_PGM (= VPP-6V) and the second node voltage VPPL_ERS (= VPP-3V) of the charge pump unit 85 of FIG. Power supply switching circuit to be supplied to the second boosted voltage VPPL.

FIG. 11 is a circuit diagram illustrating the power switching circuit of FIG. 8. Referring to FIG. 11, the power switching circuit 86 generates the second boosted voltage VPPL from the first node voltage VPPL_PGM and the second node voltage VPPL_ERS in response to the control signals PROGRAM and ERASE. . The power switching circuit 86 includes a programming power selection signal generator 110, a clear power selection signal generator 120, a first switching unit 130, and a second switching unit 140.

The programming power selection signal generator 110 may include a first NMOS transistor 111 and a programming control signal PROGRAM having a programming control signal PROGRAM connected to a gate thereof and a ground voltage VSS connected to a source thereof. The first NMOS transistor 113 and the second NMOS transistor 113 having the output of the first inverter 112 connected to the gate thereof and the ground voltage VSS connected to the source thereof; and the first boosted voltage VPP. A first PMOS transistor 114 connected to its source, a drain of the second NMOS transistor 113 connected to the gate thereof, and a drain of the first NMOS transistor 111 connected to the drain thereof, and a first boosted voltage The second PMOS transistor 115 having a voltage VPP connected to its source, a drain of the first NMOS transistor 111 connected to the gate thereof, and a drain of the second NMOS transistor 113 connected to the drain thereof. And the second PMOS transistor 115 Lanes and a second inverter 116, which outputs a programming input connected to the power source selection signal (PGM).

The erase power selection signal generator 120 may include the first NMOS transistor 121 and the erase control signal ERASE having the erase control signal ERASE connected to the gate thereof and the ground voltage VSS connected to the source thereof. A first NMOS transistor 123 and a first boosted voltage VPP having an input of an input of the first inverter 122, an output of the first inverter 122 connected to a gate thereof, and a ground voltage VSS connected to a source thereof The first PMOS transistor 124 and the first boosted voltage connected to the source thereof, the drain of the second NMOS transistor 123 connected to the gate thereof, and the drain of the first NMOS transistor 121 connected to the drain thereof; The second PMOS transistor 125 having a voltage VPP connected to the source thereof, a drain of the first NMOS transistor 121 connected to the gate thereof, and a drain of the second NMOS transistor 123 connected to the drain thereof. And the drain of the second PMOS transistor 125 has its input. It is connected to a second inverter 126 to output a clear select signal power (ERS).

The first switching unit 130 includes a first node having a first node voltage VPPL_PGM connected to its source, a programming power supply selection signal PGM connected to its gate, and a second boosted voltage VPPL connected to its drain. PMOS transistor 131, a second PMOS transistor having a programming power supply selection signal PGM connected to its source, a first node voltage VPPL_PGM connected to its gate, and a second boosted voltage VPPL connected to a drain And a third PMOS transistor 133 having a programming power supply selection signal PGM connected to its source, a first node voltage VPPL_PGM connected to its gate, and a second boosted voltage VPPL connected to a drain. ).

The second switching unit 140 includes a first node having a second node voltage VPPL_ERS connected to its source, a clear power supply selection signal ERS connected to its gate, and a second boosted voltage VPPL connected to its drain. PMOS transistor 141, a second PMOS transistor having a clear power supply selection signal ERS connected to a source thereof, a second boosted voltage VPPL connected to a gate thereof, and a second node voltage VPPL_ERS connected to a drain thereof; 142 and a third PMOS transistor 143 having a clear power supply selection signal ERS connected to the source thereof, a second node voltage VPPL_ERS connected to the gate thereof, and a second boosted voltage VPPL connected to the drain thereof. ).

FIG. 12 is a diagram illustrating a timing diagram of control signals generated by the control logic unit 23 (FIG. 2) in the read mode of the EEPROM 20 (FIG. 2). Referring to FIG. 12, when a read command is input, the data line DLINE and the bit line BL are precharged to the power supply voltage VDD by a precharge signal. When the data is transferred to the bit line BL while the word line WL is activated after the bit line BL is precharged, the data of the data line DLINE is detected by the sensing enable signal SAENb. The amplifier goes out to the data output port (DOUT). The simulation results show that tACC (Read access time) is 81㎱ when VDD is 1.62V and the temperature is 50 ℃.

FIG. 13 is a diagram illustrating a first boosted voltage VPP and a second boosted voltage VPPL in a program mode and an erase mode of the EEPROM 20 (FIG. 2). Referring to FIG. 13, the simulation result shows that the first boosted voltage VPP in the program mode is 16V, and the second boosted voltage VPPL_ is 10V, which is VPP-6V, and the first boosted voltage in the erase mode ( VPP) is 14V, and the second boosted voltage VPPL is outputted as 11V, which is VPP-3V.

FF model VDD = 1.98 V Temp = -40 ℃ TT model VDD = 1.8V Temp = 25 ℃ SS model VDD = 1.62V Temp = 50 ℃ READ 9.9 ㎂ 8.0 ㎂ 7.3 ㎂ ERASE 27.9 ㎂ 25.5 ㎂ 23.6 ㎂ PROGRAM 31.4 ㎂ 28.4 ㎂ 25.7 ㎂

Table 3 shows the current consumption of program mode, erase mode, and read mode for each simulation condition. For each simulation condition, the model shows wafer characteristics of NMOS and PMOS. FF, TT, and SS represent Fast, Typical, and Slow models, respectively. Under typical conditions, current consumption of read mode, erase mode and program mode is 8.0kW, 25.5kW and 28.4kW, respectively.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

1 is a diagram illustrating a passive UHF RFID tag.

2 is a block diagram illustrating an EEPROM according to an embodiment of the present invention.

3 and 4 are diagrams for explaining an operation timing diagram of a synchronous EEPROM.

5 is a diagram illustrating a write timing diagram of an asynchronous EEPROM.

6 is a diagram illustrating a read timing diagram of an asynchronous EEPROM.

FIG. 7 is a circuit diagram illustrating the bitline sense amplifier of FIG. 2.

FIG. 8 is a block diagram illustrating the DC-DC converter of FIG. 2.

FIG. 9 is a diagram for explaining the charge pump unit in FIG. 8. FIG.

10 is a cross-sectional view of a Schottky diode used in the charge pump unit of FIG. 9.

FIG. 11 is a circuit diagram illustrating the power switching circuit of FIG. 8.

FIG. 12 is a timing diagram of control signals generated in the control logic unit in the read mode of the EEPROM of FIG. 2.

FIG. 13 is a diagram illustrating a first boosted voltage and a second boosted voltage in a program mode and an erase mode of the EEPROM of FIG. 2.

Claims (10)

A memory cell array in which a plurality of nonvolatile memory cells are arranged in rows and columns; A data input port for receiving data to be written into the nonvolatile memory cell; A bit line sense amplifier configured to sense data of the nonvolatile memory cell and output the data to a data output port; And Generating first and second boost voltages for programming the write data into the nonvolatile memory cell, using a Dickson charge pump circuit composed of a plurality of Schottky diodes and pumping diodes connected in series. And a DC-DC converter for generating boost voltages. The method of claim 1, wherein the bit line sense amplifier A first inverter for inputting a precharge signal; A first PMOS transistor configured to precharge the data line to which the data of the nonvolatile memory cell is transferred to a power supply voltage level in response to an output of the first inverter; A second PMOS transistor driving the data line to the power supply voltage level in response to a data line load signal; A clock inverter for inverting data of the data line in response to a sensing enable signal; And And a latch configured to latch an output of the clocked inverter to output the data output port. The method of claim 2, wherein the clocked inverter A second inverter configured to input the sensing enable signal; A third PMOS transistor having the power supply voltage connected to its source and the data line connected to its gate; A fourth PMOS transistor having a drain of the third inverter connected to a source thereof, a sensing enable signal connected to a gate thereof, and a drain of the third inverter being an output of the clocked inverter; A first NMOS transistor having an output of the second inverter connected to a gate thereof, and a drain of the fourth PMOS transistor connected to the drain thereof; And And a second NMOS transistor coupled to a ground voltage thereof, a source line thereof coupled to a gate thereof, and a source of the first NMOS transistor coupled to a drain thereof. The DC-DC converter of claim 1, wherein A bandgap reference voltage generator for generating a reference voltage; A boosted voltage level detector for comparing the reference voltage with the first boosted voltage; A ring oscillator for outputting an oscillation signal in response to the output of the boosted voltage level detector  A boosted voltage control logic unit configured to generate first and second clock signals in response to an output of the ring oscillator; A plurality of first and second unit charge pump units receiving a power supply voltage and responding to the first and second clock signals are connected in series, and generating first and second node voltages and the first boosted voltage. A charge pump unit; And And a power supply switching circuit which generates the first node voltage or the second node voltage as the second boosted voltage. The method of claim 4, wherein the first unit charge pump unit A first diode for inputting the power supply voltage; A second diode for inputting the output of the first diode; A first pumping capacitor connected between the output of the first diode and the inverted first clock signal; And A second pumping capacitor is provided between the output of the second diode and the first clock signal, The second unit charge pump unit A third diode configured to input the power supply voltage; A fourth diode for inputting an output of the third diode; A third pumping capacitor connected between the output of the third diode and the second clock signal; And And a fourth pumping capacitor between the output of the fourth diode and the inverted second clock signal. The method of claim 4, wherein the power switching circuit is A programming power selection signal generator driven by the first boosted voltage and configured to generate a programming power selection signal in response to a programming control signal; A clear power selection signal generation unit driven by the first boosted voltage and generating a clear power selection signal in response to a clear control signal; A first switching unit transferring the first node voltage to the second boosted voltage in response to the programming power selection signal; And And a second switching unit configured to transfer the second node voltage to the second boosted voltage in response to the erase power selection signal. The method of claim 6, wherein the programming power selection signal generator A first NMOS transistor having a programming control signal coupled to a gate thereof and a ground voltage coupled to a source thereof; A first inverter for inputting the programming control signal; A second NMOS transistor having an output of the first inverter connected to a gate thereof, and a ground voltage connected to a source thereof; A first PMOS transistor connected to a source of the first boosted voltage, a drain of the second NMOS transistor to a gate thereof, and a drain of the first NMOS transistor connected to the drain thereof; A second PMOS transistor connected to a source of the first boosted voltage, a drain of the first NMOS transistor to a gate thereof, and a drain of the second NMOS transistor connected to the drain thereof; And And a second inverter having a drain of the second PMOS transistor connected to an input thereof to output the programming power selection signal. The method of claim 6, wherein the erase power selection signal generator A first NMOS transistor coupled with the erase control signal to a gate thereof, and a ground voltage coupled to a source thereof; A first inverter for inputting the erase control signal; A second NMOS transistor having an output of the first inverter connected to a gate thereof, and a ground voltage connected to a source thereof; A first PMOS transistor connected to a source of the first boosted voltage, a drain of the second NMOS transistor to a gate thereof, and a drain of the first NMOS transistor connected to a drain thereof; A second PMOS transistor connected to a source of the first boosted voltage, a drain of the first NMOS transistor to a gate thereof, and a drain of the second NMOS transistor connected to the drain thereof; And And a second inverter having a drain of the second PMOS transistor connected to an input thereof to output the erase power selection signal. The method of claim 6, wherein the first switching unit A first PMOS transistor coupled to the source of the first node voltage, coupled to the gate of the programming power supply selection signal, coupled to the drain of the second boosted voltage;  A second PMOS transistor coupled with the programming power supply selection signal to its source, coupled with the second boosted voltage to its gate, and coupled with the first node voltage to a drain; And  And a third PMOS transistor, wherein the programming power supply selection signal is connected to a source thereof, the first node voltage is connected to a gate thereof, and the second boosted voltage is connected to a drain. . The method of claim 6, wherein the second switching unit A first PMOS transistor connected at a source thereof to the second node voltage, at a gate thereof to the erase power selection signal, and at a drain thereof to the second boosted voltage;  A second PMOS transistor coupled to the erase power selection signal to a source thereof, the second boosted voltage to a gate thereof, and the second node voltage to a drain; And And a third PMOS transistor coupled to the source thereof, the second node voltage connected to the gate thereof, and the second boosted voltage connected to the drain thereof. .

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