CN117079694A - Chip and electronic equipment - Google Patents

Chip and electronic equipment Download PDF

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Publication number
CN117079694A
CN117079694A CN202311165751.4A CN202311165751A CN117079694A CN 117079694 A CN117079694 A CN 117079694A CN 202311165751 A CN202311165751 A CN 202311165751A CN 117079694 A CN117079694 A CN 117079694A
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China
Prior art keywords
voltage
unit
switch
power supply
electrically connected
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Granted
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CN202311165751.4A
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Chinese (zh)
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CN117079694B (en
Inventor
李垒
王峰
李子鹏
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Honor Device Co Ltd
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Honor Device Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The embodiment of the application provides a chip and electronic equipment, and relates to the technical field of integrated circuits. The chip is electrically connected with the power module and comprises an instruction operation unit, a clock generation unit, a frequency decision unit, a voltage adjustment control unit and a programmable boost unit. The instruction operation unit is electrically connected with the clock generation unit, the frequency decision unit and the programmable boost unit, the clock generation unit is electrically connected with the programmable boost unit, the voltage adjustment control unit is electrically connected with the clock generation unit, the frequency decision unit and the programmable boost unit, and the programmable boost unit is electrically connected with the power supply module. The programmable boost unit is used for: the current voltage of the instruction operation unit is raised to a target voltage according to the boost control signal of the voltage adjustment control unit and the target clock signal of the clock generation unit. The instruction operation unit is used for: based on the target voltage and the target clock signal. The programmable boost unit supplies power to the instruction arithmetic unit, thereby increasing the voltage regulation rate.

Description

Chip and electronic equipment
Technical Field
The embodiment of the application relates to the technical field of integrated circuits (Integrated Circuit, ICs), in particular to a chip and electronic equipment.
Background
As the operating rates of various components (e.g., processors) within a chip become higher, the operating frequencies of the corresponding chips become higher. The working frequency of the chip and the working voltage are in positive correlation. When the working frequency of the chip is increased, the working voltage is increased first until the working voltage tends to be stable, and then the working frequency is increased. Currently, power supplies for chips typically employ switching power supplies that typically employ dynamic voltage frequency scaling (Dynamic Voltage and Frequency Scaling, DVFS) techniques or adaptive voltage frequency scaling (Adaptive Voltage and Frequency Scaling, AVFS) techniques to regulate the operating voltage. However, when the chip increases the operating frequency, the voltage adjustment rate of the switching power supply is low, resulting in a longer adjustment delay of the operating frequency, thereby affecting the response performance of the chip.
Disclosure of Invention
The embodiment of the application provides a chip and electronic equipment, and aims to solve the problem that the voltage regulation rate of a power supply is low when the working frequency of the chip is increased.
The first aspect of the embodiment of the application provides a chip, which is electrically connected with a power supply module and comprises an instruction operation unit, a clock generation unit, a frequency decision unit, a voltage adjustment control unit and a programmable boost unit. The frequency decision unit is electrically connected with the instruction operation unit and is used for: the target frequency is calculated based on the calculation power demand information of the instruction calculation unit. The voltage adjustment control unit is electrically connected with the frequency decision unit and the clock generation unit and is used for: based on the target frequency being higher than the current frequency of the instruction operation unit, outputting a corresponding boost control signal according to the target frequency and the current voltage of the instruction operation unit; and controlling the clock generating unit to generate a target clock signal, wherein the working frequency of the target clock signal is the target frequency. The programmable boost unit is electrically connected with the clock generation unit, the voltage adjustment control unit and the instruction operation unit and is used for: the present voltage is raised to a target voltage corresponding to the target frequency according to the boost control signal and the clock signal of the clock generation unit. The instruction operation unit is electrically connected with the clock generation unit and the programmable boost unit and is used for: based on the target voltage and the target clock signal.
In this embodiment, since the programmable boost unit is integrated inside the chip, when the chip needs to increase the operating frequency, the programmable boost unit can boost the target voltage faster than the power module outside the chip, and output the voltage provided by the programmable boost unit to the instruction operation unit, thereby reducing the time delay of the increase of the operating voltage, and improving the power supply efficiency. Moreover, since the working voltage rises faster, the working frequency rises faster, thereby improving the response performance of the chip. In addition, since the operating voltage rises faster, the duration that the operating voltage is greater than the minimum operating voltage required by the operating frequency is shorter, and thus the wasted energy is reduced, thereby improving the energy efficiency of the chip.
In one of the embodiments, the programmable boost unit is further configured to: based on the current voltage rising to the target voltage, a boosting completion signal is output. The voltage adjustment control unit is also used for: and outputting a frequency adjustment command according to the boosting completion signal. The clock generation unit is further configured to: and generating a target clock signal according to the frequency adjustment instruction.
In another embodiment, the programmable boost unit includes a switched capacitor circuit including a flying capacitor and an output capacitor, first to fourth switches, a first voltage comparator, a reference voltage source, and a switch control signal generator. One end of the flying capacitor is connected between the first switch and the fourth switch, and the other end of the flying capacitor is connected between the second switch and the third switch; the first switch and the third switch are electrically connected to the circuit input end, the second switch is grounded, the fourth switch is connected to the circuit output end, the circuit input end is used for being electrically connected to the power supply module, and the circuit output end is used for being electrically connected to the instruction operation unit; one end of the output capacitor is electrically connected to the output end of the circuit, and the other end of the output capacitor is grounded; the first input end of the first voltage comparator is electrically connected to the circuit output end, the second input end of the first voltage comparator is electrically connected to the reference voltage source, and the output end of the first voltage comparator is electrically connected to the switch control signal generator; the reference voltage source is electrically connected with the voltage adjustment control unit; the switch control signal generator is electrically connected with the first switch to the fourth switch and the clock generating unit. The reference voltage source is used for: and outputting a reference voltage according to the boost control signal, wherein the difference value between the reference voltage and the target voltage is within a preset value range. The first voltage comparator is used for: and outputting an enabling signal based on the fact that the difference value between the output voltage of the circuit output end and the reference voltage exceeds a preset value range. The switch control signal generator is used for: and adjusting the duty ratio of a switch control signal according to the enable signal and the clock signal, wherein the switch control signal is used for controlling the switch states of the first switch to the fourth switch, and the switch states comprise on or off.
In this embodiment, since the capacitance value of the flying capacitor is small, the time delay of charging and discharging the flying capacitor is short, and thus the output voltage of the switched capacitor circuit rises faster. And because the switch capacitor circuit is integrated in the chip, the distance between the output end of the switch capacitor circuit and the instruction operation unit is shorter, so that the working voltage of the chip is also faster.
In another embodiment, the flying capacitor is in a charged state based on the first and second switches being closed, the third and fourth switches being open; based on the first switch and the second switch being turned on, the third switch and the fourth switch being turned off, the flying capacitor being in a discharge state, the flying capacitor charging the output capacitor, the voltage across the output capacitor being equal to the output voltage at the output of the circuit.
In this embodiment, since the voltage across the flying capacitor does not change suddenly, the voltage at one end of the flying capacitor can be increased by changing the voltage at the other end of the flying capacitor, thereby charging the output capacitor. The duty ratio of the switch control signal is adjusted, so that the duty ratio of the charge duration and the discharge duration of the flying capacitor can be adjusted, and the voltage at two ends of the output capacitor, namely the output voltage of the switch capacitor circuit, is adjusted.
In another embodiment, the chip further includes a power switching unit electrically connected to the voltage adjustment control unit, the programmable boost unit, the power module, and the instruction operation unit. The voltage adjustment control unit is also used for: and outputting a power supply switching instruction according to the boosting completion signal. The power supply switching unit is used for: outputting a voltage provided by the power supply module based on the voltage output by the programmable boost unit not reaching the target voltage; and outputting the target voltage provided by the programmable boost unit according to the power supply switching instruction.
In this embodiment, the power supply switching unit first controls the power supply from the power supply module to the instruction arithmetic unit. When the boosting of the programmable boosting unit is completed, the power supply switching unit is switched to supply power to the instruction operation unit by the programmable boosting unit, so that the time delay of the rise of the working voltage is reduced, and the power supply efficiency is improved.
In another embodiment, the power switching unit is further configured to: outputting the target voltage provided by the programmable boost unit based on the voltage output by the power supply module not reaching the target voltage; and outputting the voltage provided by the power supply module based on the voltage output by the power supply module reaching the target voltage.
In this embodiment, the power supply switching unit controls the power supply from the programmable boosting unit to the instruction arithmetic unit. When the boosting of the power supply module is completed, the power supply switching unit is switched to supply power to the instruction operation unit by the power supply module.
In another embodiment, the power switching unit includes a second voltage comparator, a power switching switch controller, and a power switching switch. The first input end of the second voltage comparator is electrically connected to the power supply module, the second input end of the second voltage comparator is electrically connected to the programmable boost unit, and the output end of the second voltage comparator is electrically connected to the power supply change-over switch controller; the power supply change-over switch controller is electrically connected with the power supply change-over switch and the voltage adjustment control unit; one end of the power supply change-over switch is electrically connected to the power supply module or the programmable boost unit, and the other end of the power supply change-over switch is electrically connected to the instruction operation unit. The second voltage comparator is used for: and outputting a voltage adjustment completion signal based on the difference value between the voltage of the power supply module and the target voltage of the programmable boost unit being within a preset value range. The power supply changeover switch controller is used for: and outputting a power supply switching signal according to the power supply switching instruction or the voltage regulation completion signal, wherein the power supply switching signal is used for indicating a power supply switching switch to switch the connecting line.
In another embodiment, the power switching signals include a first power switching signal and a second power switching signal, and the power switching switch controller is configured to: and outputting a first power supply switching signal according to the power supply switching instruction, wherein the first power supply switching signal is used for instructing a power supply switching switch to switch a connecting line between the power supply module and the instruction operation unit into a connecting line between the programmable boost unit and the instruction operation unit. Or outputting a second power supply switching signal according to the voltage regulation completion signal, wherein the second power supply switching signal is used for instructing a power supply switching switch to switch a connecting line between the programmable boost unit and the instruction operation unit into a connecting line between the power supply module and the instruction operation unit.
In another embodiment, the power switching unit further includes a filter capacitor. One end of the filter capacitor is electrically connected to the instruction operation unit, and the other end of the filter capacitor is grounded. The filter capacitor is used for: at the moment when the power supply changeover switch changes over the connecting line, power is supplied to the instruction operation unit.
In this embodiment, since the voltage drop occurs at the moment when the power supply switch switches the connection line, the filter capacitor is disposed at the other end of the power supply switch, thereby being beneficial to avoiding the voltage drop from affecting the power supply of the instruction arithmetic unit.
In another embodiment, the chip further comprises a performance detection unit. The performance detection unit is electrically connected with the clock generation unit and the voltage adjustment control unit, and the power supply environment of the performance detection unit is the same as that of the instruction operation unit. The performance detection unit is used for: based on the target voltage and the target clock signal, a detection voltage corresponding to the target frequency is detected, and the detection voltage is output. The voltage adjustment control unit is also used for: and outputting an operating voltage adjustment instruction based on the detected voltage not reaching the target voltage, wherein the operating voltage adjustment instruction is used for instructing the programmable boost unit or the power supply module to adjust the output voltage to the target voltage.
In this embodiment, the performance detecting unit fine-adjusts the voltage of the programmable voltage boosting unit or the power supply module until the voltage to be output by the programmable voltage boosting unit or the power supply module reaches the target voltage.
A second aspect of the embodiment of the present application provides an electronic device, where the electronic device includes a power module and a chip according to the embodiment of the present application, and the chip is electrically connected to the power module.
The technical effects brought by the second aspect of the embodiments of the present application may be referred to the related description of the chip of the first aspect, which is not repeated here.
Drawings
Fig. 1 is a schematic diagram illustrating a correspondence relationship between an operating frequency and an operating voltage of a chip provided by an example.
Fig. 2 is a schematic diagram of a chip provided by an example.
Fig. 3 is a schematic diagram of a power module provided by an example.
Fig. 4 is a schematic diagram of the operating voltage versus operating frequency variation in the context of increasing and decreasing the operating frequency of a chip provided by an example.
Fig. 5 is a schematic structural diagram of a chip according to an embodiment of the present application.
Fig. 6 is a schematic diagram of a programmable boost unit according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of a power switching unit according to an embodiment of the present application.
Fig. 8 is a timing diagram of a power switching process of a chip according to an embodiment of the present application.
Fig. 9 is a schematic diagram of the change of the operating voltage and the operating frequency in the case of increasing and decreasing the operating frequency of the chip according to an embodiment of the present application.
Fig. 10 is a schematic structural diagram of a chip according to another embodiment of the present application.
Fig. 11 is a schematic structural diagram of a chip according to another embodiment of the present application.
Fig. 12 is a schematic structural diagram of a chip according to another embodiment of the present application.
Detailed Description
It should be noted that, in the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and the representation may have three relationships, for example, a and/or B may represent: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The performance of the chip is related to the operating frequency. The higher the operating frequency of the chip, the faster the response speed and thus the better the performance. For example, when the operating frequency of the chip reaches 1GHz, the period of 1us includes 1000 clock cycles, and the maximum number of instructions executed by the processor of the chip for the period of 1us may reach 1000.
The working frequency of the chip and the working voltage are in positive correlation. For example, as shown in fig. 1, when the operating frequency of the chip is F1, the corresponding operating voltage is V1; when the working frequency of the chip is F2, the corresponding working voltage is V2; when the working frequency of the chip is F3, the corresponding working voltage is V3. When F1< F2< F3, V1< V2< V3. When the operating frequency of the chip needs to be reduced from F3 to F2 or F1, since V3 is greater than the minimum operating voltage required by F2 or F1, the operating frequency can be reduced first, and then the operating voltage can be reduced from V3 to V2 or V1, respectively. When the operating frequency of the chip needs to be increased from F1 to F2 or F3, since V1 is smaller than the minimum operating voltage required by F2 or F3, the operating voltage needs to be increased from V1 to V2 or V3, respectively, and then the operating frequency needs to be increased.
The operating frequency of the chip is generated by an internal clock generating unit and the operating voltage is provided by an external power supply module. The power scheme of the chip is exemplarily described below with reference to fig. 2 and 3.
Fig. 2 is a schematic diagram of a chip provided by an example.
As shown in fig. 2, the chip 100 includes an instruction operation unit 110, a clock generation unit 120, a frequency decision unit 130, a performance detection unit 140, and a voltage adjustment control unit 150. Wherein the instruction operation unit 110 is electrically connected to the clock generation unit 120 and the frequency decision unit 130. The clock generation unit 120 is electrically connected to the performance detection unit 140. The voltage adjustment control unit 150 is electrically connected to the clock generation unit 120, the frequency decision unit 130, the performance detection unit 140, and the power module 200 outside the chip 100. The instruction operation unit 110 and the performance detection unit 140 are electrically connected to the power module 200, respectively.
The instruction operation unit 110 may be a processor, which may include, but is not limited to, an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing Unit, GPU), an image signal processor (Image Signal Processor, ISP), a controller, a video codec, a digital signal processor (Digital Signal Processor, DSP), a baseband processor, a Neural-network processor (Neural-Network Processing Unit, NPU), and the like.
The clock generation unit 120 is configured to generate a clock signal and output the clock signal to the instruction operation unit 110 and the performance detection unit 140. The clock signal includes an operating frequency.
The frequency decision unit 130 is configured to calculate a target frequency according to the power demand information from the instruction operation unit 110, and output the target frequency to the voltage adjustment control unit 150. Wherein the power demand information is used to characterize the computing power that the instruction arithmetic unit 110 needs to achieve to run the pre-configured instructions. In one embodiment, the power demand information includes a predicted power value. When the predicted calculation force value is greater than the maximum calculation force value of the instruction calculation unit 110 at the current operation frequency, it is indicated that the current operation frequency cannot meet the calculation force demand, and at this time, the operation frequency needs to be increased, thereby increasing the calculation force value of the instruction calculation unit 110.
The performance detecting unit 140 is configured to detect a detection voltage corresponding to an operating frequency of the clock signal from the clock generating unit 120 under the excitation of the voltage from the power supply module 200, and output the detection voltage to the voltage adjustment control unit 150. The detection voltage output by the performance detection unit 140 is substantially equal to the operation voltage of the instruction operation unit 110. When the detected voltage output by the performance detecting unit 140 does not reach the minimum operating voltage required by the operating frequency, it is indicated that the current operating frequency of the instruction calculating unit 110 is lower than the operating frequency of the clock signal, and the voltage of the power module 200 needs to be increased until the detected voltage output by the performance detecting unit 140 reaches the minimum operating voltage required by the operating frequency. The performance detecting unit 140 is used for fine-tuning the voltage of the power module 200 until the voltage of the power module 200 reaches the minimum operating voltage required by the operating frequency.
The voltage adjustment control unit 150 is configured to obtain a corresponding target voltage according to the target frequency from the frequency decision unit 130, and output a target voltage adjustment instruction to the power module 200; when the operating voltage from the performance detecting unit 140 does not reach the minimum operating voltage required by the operating frequency, an operating voltage adjustment command is output to the power module 200; and, when receiving the voltage adjustment completion signal from the power supply module 200, outputting a frequency adjustment instruction to the clock generation unit 120. The target voltage adjustment command is used to instruct the power module 200 to adjust the output voltage to a target voltage, where the target voltage is the minimum operating voltage required by the target frequency. The operating voltage adjustment command is used to instruct the power module 200 to adjust the output voltage to the minimum operating voltage required by the operating frequency. The voltage adjustment completion signal is used to inform the voltage adjustment control unit 150 that the voltage of the power supply module 200 has been adjusted. The frequency adjustment instruction is for instructing the clock generation unit 120 to adjust the operating frequency to the target frequency.
It is understood that the voltage adjustment control unit 150 may acquire the corresponding target voltage according to the target frequency based on the correspondence between the preconfigured target voltage and the target frequency. For example, the voltage adjustment control unit 150 may store a correspondence table of target voltages and target frequencies. When the voltage adjustment control unit 150 receives the target frequency from the frequency decision unit 130, it queries the corresponding relation table according to the target frequency to obtain the corresponding target voltage.
The power module 200 typically employs a switching power supply (e.g., a DC-DC converter) that typically employs DVFS technology or AVFS technology to regulate the operating voltage of the chip 100.
Fig. 3 is a schematic diagram of a power module provided by an example.
As shown in fig. 3, the power module includes a Buck (Buck) circuit including an input capacitor C IN Output capacitance C OUT An inductance L and switching transistors Q1 and Q2. The switching tube Q1 and Q2 are connected IN series, the switching tube Q1 is electrically connected to the input end IN, and the switching tube Q2 is grounded. One end of the inductor L is electrically connected between the switching transistors Q1 and Q2, and the other end of the inductor L is electrically connected to the output terminal OUT. Input capacitance C IN Is electrically connected to the input terminal IN, and is input with a capacitor C IN The other end of which is grounded. Output capacitor C OUT Is electrically connected to the output terminal OUT, and outputs a capacitor C OUT The other end of which is grounded.
Illustratively, the switching transistors Q1 and Q2 may each be a Metal-Oxide-semiconductor transistor (MOSFET) or an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), and the embodiment is not limited to a specific type of switching transistor.
The switching transistors Q1 and Q2 are turned on or off based on the control signal, thereby inputting the voltage V IN Step-down conversion to output voltage V OUT . The output voltage variation value can be calculated by the formula (1):
（1）
in the course of the time period T,for outputting the voltage variation value, < >>Is the change value of the inductance charge quantity, ">Is the inductance current variation value. Inductance current variation value can be communicatedCalculated by the formula (2):
（2）
wherein,the inductance voltage, L is the inductance value.
As is clear from the formulas (1) and (2), in the case where the inductance value is constant, the maximum value of the inductance voltage is limited due to the withstand voltage limitation of the switching transistors Q1 and Q2, and thus the maximum value of the inductance current variation value is limited. At the output capacitance C OUT And the time period T is fixed, the maximum value of the variation value of the output voltage is limited because the maximum value of the variation value of the inductor current is limited. Thus, during the period T, the voltage V is outputted OUT The amount of regulation of (c) may be limited, thereby limiting the voltage regulation rate.
The voltage regulation bandwidth of the Buck circuit is usually below 1MHz, and the voltage regulation rate is lower than 100mv/us. For chips with operating frequencies above 1GHz, the voltage regulation rate of the Buck circuit cannot meet the regulation requirement of the operating voltage.
For example, as shown in fig. 4, in the case where the operating frequency of the chip increases and decreases, the curve S1 is a curve of the operating voltage with time, and the curve S2 is a curve of the operating frequency with time. When the chip needs to increase the working frequency, the power module starts voltage regulation at the time t 1. At time t2, the voltage adjustment of the power supply module is completed, the working voltage of the chip reaches the minimum working voltage required by the target frequency, and the clock generation unit of the chip starts the frequency adjustment. At time t3, the clock generation unit frequency adjustment is completed. When the chip needs to reduce the working frequency, at the time t4, the clock generating unit of the chip starts frequency adjustment. At time t5, the clock generation unit frequency adjustment is completed, and the power supply module starts voltage adjustment. From time t1 to time t2, the operating voltage of the chip gradually rises, while the operating frequency remains unchanged, and the energy efficiency is lower because the operating voltage is greater than the minimum operating voltage required by the current operating frequency. In addition, since the rate of rise of the operating voltage of the chip is low, the time delay of the rise of the operating frequency is long, thereby affecting the response performance of the chip.
Based on the above, the embodiment of the application provides a chip and electronic equipment, which aim to solve the problem that the voltage regulation rate of a power supply is low when the working frequency of the chip is increased.
The chip structure provided by the embodiment of the application is specifically described below with reference to fig. 5 to 7.
Fig. 5 is a schematic structural diagram of a chip according to an embodiment of the present application.
The chip structure of the present embodiment is different from the chip structure shown in fig. 2 in that a programmable boosting unit and a power switching unit are newly added inside the chip.
Referring to fig. 2 and fig. 5 together, based on the chip structure shown in fig. 2, the programmable boost unit 160 is electrically connected to the clock generating unit 120, the voltage adjustment control unit 150, and the power switching unit 170. The power switching unit 170 is electrically connected to the instruction operation unit 110, the performance detection unit 140, and the voltage adjustment control unit 150. The programmable boost unit 160 and the power switching unit 170 are electrically connected to the power module 200 outside the chip 100, respectively.
The voltage adjustment control unit 150 outputs a corresponding boost control signal to the programmable boost unit 160 according to the target frequency and the current voltage of the instruction operation unit 110, based on the target frequency being higher than the current frequency of the instruction operation unit 110. The boost control signal includes a current voltage of the instruction operation unit 110 and a target voltage, and is used to instruct the programmable boost unit 160 to boost the current voltage of the instruction operation unit 110 to the target voltage.
The programmable boost unit 160 is configured to boost the current voltage of the instruction operation unit 110 to a target voltage according to the boost control signal from the voltage adjustment control unit 150 and the clock signal from the clock generation unit 120; and, when the boosting is completed, outputting a boosting completion signal to the voltage adjustment control unit 150. The boosting completion signal is used to notify the voltage adjustment control unit 150 of the completion of boosting by the programmable boosting unit 160. The voltage adjustment control unit 150 outputs a power supply switching instruction to the power supply switching unit 170 and a frequency adjustment instruction to the clock generation unit 120 based on the boosting completion signal. The power supply switching instruction is for instructing the power supply switching unit 170 to output the voltage supplied by the programmable boosting unit 160 to the instruction arithmetic unit 110. The clock generation unit 120 generates a target clock signal according to the frequency adjustment instruction, the operating frequency of the target clock signal being the target frequency.
The power supply switching unit 170 is configured to output the target voltage supplied from the programmable boost unit 160 to the instruction operation unit 110 according to the power supply switching instruction from the voltage adjustment control unit 150; and outputting the voltage supplied by the power module 200 to the instruction operation unit 110 when the voltage outputted by the power module 200 reaches the target voltage.
The performance detecting unit 140 is configured to detect a detection voltage corresponding to a target frequency of the target clock signal from the clock generating unit 120 under the excitation of the voltage from the programmable boosting unit 160 or the power supply module 200, and output the detection voltage to the voltage adjustment control unit 150. The voltage adjustment control unit 150 outputs an operating voltage adjustment instruction for instructing the programmable voltage boosting unit 160 or the power supply module 200 to adjust the output voltage to the target voltage, based on the detected voltage not reaching the target voltage corresponding to the target frequency.
In this embodiment, since the programmable boost unit is integrated inside the chip, when the chip needs to increase the operating frequency, the programmable boost unit can boost to the target voltage faster than the power module outside the chip, and the power switching unit outputs the voltage provided by the programmable boost unit to the instruction operation unit, thereby reducing the time delay of the increase of the operating voltage, and thus improving the power supply efficiency. Moreover, since the working voltage rises faster, the working frequency rises faster, thereby improving the response performance of the chip. In addition, since the operating voltage rises faster, the duration that the operating voltage is greater than the minimum operating voltage required by the operating frequency is shorter, and thus the wasted energy is reduced, thereby improving the energy efficiency of the chip.
Fig. 6 is a schematic diagram of a programmable boost unit according to an embodiment of the present application.
As shown in fig. 6, the programmable boost unit includes a switched capacitor circuit including a Fly (Fly) capacitor C F Output capacitance C out Switches S1 to S4, a voltage comparator 161, a switch control signal generator 162, and a reference voltage source 163. Wherein Fly capacitor C F One end of (C) is connected between the switches S1 and S4, fly capacitor C F And the other end of which is connected between switches S2 and S3. Switches S1 and S3 are electrically connected to the circuit input IN, switch S2 is grounded, and switch S4 is electrically connected to the circuit output OUT. The circuit input terminal IN is electrically connected to the power module 200, and the circuit output terminal OUT is electrically connected to the instruction operation unit 110. Output capacitor C out Is electrically connected to the circuit output terminal OUT, and outputs a capacitor C out The other end of which is grounded. A first input terminal of the voltage comparator 161 is electrically connected to the circuit output terminal OUT, a second input terminal of the voltage comparator 161 is electrically connected to the reference voltage source 163, and an output terminal of the voltage comparator 161 is electrically connected to the switch control signal generator 162. The reference voltage source 163 is electrically connected to the voltage adjustment control unit 150. The switch control signal generator 162 electrically connects the switches S1 to S4 and the clock generation unit 120.
The voltage comparator 161 is for outputting a voltage V based on the circuit output terminal OUT out The difference with the reference voltage from the reference voltage source 163 is out of the preset value range, and an enable signal is output to the switching control signal generator 162. Wherein the enable signal is used to instruct the switch control signal generator 162 to generate a switch control signal for controlling the switch states of the switches S1 to S4, the switch states including on or off.
The switching control signal generator 162 is used for adjusting the duty ratio of the switching control signal according to the enable signal and the clock signal from the clock generation unit 120. For example, when the switch control signal is high, switches S1 and S2 are closed, switches S3 and S4 are open, fly capacitor C F And (5) charging. When the switch control signal is low, the switches S1 and S2 are turned on, the switches S3 and S4 are turned off, and the Fly capacitor C F And (5) discharging. Due to Fly capacitance C F Voltage acrossNo abrupt change occurs, and therefore by changing Fly capacitance C F Can increase Fly capacitance C F To output capacitor C out And (5) charging. By adjusting the duty cycle of the switch control signal, fly capacitance C can be adjusted F Duty ratio of charge duration and discharge duration of (C), thereby adjusting output capacitance C out The voltage across, i.e. regulating the output voltage V out . For example, when the duty ratio of the switch control signal is 50%, the voltage V is output out Can reach the input voltage V in Twice as many as (x).
The reference voltage source 163 is configured to output a reference voltage to the voltage comparator 161 according to the boost control signal from the voltage adjustment control unit 150, where a difference between the reference voltage and the target voltage is within a preset range.
In the present embodiment, due to Fly capacitance C F The capacitance value of (2) is small, so that Fly capacitance C F The time delay of charging and discharging is short, thereby outputting the voltage V out The rise is faster. And because the switch capacitor circuit is integrated in the chip, the distance between the output end OUT of the switch capacitor circuit and the chip load (namely, the instruction operation unit) is shorter, so that the working voltage of the chip is also faster.
Since the switched-capacitor circuit regulates the output voltage V by closed-loop control out Therefore, the switched capacitor circuit is always in a voltage regulation state, i.e. outputting voltage V out When the target voltage is reached, the switched-capacitor circuit still continues to perform closed-loop control, resulting in lower voltage output efficiency of the switched-capacitor circuit. Therefore, when the voltage output by the power supply module reaches the target voltage, the power supply switching unit controls the programmable boost unit to stop supplying power, and the power supply module supplies power to the chip load, so that the power supply efficiency of the chip is improved.
Fig. 7 is a schematic structural diagram of a power switching unit according to an embodiment of the present application.
As shown in fig. 7, the power switching unit includes a voltage comparator 171, a power switching switch controller 172, a power switching switch S, and a filter capacitor C. The first input end of the voltage comparator 171 is electrically connected to the power module 200, the second input end of the voltage comparator 171 is electrically connected to the programmable boost unit 160, and the output end of the voltage comparator 171 is electrically connected to the power switch controller 172. The power supply changeover switch controller 172 is electrically connected to the power supply changeover switch S and the voltage adjustment control unit 150. One end of the power switch S is electrically connected to the power module 200 or the programmable boost unit 160, and the other end of the power switch S is electrically connected to the output terminal OUT. The output terminal OUT is electrically connected to the instruction operation unit 110. One end of the filter capacitor C is electrically connected to the output end OUT, and the other end of the filter capacitor C is grounded.
The voltage comparator 171 is configured to output a voltage adjustment completion signal to the power supply changeover switch controller 172 based on a difference between the voltage from the power supply module 200 and the target voltage from the programmable boosting unit 160 being within a preset value range. Wherein the voltage adjustment completion signal is used to inform the power supply changeover switch controller 172 that the voltage adjustment of the power supply module 200 is completed. The power supply changeover switch controller 172 outputs a power supply changeover signal for instructing the power supply changeover switch S to change over the connection line according to the voltage adjustment completion signal. The power switch S switches a connection line between the programmable boost unit 160 and the output terminal OUT to a connection line between the power module 200 and the output terminal OUT based on the power switching signal.
The power supply changeover switch controller 172 is configured to output a power supply changeover signal to the power supply changeover switch S in accordance with a power supply changeover instruction from the voltage adjustment control unit 150 or a voltage adjustment completion signal from the voltage comparator 171. When the operating frequency of the chip 100 needs to be increased, the programmable boost unit 160 completes the boost, so the power switch controller 172 receives the power switch command first and outputs a power switch signal to the power switch S. The power switch S switches a connection line between the power module 200 and the output terminal OUT to a connection line between the programmable boost unit 160 and the output terminal OUT according to the power switching signal. Then, when the power supply module 200 completes the boosting, the power supply changeover switch controller 172 receives the voltage adjustment completion signal and outputs a power supply changeover signal to the power supply changeover switch S. The power switch S switches a connection line between the programmable boost unit 160 and the output terminal OUT to a connection line between the power module 200 and the output terminal OUT according to the power switching signal.
Since the power supply switch S will drop in voltage at the moment of switching the connection line, the filter capacitor C is disposed at the other end of the power supply switch S, and the filter capacitor C is used for supplying power to the chip load at the moment of switching the connection line by the power supply switch S.
The power switching process of the chip will be described below using the chip 100 shown in fig. 5 as an example.
Fig. 8 is a timing diagram of a power switching process of a chip according to an embodiment of the present application.
As shown in fig. 8, the power switching process of the chip includes the steps of:
s101, the instruction operation unit outputs calculation power demand information to the frequency decision unit.
S102, the frequency decision unit calculates the target frequency according to the calculation power demand information.
S103, the frequency decision unit outputs the target frequency to the voltage adjustment control unit.
S104, the voltage adjustment control unit outputs a boost control signal to the programmable boost unit based on the target frequency being higher than the current frequency of the instruction operation unit.
S105, the voltage adjustment control unit outputs a target voltage adjustment instruction to the power supply module.
S106, the clock generation unit outputs a clock signal to the programmable boost unit.
S107, the programmable boosting unit boosts the current voltage of the instruction operation unit to the target voltage according to the boosting control signal and the clock signal.
S108, the programmable boosting unit outputs the target voltage to the power supply switching unit.
S109, the programmable boosting unit outputs a boosting completion signal to the voltage adjustment control unit based on the boosting completion.
S110, the voltage adjustment control unit outputs a power supply switching instruction to the power supply switching unit according to the boosting completion signal.
S111, the power supply switching unit switches a connecting line between the instruction operation unit and the power supply module into a connecting line between the instruction operation unit and the programmable boost unit according to the power supply switching instruction.
S112, the power supply switching unit outputs the target voltage to the instruction operation unit.
S113, the voltage adjustment control unit outputs a frequency adjustment instruction to the clock generation unit.
S114, the clock generation unit outputs a target clock signal to the instruction operation unit according to the frequency adjustment instruction.
S115, the power module increases the voltage to the target voltage according to the target voltage adjustment command.
S116, the power supply module outputs voltage to the power supply switching unit.
S117, the power supply switching unit switches a connecting line between the instruction operation unit and the programmable boost unit into a connecting line between the instruction operation unit and the power supply module based on the difference value between the voltage from the power supply module and the target voltage from the programmable boost unit within a preset value range.
S118, the power supply switching unit outputs voltage to the instruction operation unit.
S119, the power supply switching unit outputs a power supply switching completion signal to the voltage adjustment control unit.
The power supply switching completion signal is used for notifying the voltage adjustment control unit that the power supply switching unit completes power supply switching.
S120, the voltage adjustment control unit outputs a closing signal to the programmable boost unit according to the power supply switching completion signal.
The closing signal is used for indicating the programmable boost unit to be closed.
S121, the programmable boost unit is turned off according to the turn-off signal.
Wherein, the operation is stopped when the device is closed.
In this embodiment, when the chip needs to increase the operating frequency, the programmable boosting unit inside the chip can boost to the target voltage faster than the power module outside the chip. After the programmable boost unit is boosted, the programmable boost unit supplies power to the chip load, so that the working frequency can be increased more quickly, and the response performance of the chip is improved. Then, after the boosting of the power supply module is completed, power is supplied to the chip load by the power supply module. Under the condition that the working voltage and the working frequency of the chip tend to be stable, compared with a programmable boost unit, the power supply efficiency of the power supply module is higher.
For example, referring to fig. 4 and fig. 9 together, when the chip needs to increase the operating frequency, the programmable boost unit and the power module start voltage adjustment at time t 1. At time t2', the voltage regulation of the programmable boost unit is completed, the power supply switching unit switches the power supply of the power supply module into the power supply of the programmable boost unit, the working voltage of the chip reaches the minimum working voltage required by the target frequency, and the clock generating unit of the chip starts the frequency regulation. At time t3', the clock generation unit frequency adjustment is completed. After the voltage regulation of the power supply module is completed, the power supply switching unit switches the programmable boost unit power supply to the power supply module power supply. When the chip needs to reduce the working frequency, at the time t4, the clock generating unit of the chip starts frequency adjustment. At time t5, the clock generation unit frequency adjustment is completed, and the power supply module starts voltage adjustment. Wherein time t2' is before time t 2. From time t1 to time t2', the working voltage of the chip is rapidly increased, and the chip can rapidly start frequency adjustment, so that the time delay of the increase of the working frequency is reduced, and the response performance of the chip is improved.
The embodiment of the application also provides an electronic device, which may include the chip 100 and the power module 200 shown in fig. 5.
It is understood that in other embodiments, the chip 100 shown in fig. 5 may not include the performance detection unit 140 and/or the power switching unit 170.
In the case where the chip 100 does not include the performance detecting unit 140, as shown in fig. 10, the instruction calculating unit 110 is electrically connected to the clock generating unit 120, the frequency deciding unit 130, and the power switching unit 170. The clock generation unit 120 is electrically connected to the programmable boost unit 160. The voltage adjustment control unit 150 is electrically connected to the clock generation unit 120, the frequency decision unit 130, the programmable boost unit 160, the power switching unit 170, and the power module 200 outside the chip 100. The programmable boost unit 160 is electrically connected to the power switching unit 170 and the power module 200. The power switching unit 170 is electrically connected to the power module 200.
The voltage adjustment control unit 150 is further configured to output a power supply switching instruction to the power supply switching unit 170 according to the boosting completion signal from the programmable boosting unit 160, the power supply switching instruction being configured to instruct the power supply switching unit 170 to output the target voltage supplied by the programmable boosting unit 160 to the instruction arithmetic unit 110.
The power supply switching unit 170 is configured to output the target voltage supplied from the programmable boost unit 160 to the instruction operation unit 110 according to the power supply switching instruction from the voltage adjustment control unit 150; and outputting the voltage supplied by the power module 200 to the instruction operation unit 110 based on the voltage output by the power module 200 reaching the target voltage.
In the case where the chip 100 does not include the power switching unit 170, as shown in fig. 11, the instruction operation unit 110 is electrically connected to the clock generation unit 120, the frequency decision unit 130, and the programmable boost unit 160. The clock generation unit 120 is electrically connected to the programmable boost unit 160 and the performance detection unit 140. The voltage adjustment control unit 150 is electrically connected to the clock generation unit 120, the frequency decision unit 130, the performance detection unit 140, the programmable boost unit 160, and the power module 200 external to the chip 100. The programmable boost unit 160 electrically connects the performance detection unit 140 and the power module 200.
The performance detecting unit 140 is configured to detect a detection voltage corresponding to a target frequency of the target clock signal from the clock generating unit 120 under the excitation of the voltage from the programmable boosting unit 160 or the power supply module 200, and output the detection voltage to the voltage adjustment control unit 150.
The voltage adjustment control unit 150 is configured to output an operating voltage adjustment instruction to the programmable voltage boosting unit 160 based on the detected voltage not reaching the target voltage, the operating voltage adjustment instruction being configured to instruct the programmable voltage boosting unit 160 to adjust the output voltage to the target voltage.
In the case where the chip 100 does not include the performance detecting unit 140 and the power switching unit 170, as shown in fig. 12, the instruction calculating unit 110 is electrically connected to the clock generating unit 120, the frequency deciding unit 130, and the programmable boosting unit 160. The clock generation unit 120 is electrically connected to the programmable boost unit 160. The voltage adjustment control unit 150 is electrically connected to the clock generation unit 120, the frequency decision unit 130, and the programmable boost unit 160. The programmable boost unit 160 is electrically connected to the power module 200 outside the chip 100.
The clock generation unit 120 is configured to generate a target clock signal and a clock signal, output the target clock signal to the instruction operation unit 110, and output the clock signal to the programmable boost unit 160.
The frequency decision unit 130 is configured to calculate a target frequency according to the power demand information from the instruction operation unit 110, and output the target frequency to the voltage adjustment control unit 150.
The voltage adjustment control unit 150 is configured to obtain a corresponding target voltage according to the target frequency, and output a boost control signal to the programmable boost unit 160; and outputting a frequency adjustment instruction to the clock generation unit 120 according to the boosting completion signal from the programmable boosting unit 160, the frequency adjustment instruction being for instructing the clock generation unit 120 to generate the target clock signal.
The programmable boost unit 160 is configured to boost the current voltage of the instruction operation unit 110 to a target voltage according to the boost control signal, and output the target voltage to the instruction operation unit 110.
The embodiments of the present application have been described in detail with reference to the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present application.

Claims (11)

1. The chip is electrically connected with the power supply module and is characterized by comprising an instruction operation unit, a clock generation unit, a frequency decision unit, a voltage adjustment control unit and a programmable boost unit;
the frequency decision unit is electrically connected with the instruction operation unit and is used for: calculating a target frequency according to the calculation power demand information of the instruction operation unit;
the voltage adjustment control unit is electrically connected with the frequency decision unit and the clock generation unit, and is used for: outputting a corresponding boost control signal according to the target frequency and the current voltage of the instruction operation unit based on the target frequency being higher than the current frequency of the instruction operation unit; and controlling the clock generating unit to generate a target clock signal, wherein the working frequency of the target clock signal is the target frequency;
The programmable boost unit is electrically connected with the clock generation unit, the voltage adjustment control unit and the instruction operation unit, and is used for: according to the boost control signal and the clock signal of the clock generation unit, the current voltage is increased to a target voltage corresponding to the target frequency;
the instruction operation unit is electrically connected with the clock generation unit and the programmable boost unit, and is used for: operating based on the target voltage and the target clock signal.
2. The chip of claim 1, wherein the programmable boost unit is further to: outputting a boosting completion signal based on the current voltage boosting to the target voltage;
the voltage adjustment control unit is further configured to: outputting a frequency adjustment instruction according to the boosting completion signal;
the clock generation unit is further configured to: and generating the target clock signal according to the frequency adjustment instruction.
3. The chip of claim 1, wherein the programmable boost unit comprises a switched capacitor circuit comprising a flying capacitor and an output capacitor, a first switch, a second switch, a third switch, a fourth switch, a first voltage comparator, a reference voltage source, and a switch control signal generator;
One end of the flying capacitor is connected between the first switch and the fourth switch, and the other end of the flying capacitor is connected between the second switch and the third switch; the first switch and the third switch are electrically connected to a circuit input end, the second switch is grounded, the fourth switch is connected to a circuit output end, the circuit input end is used for being electrically connected to the power supply module, and the circuit output end is used for being electrically connected to the instruction operation unit; one end of the output capacitor is electrically connected to the output end of the circuit, and the other end of the output capacitor is grounded; a first input end of the first voltage comparator is electrically connected to the circuit output end, a second input end of the first voltage comparator is electrically connected to the reference voltage source, and an output end of the first voltage comparator is electrically connected to the switch control signal generator; the reference voltage source is electrically connected with the voltage adjustment control unit; the switch control signal generator is electrically connected with the first switch, the second switch, the third switch, the fourth switch and the clock generation unit;
the reference voltage source is used for: outputting a reference voltage according to the boost control signal, wherein the difference value between the reference voltage and the target voltage is within a preset value range;
The first voltage comparator is used for: outputting an enabling signal based on the difference value between the output voltage of the circuit output end and the reference voltage exceeding the preset value range;
the switch control signal generator is used for: and according to the enabling signal and the clock signal, the duty ratio of a switch control signal is adjusted, wherein the switch control signal is used for controlling the switch states of the first switch, the second switch, the third switch and the fourth switch, and the switch states comprise on or off.
4. A chip as claimed in claim 3, wherein:
based on the first and second switches being turned off, the third and fourth switches are turned on, the flying capacitor is in a charged state;
based on the first switch and the second switch being turned on, the third switch and the fourth switch being turned off, the flying capacitor is in a discharging state, the flying capacitor charges the output capacitor, and voltages at two ends of the output capacitor are equal to output voltages of the circuit output end.
5. The chip of claim 2, further comprising a power switching unit electrically connected to the voltage regulation control unit, the programmable boost unit, the power module, and the instruction arithmetic unit;
The voltage adjustment control unit is further configured to: outputting a power supply switching instruction according to the boosting completion signal;
the power supply switching unit is used for: outputting a voltage provided by the power supply module based on the voltage output by the programmable boost unit not reaching the target voltage; and outputting the target voltage provided by the programmable boost unit according to the power supply switching instruction.
6. The chip of claim 5, wherein the power switching unit is further to: outputting the target voltage provided by the programmable boost unit based on the voltage output by the power supply module not reaching the target voltage; and outputting a voltage provided by the power supply module based on the voltage output by the power supply module reaching the target voltage.
7. The chip of claim 5, wherein the power switching unit comprises a second voltage comparator, a power switching controller, and a power switching switch;
the first input end of the second voltage comparator is electrically connected to the power supply module, the second input end of the second voltage comparator is electrically connected to the programmable boost unit, and the output end of the second voltage comparator is electrically connected to the power supply change-over switch controller; the power supply change-over switch controller is electrically connected with the power supply change-over switch and the voltage adjustment control unit; one end of the power supply change-over switch is electrically connected to the power supply module or the programmable boost unit, and the other end of the power supply change-over switch is electrically connected to the instruction operation unit;
The second voltage comparator is configured to: outputting a voltage adjustment completion signal based on a difference value between the voltage of the power supply module and the target voltage of the programmable boost unit being within a preset value range;
the power supply changeover switch controller is used for: and outputting a power supply switching signal according to the power supply switching instruction or the voltage adjustment completion signal, wherein the power supply switching signal is used for indicating the power supply switching switch to switch the connecting line.
8. The chip of claim 7, wherein the power switch signal comprises a first power switch signal and a second power switch signal, the power switch controller to:
outputting a first power supply switching signal according to the power supply switching instruction, wherein the first power supply switching signal is used for instructing the power supply switching switch to switch a connecting line between the power supply module and the instruction operation unit into a connecting line between the programmable boost unit and the instruction operation unit; or,
and outputting a second power supply switching signal according to the voltage regulation completion signal, wherein the second power supply switching signal is used for indicating the power supply switching switch to switch a connecting line between the programmable boost unit and the instruction operation unit into a connecting line between the power supply module and the instruction operation unit.
9. The chip of claim 7, wherein the power switching unit further comprises a filter capacitor;
one end of the filter capacitor is electrically connected to the instruction operation unit, and the other end of the filter capacitor is grounded;
the filter capacitor is used for: and supplying power to the instruction operation unit at the moment when the power supply change-over switch changes over the connecting line.
10. The chip of claim 1, wherein the chip further comprises a performance detection unit;
the performance detection unit is electrically connected with the clock generation unit and the voltage adjustment control unit, and the power supply environment of the performance detection unit is the same as that of the instruction operation unit;
the performance detection unit is used for: detecting a detection voltage corresponding to the target frequency based on the target voltage and the target clock signal, and outputting the detection voltage;
the voltage adjustment control unit is further configured to: and outputting an operating voltage adjusting instruction based on that the detected voltage does not reach the target voltage, wherein the operating voltage adjusting instruction is used for instructing the programmable boost unit or the power supply module to adjust the output voltage to the target voltage.
11. An electronic device comprising a power module and a chip as claimed in any one of claims 1 to 10, the chip being electrically connected to the power module.
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