CN204046728U - A kind of multiple DSP system based on video information acquisition process - Google Patents
A kind of multiple DSP system based on video information acquisition process Download PDFInfo
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- CN204046728U CN204046728U CN201420359531.5U CN201420359531U CN204046728U CN 204046728 U CN204046728 U CN 204046728U CN 201420359531 U CN201420359531 U CN 201420359531U CN 204046728 U CN204046728 U CN 204046728U
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Abstract
The utility model relates to a kind of multiple DSP system based on video information acquisition process, comprising: engine control system, FPGA data acquisition memory allocation system, many DSP data handling system and power supply, reset administration module; Described engine control system connects described FPGA data acquisition memory allocation system by synchronous serial interface, described engine control system connects described DSP data handling system by host interface (HPI), and described many DSP data handling system connects described FPGA data acquisition memory allocation system by asynchronous external memory interface (EMIF); Described engine control system, FPGA data acquisition memory allocation system are connected power supply, reset administration module respectively with many DSP data handling system.The utility model is simple and compact for structure, can meet the complex calculation in the fields such as video, has good practical value.
Description
Technical field
The utility model belongs to digital signal processing technique field, is specifically related to a kind of multiple DSP system based on video information acquisition process.
Background technology
At present along with the development of present information application technology, the continuous proposition of digital processing field new theory, there has been swift and violent development in the fields such as the antagonism of scan picture, Radar Signal Processing, software radio, electronic information, computer sim-ulation.The development of information application technique is to the data-handling capacity of present signal processing system, and system data throughput and real-time disposal of multi-tasks ability all create challenge.Single DSP (digital signal processor digitalsignal processor) data handling system cannot meet the requirement of the system needed for present information application technology for information data disposal ability in the signal-data processing system of more complicated.Many DSP information processing system becomes rapidly the basis needed for present information application technical processing with the calculation processing power of its excellence.
Existing multiple DSP system has based on several bus connecting modes such as shared bus, Link, HPI/IDMA, exchanges data, SPORT, pci buss.Wherein often kind has respective pluses and minuses, wherein the connected mode of Based PC I networking bus, needs to utilize the proprietary chip of PCI to set up secondary PCI network, could by multiple DSP carry on network.Such connection makes task processing capability in real time seriously influenced on the one hand, and secondly this kind of connection has networking complicated, needs a large amount of resources for the problem of network operation.Based on the system of exchanges data, its design feature determine to need between every two DSP module DPRAM or two-way FIFO to or the network switch maintain the exchanges data of two dsp systems, its task matching is complicated, exchanges data real-time is low, and DSP connects needs multiple exchanges data material to realize the interconnected of DSP in system.
Utility model content
In order to solve the baroque problem of current multiple DSP system, the utility model provides the multiple DSP system based on video information acquisition process, and this system configuration is simple, compact, has good actual application value.
For achieving the above object, the technical solution of the utility model is:
A kind of multiple DSP system based on video information acquisition process comprises: engine control system, FPGA data acquisition memory allocation system, many DSP data handling system and power supply, reset administration module; Described engine control system connects described FPGA data acquisition memory allocation system by synchronous serial interface, described engine control system connects described DSP data handling system by host interface (HPI), and described many DSP data handling system connects described FPGA data acquisition memory allocation system by asynchronous external memory interface (EMIF); Described engine control system, FPGA data acquisition memory allocation system are connected power supply, reset administration module respectively with many DSP data handling system.
Preferably, described power supply, reset administration module comprise power management module and reset administration module; Described engine control system, FPGA data acquisition memory allocation system, many DSP data handling system and reset administration module are connected with+1.2V the power interface of power management module ,+1.8V power interface ,+3.3V power interface ,+5V power interface respectively according to respective Power supply demand; Described engine control system, FPGA data acquisition memory allocation system, many DSP data handling system pass through the connection of electrification reset interface and a key reseting interface and reset administration module respectively.
Preferably, described engine control system comprises S3C44B0X main control chip, reset circuit, JTAG download debugging interface, extend out Flash, extend out DDRSDRAM, engine control system and FPGA data acquisition memory allocation system command Fabric Interface and engine control system and many DSP data handling system instruction Fabric Interface; Described reset circuit, JTAG download debugging interface, extend out Flash, extend out DDRSD RAM, engine control system is connected with S3C44B0X main control chip with many DSP data handling system instruction Fabric Interface respectively with FPGA data acquisition memory allocation system command Fabric Interface and engine control system; The described Flash that extends out adopts S29AL032D chip, extends out DDRSDRAM and adopts IS6ILV51216 chip; Described engine control system and FPGA data acquisition memory allocation system command Fabric Interface are synchronous serial interface, and described engine control system and many DSP data handling system instruction Fabric Interface are host interface (HPI);
Preferably, described FPGA data acquisition memory allocation system comprises Virtex-5 series A DP1828 chip, reset circuit, JTAG download debugging interface, extends out Flash, data acquisition front, engine control system and FPGA data acquisition distribution system instruction Fabric Interface, FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface; Described reset circuit, JTAG download debugging interface, extend out Flash, data acquisition front, machine control system and FPGA data acquisition distribution system instruction Fabric Interface, FPGA data acquisition distribution system is all connected with Virtex-5 series A DP1828 chip with many DSP data handling system instruction Fabric Interface; Described data acquisition front adopts TVP5150PBS video decoding chip; Described FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface are asynchronous external memory interface (EMIF);
Preferably, described many DSP data handling system is made up of four identical DSP data process subsystems and JTAG daisy chain debugging interface, each DSP data process subsystem comprises TMS320DM6437 data processing chip, reset circuit, the synchronous static data memory of DDR2, engine control system and DSP data handling unit (DHU) assembly instruction Fabric Interface and FPGA data acquisition memory allocation system and many DSP data handling system instruction Fabric Interface; In each DSP data process subsystem, the synchronous static data memory of described reset circuit, DDR2, engine control system are all connected with TMS320DM6437 data processing chip with many DSP data handling system instruction Fabric Interface with DSP data handling unit (DHU) assembly instruction Fabric Interface, FPGA data acquisition memory allocation system; Described JTAG daisy chain debugging interface is connected with the TMS320DM6437 data processing chip in each DSP data process subsystem; Connected by share host interface (HPI) between described DSP data process subsystem, the synchronous static data memory of described DDR2 is for form 32 bit synchronization data storages by two panels MT47H64M16BT chip; Described JTAG daisy chain debugging interface is the daisy chain structure adopting the SN74LVT8986 chip of TI to build serial mode, for the debugging of many DPS system.
Preferably, described power supply, reset administration module comprise power management module and reset administration module; Described power management module comprises the circuit of the supervision power source change adopting TLC7733, TLC7725, TPS3707 chip to build, peripheral circuit is coordinated to produce+1.2V power supply ,+1.8V power supply ,+3.3V power supply ,+5V power supply, for the power demands of each system, supply power voltage produces reset signal lower than controlling during threshold values; Described reset administration module forms reset circuit by providing TPS3808, TPS3350 chip of required reset signal for system, for whole system provides electrification reset interface, a key reseting interface, low-voltage reset interface.
Relative to prior art, the beneficial effects of the utility model are: structure is more simple, compact.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the utility model based on the multiple DSP system of video information acquisition process;
Fig. 2 is the structural representation of the utility model based on the multiple DSP system of video information acquisition process;
Fig. 3 is the structural representation of engine control system;
Fig. 4 is the structural representation of FPGA data acquisition memory allocation system;
Fig. 5 is the structural representation of many DSP data handling system;
Fig. 6 is the structural representation of power supply, reset administration module.
In figure, 1-engine control system, 101-S3C44B0X main control chip, 102-reset circuit, 103-JTAG downloads debugging interface, 104-extends out Flash, 105-extends out DDR SDRAM, 106-engine control system and FPGA data acquisition memory allocation system command Fabric Interface, 107-engine control system and many DSP data handling system instruction Fabric Interface, 2-FPGA data acquisition memory allocation system, 201-ADP1828 chip, 202-data acquisition front, 203-FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface, 3-many DSP data handling system, 301-TMS320DM6437 data processing chip, 302-JTAG daisy chain debugging interface, the synchronous static data memory of 303-DDR2, 4-power supply, reset administration module, 401-power management module, 402-reset administration module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is elaborated:
As shown in Figure 1, a kind of multiple DSP system based on video information acquisition process of the utility model comprises engine control system 1, FPGA data acquisition memory allocation system 2, many DSP data handling system 3 and power supply, reset administration module 4.Engine control system 1 connects FPGA data acquisition memory allocation system 2 by synchronous serial interface, engine control system 1 connects described DSP data handling system 3, many DSP data handling system 3 by host interface (HPI) and connects FPGA data acquisition memory allocation system 2 by asynchronous external memory interface (EMIF); Described engine control system 1, FPGA data acquisition memory allocation system 2 are connected power supply, reset administration module 4 respectively with many DSP data handling system 3.
As shown in Figure 2, power supply, reset administration module 4 comprise power management module 401 and reset administration module 402; Engine control system 1, FPGA data acquisition memory allocation system 2, many DSP data handling system 3 and reset administration module 402 are connected with+1.2V the power interface of power management module 401 ,+1.8V power interface ,+3.3V power interface ,+5V power interface respectively according to respective Power supply demand; Engine control system 1, FPGA data acquisition memory allocation system 2, many DSP data handling system 3 pass through the connection of electrification reset interface and a key reseting interface and reset administration module respectively.
In whole video information acquisition process multiple DSP system, engine control system 1 is in the hub location of system, be responsible for the control realizing starting the regulating and controlling of FPGA data acquisition memory allocation system 2 and the task matching of many DSP data handling system 3, play the effect of integrated scheduling, an adjustment to system when also taking into account detection and the system generation run-time error of system cloud gray model mistake, engine control system 1 sends instruction control word in task free time, this instruction control word is responded to engine control system after the instruction control word that each system acceptance sends to main frame, so that engine control system 1 confirms the running status of each system, when system cloud gray model makes a mistake, engine control system is responsible for confirming system mistake state and is taked the mode recovered or reset to recover this mistake.FPGA data acquisition memory allocation system 2 plays the effect of data acquisition memory allocation; Many DSP data handling system 3 is the main core of whole system algorithm process; Power supply, reset administration module 4 run for whole system and provide necessary power supply signal and reset signal.
As shown in Figure 3, engine control system 1 comprises S3C44B0X main control chip 101, reset circuit 102, JTAG download debugging interface 103, extend out Flash104, extend out DDR SD RAM105, engine control system and FPGA data acquisition memory allocation system command Fabric Interface 106 and engine control system and many DSP data handling system instruction Fabric Interface 107; Reset circuit 102, JTAG download debugging interface 103, extend out Flash104, extend out DDR SD RAM105, engine control system is all connected with S3C44B0X main control chip 101 with many DSP data handling system instruction Fabric Interface 107 with FPGA data acquisition memory allocation system command Fabric Interface 106 and engine control system; Extend out Flash104 and adopt S29AL032D chip, extend out DDRSD RAM105 and adopt IS6ILV51216 chip; Engine control system and FPGA data acquisition memory allocation system command Fabric Interface 106 are synchronous serial interface, and engine control system and many DSP data handling system instruction Fabric Interface 107 are host interface (HPI); Wherein, reset circuit 102 provides power-on reset signal, hot reset signal, hand-reset signal for engine control system 1.JTAG downloads debugging interface 103 and downloads for the debugging of engine control system 1 and source code.Extend out Flash104 and run required code, data and for the dsp system code data needed for many DSP data handling system 2 initialization for depositing engine control system 1, extend out the operation of DDRSD RAM105 for engine control system 1 program and the storage of data.
As shown in Figure 4, FPGA data acquisition memory allocation system 2 comprises Virtex-5 series A DP1828 chip 201, reset circuit 102, JTAG download debugging interface 103, extend out Flash104, data acquisition front 202, engine control system and FPGA data acquisition distribution system instruction Fabric Interface 106 and FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface 203; Reset circuit 102, JTAG download debugging interface 103, extend out Flash104, data acquisition front 202, machine control system and FPGA data acquisition distribution system instruction Fabric Interface 106, FPGA data acquisition distribution system are all connected with Virtex-5 series A DP1828 chip 201 with many DSP data handling system instruction Fabric Interface 203; Data acquisition front 202 adopts TVP5150PBS video decoding chip; FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface 203 are asynchronous external memory interface (EMIF); Wherein, reset circuit 102 provides reset signal for FPGA data acquisition memory allocation system 2.JTAG downloads debugging interface 103 and downloads for the debugging of FPGA data acquisition memory allocation system 3 and source code.Extending out Flash is FPGA data acquisition memory allocation system 3 providing source code memory space.Data acquisition front 202 is responsible for the collection of image/video information, uses TVP5150PBS video decoding chip to decoding video signal collection.
As shown in Figure 5, many DSP data handling system 3 is made up of four identical DSP data process subsystems and JTAG daisy chain debugging interface 302, and each DSP data process subsystem comprises TMS320DM6437 data processing chip 301, reset circuit 102, the synchronous static data memory 303 of DDR2, engine control system and DSP data handling unit (DHU) assembly instruction Fabric Interface 107 and FPGA data acquisition memory allocation system and many DSP data handling system instruction Fabric Interface 203; In each DSP data process subsystem, the synchronous static data memory 303 of reset circuit 102, DDR2, engine control system are all connected with TMS320DM6437 data processing chip 301 with many DSP data handling system instruction Fabric Interface 203 with DSP data handling unit (DHU) assembly instruction Fabric Interface 107, FPGA data acquisition memory allocation system; JTAG daisy chain debugging interface 302 is connected with the TMS320DM6437 data processing chip 301 in each DSP data process subsystem; Connected by share host interface (HPI) between each DSP data process subsystem, and the exchange of Interface realization Large Volume Data by being connected with FPGA data acquisition memory allocation system 2.The synchronous static data memory 303 of DDR2 is for form 32 bit synchronization data storages by two panels MT47H64M16BT chip; Described JTAG daisy chain debugging interface is the daisy chain structure adopting the SN74LVT8986 chip of TI to build serial mode, for the debugging of many DPS system.
As shown in Figure 6, power supply, reset administration module 4 comprise power management module 401 and reset administration module 402; Described power management module 401 comprises the circuit of the supervision power source change adopting TLC7733, TLC7725, TPS3707 chip to build, peripheral circuit is coordinated to produce+1.2V power supply ,+1.8V power supply ,+3.3V power supply ,+5V power supply, for the power demands of each system, supply power voltage produces reset signal lower than controlling during threshold values; Described reset administration module 402 forms reset circuit by providing TPS3808, TPS3350 chip of required reset signal for system, for whole system provides electrification reset interface, a key reseting interface, low-voltage reset interface.
Operation principle of the present utility model is as follows:
System electrification starts, and engine control system 1 and FPGA data acquisition memory allocation system 2 start respectively, and Booting sequence separately required code is directed to chip RAM and extends out DDR SDRAM runs from extending out Flash, the initialization of completion system.Suspended state is in after wherein FPGA data acquisition memory allocation system 2 completes initializes itself.Engine control system 1 starts after initialization completes, the initialize flow to many DSP data handling system 3 is realized by host interface (HPI), first from extending out Flash memory space, the setup code of required many DSP data handling system 3 is copied to running memory unit, then be transferred to DSP internal storage location by host interface (HPI) and complete initialization to many DSP data handling system 3, the advantage of such design is when selected DSP type is the same, setup code may repeat, realize initialization by engine control system 1 couple of DSP and can reduce depositing of duplicated code, save memory space, engine control system 1 is also responsible for carrying out the division of task and the transmission of task parameters and task initialization to many DSP data handling system 3, after engine control system 1 completes the initialization to DSP, many DSP data handling system 3 is also in a kind of suspended state.
The initialized effect of FPAG data acquisition memory allocation system 2 is input interface partial interior logical block being defined as data acquisition, and a part of internal logic resources definition soft kernel is used for exchanging control command to the management and utilization of FPGA resource and main frame by serial data interface in addition.Wherein key is the shared internal data storage unit pond of more than mouthful by internal logic resources definition, wherein input interface is designed to be connected with data acquisition interface by soft kernel, and output interface is divided into four data transmission interfaces compatible mutually with the asynchronous external memory interface of DSP (EMIF) interface that are that can simultaneously operate.
After engine control system 1 completes and completes the initialization of DSP hardware resource and the initialization of computing task division, engine control system 1 gathers original information data by synchronous serial interface transmission command notice FPGA data acquisition memory allocation system 2, in gatherer process, image data is left respectively in the assigned address of shared internal data storage unit by the processing requirements of specifying, after data acquisition, via host interface (HPI), FPGA data acquisition memory allocation system 2 notifies that many DSP data handling system 3 is shared data in internal storage unit to fetch being left FPGA in via asynchronous external memory interface (EMIF) and leave in the synchronous static data memory 303 of DDR2 with by engine control system 1, after data batchmove completes, each DSP data process subsystem starts to carry out computing according to a point pairing image data for task.After having processed, data are transferred to via asynchronous external memory interface (EMIF) the memory address unit place that FPGA shares internal data storage unit event memory.Engine control system 1 adds up the situation about completing of each DSP data process subsystem through host interface (HPI), and all DSP data process subsystems all process terminate the acquisition process that aft engine is responsible for notifying beginning second frame data.
Meanwhile, engine control system 1 sends instruction control word in task free time, responds this instruction control word to engine control system, so that engine control system 1 confirms the running status of each system after the instruction control word that each system acceptance sends to main frame; When system cloud gray model makes a mistake, engine control system is responsible for confirming system mistake state and is taked the mode recovered or reset to recover this mistake.
The utility model mainly adopts existing chip, and the software of chip is all existing software, and its functional realiey is that setting operation order realizes on existing software, do not improve software itself, and the utility model structure is the improvement to existing structure.The utility model is in the process run, maximization and the real-time of operation can be realized calculating by carrying out task division to each system, meet the complex calculation in the fields such as video, and each system comprises respective JTAG downloads debugging interface, makes each system can realize respective debug function alone in the debug phase.The JTAG daisy chain of many DSP data handling system 3 connects the debugging that can realize multiple DSP.Such design can be carried out controlledly debugging intuitively to the operation of DSP in task algorithmic dispatching operation etc., more efficient and convenient.Above each several part composition adopts existing equipment chip, as long as function can realize function of the present utility model.Software is wherein device chip and carries, and only needs to carry out instruction layout according to chip functions mode of operation.
The above is only preferred implementation of the present utility model; be noted that for those skilled in the art; under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (6)
1. the multiple DSP system based on video information acquisition process, it is characterized in that, comprising: engine control system (1), FPGA data acquisition memory allocation system (2), many DSP data handling system (3) and power supply, reset administration module (4); Described engine control system (1) connects described FPGA data acquisition memory allocation system (2) by synchronous serial interface, described engine control system (1) connects described DSP data handling system (3) by host interface (HPI), and described many DSP data handling system (3) connects described FPGA data acquisition memory allocation system (2) by asynchronous external memory interface (EMIF); Described engine control system (1), FPGA data acquisition memory allocation system (2) and many DSP data handling system (3) are connected power supply, reset administration module (4) respectively.
2. according to the multiple DSP system based on video information acquisition process a kind of described in claim 1, it is characterized in that, described power supply, reset administration module (4) comprise power management module (401) and reset administration module (402); Described engine control system (1), FPGA data acquisition memory allocation system (2), many DSP data handling system (3) and reset administration module (402) are connected with+1.2V the power interface of power management module (401) ,+1.8V power interface ,+3.3V power interface ,+5V power interface respectively according to respective Power supply demand; Described engine control system (1), FPGA data acquisition memory allocation system (2), many DSP data handling system (3) pass through the connection of electrification reset interface and a key reseting interface and reset administration module (402) respectively.
3. the multiple DSP system based on video information acquisition process according to claim 1, it is characterized in that, described engine control system (1) comprises S3C44B0X main control chip (101), reset circuit (102), JTAG download debugging interface (103), extend out Flash (104), extend out DDR SDRAM (105), engine control system and FPGA data acquisition memory allocation system command Fabric Interface (106) and engine control system and many DSP data handling system instruction Fabric Interface (107); Described reset circuit (102), JTAG download debugging interface (103), extend out Flash (104), extend out DDR SDRAM (105), engine control system is connected with S3C44B0X main control chip (101) with many DSP data handling system instruction Fabric Interface (107) respectively with FPGA data acquisition memory allocation system command Fabric Interface (106) and engine control system; The described Flash (104) that extends out adopts S29AL032D chip, described in extend out DDRSD RAM (105) and adopt IS6ILV51216 chip; Described engine control system and FPGA data acquisition memory allocation system command Fabric Interface (106) are synchronous serial interface, and described engine control system and many DSP data handling system instruction Fabric Interface (107) are host interface (HPI).
4. the multiple DSP system based on video information acquisition process according to claim 1, it is characterized in that, FPGA data acquisition memory allocation system (2) comprises Virtex-5 series A DP1828 chip (201), reset circuit (102), JTAG download debugging interface (103), extends out Flash (104), data acquisition front (202), engine control system and FPGA data acquisition distribution system instruction Fabric Interface (106), FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface (203); Described reset circuit (102), JTAG download debugging interface (103), extend out Flash (104), data acquisition front (202), machine control system are connected with Virtex-5 series A DP1828 chip (201) with many DSP data handling system instruction Fabric Interface (203) respectively with FPGA data acquisition distribution system instruction Fabric Interface (106) and FPGA data acquisition distribution system; Described data acquisition front (202) adopts TVP5150PBS video decoding chip; Described FPGA data acquisition distribution system and many DSP data handling system instruction Fabric Interface (203) are asynchronous external memory interface (EMIF).
5. the multiple DSP system based on video information acquisition process according to claim 1, it is characterized in that, described many DSP data handling system (3) is made up of four identical DSP data process subsystems and JTAG daisy chain debugging interface (302), each DSP data process subsystem comprises TMS320DM6437 data processing chip (301), reset circuit (102), the synchronous static data memory (303) of DDR2, engine control system and DSP data handling unit (DHU) assembly instruction Fabric Interface (107) and FPGA data acquisition memory allocation system and many DSP data handling system instruction Fabric Interface (203), in each DSP data process subsystem, the synchronous static data memory (303) of described reset circuit (102), DDR2, engine control system are all connected with TMS320DM6437 data processing chip (301) with many DSP data handling system instruction Fabric Interface (203) with DSP data handling unit (DHU) assembly instruction Fabric Interface (107), FPGA data acquisition memory allocation system, described JTAG daisy chain debugging interface (302) is connected with the TMS320DM6437 data processing chip (301) in each DSP data process subsystem, connected by share host interface (HPI) between each DSP data process subsystem, the synchronous static data memory (303) of described DDR2 is for form 32 bit synchronization data storages by two panels MT47H64M16BT chip, described JTAG daisy chain debugging interface is the daisy chain structure adopting the SN74LVT8986 chip of TI to build serial mode, for the debugging of many DPS system.
6. the multiple DSP system based on video information acquisition process according to claim 2, it is characterized in that, described power management module (401) comprises the circuit of the supervision power source change adopting TLC7733, TLC7725, TPS3707 chip to build, peripheral circuit is coordinated to produce+1.2V power supply ,+1.8V power supply ,+3.3V power supply ,+5V power supply, for the power demands of each system, supply power voltage produces reset signal lower than controlling during threshold values; Described reset administration module (402) forms reset circuit by providing TPS3808, TPS3350 chip of required reset signal for system, for whole system provides electrification reset interface, a key reseting interface, low-voltage reset interface.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106454280A (en) * | 2016-12-03 | 2017-02-22 | 河池学院 | H.264 based network video transmission system |
| CN114374243A (en) * | 2021-12-22 | 2022-04-19 | 南京安广电力设备有限公司 | Energy storage battery control device and method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106454280A (en) * | 2016-12-03 | 2017-02-22 | 河池学院 | H.264 based network video transmission system |
| CN106454280B (en) * | 2016-12-03 | 2023-05-30 | 河池学院 | Method for video transmission based on H.264 network video transmission system |
| CN114374243A (en) * | 2021-12-22 | 2022-04-19 | 南京安广电力设备有限公司 | Energy storage battery control device and method |
| CN114374243B (en) * | 2021-12-22 | 2024-02-23 | 南京安广电力设备有限公司 | Energy storage battery control device and method |
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