CN105608039A - FIFO and ARINC659 bus based dual-redundancy computer period control system and method - Google Patents
FIFO and ARINC659 bus based dual-redundancy computer period control system and method Download PDFInfo
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- CN105608039A CN105608039A CN201510917933.1A CN201510917933A CN105608039A CN 105608039 A CN105608039 A CN 105608039A CN 201510917933 A CN201510917933 A CN 201510917933A CN 105608039 A CN105608039 A CN 105608039A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
- G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
Abstract
The invention relates to an FIFO and ARINC659 bus based dual-redundancy computer period control system and method. An ARINC659 bus is adopted to replace a conventional synchronous and channel cross transmission framework, and the system coupling degree is increased to tight coupling from loose coupling. Meanwhile, the hardware design of FIFO is adopted, so that the task time division of a task period is optimized, the task time determinacy is improved, and the workload of a main processor is released. The technical problem of difference in each task execution time of each system period in an existing airborne redundancy computer is solved. The dual-redundancy airborne computer period control system and method have high reliability and high determinacy.
Description
Technical field
The invention belongs to aircraft aviation airborne electronic equipment system field, relate to and solve two airborne calculating of remainingThe close-coupled degree of the time determinability of the duty cycle of machine and synchronous working.
Background technology
The airborne remaining computer that adopts synchronous operation, the information interaction between passage is handed over by designated laneFork data transmission link carries out (hereinafter to be referred as CCDL). Systems soft ware moves within the official hour cycle,This cycle is called system cycle (or frame), remaining computer be synchronously divided into two-stage: one-level is system cycleSynchronously, another level is tasks synchronization. System cycle synchronously refers to start at each system cycle, and institute has a surplusDegree passage uses synchronous circuit to carry out simultaneously operating, guarantees that each system cycle starts from same time referencePoint; Tasks synchronization is to guarantee that each remaining passage carries out same task at synchronization, and tasks synchronization makes equallyCarry out synchronously with synchronous circuit. Using the time asynchronous degree≤50 μ s of the each remaining passage of synchronous circuit, is a kind ofLoose coupling synchronization policy. Concrete implementation as shown in Figure 1.
Settling signal collection and processing in each system cycle, control law calculate and instruction output, monitoring andRedundancy management. Remaining channel resource (bus, analog quantity, discrete magnitude) is managed by application specific processorReason, passage primary processor completes information interaction with application specific processor by sharing storage (dual port RAM).Application specific processor is responsible for the transmitting-receiving of bus data, and the collection output of analog quantity discrete magnitude, at application specific processorMiddle operation subcycle task, the system task cycle is the exponential of subtask cycle. Each remaining passage is to moneyObtaining by access dual port RAM of source information undertaken, each resource information obtain by application specific processorSubtask cycle image data, there is asynchronous degree with the subtask cycle in the system task execution of remaining passage,Cause the each task execution time in each system cycle all to there are differences. And then cause in system cycle eachTime uncertainty in tasks carrying.
Summary of the invention
For the each task execution time that solves each system cycle in existing airborne remaining computer is all depositedIn the technical problem of difference, the invention provides a kind of two remaining meters based on FIFO and ARINC659 busCalculation machine periodic Control system and method, simplifies duty cycle, has strengthened the time determinability of periodic duty,Realized the close coupling synchronous working mode between two remaining computer access simultaneously.
Technical solution of the present invention:
Based on two remaining computer periodic Control systems for FIFO and ARINC659 bus, it is specialPart is: comprise command channel, monitor channel and fault logic treatment circuit CFL, command channel withMonitor channel structure is identical, and described command channel comprises CPU, external interface and multiple FIFO, described outsidePortion's interface is connected with CPU by the FIFO of corresponding kind, and the CPU in described command channel and monitoring are logicalCPU in road connects by ARINC659 bus.
External interface comprises AIN, DIN, AOUT, DOUT and SYS-BUS, AIN interface withFIFO/REG connect, DIN is connected with FIFO/REG, AOUT is connected with FIFO, DOUT andFIFO/REG connects, and SYS-BUS is connected with FIFO.
Based on two remaining computer periodic Control methods for FIFO and ARINC659 bus, comprise withLower step:
1) set up bus task list: the periodic duty that will carry out according to CPU, set up bus task list;
2) initialize:
ARINC659 bus initialization load bus task list;
External interface mode of operation is configured to possess to the mode of operation of FIFO buffer memory;
3) ARINC659 bus starts according to CPU in bus task list control command passage, monitor channelAfter, CPU starts execution cycle task; The periodic duty that ARINC659 bus is carried out according to CPU simultaneouslyCarry out synchronous or time delay command;
4) CPU prepares data: the data that gathered are put into corresponding FIFO, CPU by external interfaceDirect reading out data from corresponding FIFO;
5) CPU receives and in bus task list, intersects transformation task, and CPU writes the data of preparationARINC659 bus data memory block;
6) CPU continues execution cycle task, between command channel and monitor channel CPU, passes throughARINC659 synchronization mechanism completes synchronous between CPU;
7) CPU receives and in bus task list, intersects transformation task, and CPU is from ARINC659 number of busesTransmit data according to reading in memory block to intersect;
8) CPU executing data processing, calculating and fault distinguishing task, by final external interface outputData write in corresponding FIFO;
9) CPU continues execution cycle task, between command channel and monitor channel CPU, passes through ARINC659Synchronization mechanism completes synchronous between CPU;
10) CPU receives task end mark in bus task list; Execution step 3.
External interface comprises AIN, DIN, AOUT, DOUT and SYS-BUS, AIN interface withFIFO/REG connect, DIN is connected with FIFO/REG, AOUT is connected with FIFO, DOUT andFIFO/REG connects, and SYS-BUS is connected with FIFO.
Advantage of the present invention is:
1, the present invention adopts ARINC659 bus to replace conventional synchronization and passage intersection transmission architecture, adoptsTime triggering synchronous working method based on ARINC659 bus table, bus provides synchronized algorithm to guaranteeAsynchronous degree≤20 μ s between node is that one has tightly coupled system structure.
2. in the each channel hardware of remaining computer of the present invention, utilize FIFO as system task Gains resourcesCarrier, has optimized the task time of duty cycle and has divided, and makes system cycle tasks carrying have the strong timeCertainty, has discharged the service load of primary processor.
Brief description of the drawings
Fig. 1 is that existing system cycle and duty cycle synchronous and CCDL circuit and application specific processor are dividedKey diagram;
Fig. 2 is system construction drawing of the present invention;
Fig. 3 is system cycle of the present invention and duty cycle partition description figure.
Detailed description of the invention
Below the present invention is described in further details.
As shown in Figure 2, a kind of two remaining computer periodic Control based on FIFO and ARINC659 busSystem, comprises command channel, monitor channel and fault logic treatment circuit CFL, command channel and monitoringChannel design is identical, and command channel comprises CPU, external interface and multiple FIFO, and external interface is by rightAnswer the FIFO of kind to be connected with CPU, the CPU in CPU and monitor channel in described command channelConnect by ARINC659 bus.
External interface comprises AIN, DIN, AOUT, DOUT and SYS-BUS, AIN interface withFIFO/REG connect, DIN is connected with FIFO/REG, AOUT is connected with FIFO, DOUT andFIFO/REG connects, and SYS-BUS is connected with FIFO. Logical between command channel and monitor channel CPUCross ARINC659 bus mechanism and complete synchronously, CPU is reference to storage behaviour to obtaining of all dataDo (FIFO or ARINC659_RAM), discharged the load of CPU, allow CPU be absorbed in the processing of dataOn calculating.
Autopilot computer (hereinafter to be referred as AFCC), adopts double-redundancy fault-tolerant computer framework. LogicalSynchronous and intersection transmission between road adopts ARINC659 bus to realize. Its height of ARINC659 bus canGuarantee the reliable in real time of intersection transmission by property and hard real-time. In AFCC, each remaining passage is by system cycleTask combines with ARINC659 bus line command table, and bus line command table is that ARINC659 bus is carried outTime series, in bus, two passage nodes are carried out according to the time-event of command list defined, command listIn synchronizing information frame to complete the close coupling of bus synchronous. Adopt this backplane bus, will substitute former synchronousCircuit and CCDL circuit are write bus line command table according to the system task cycle simultaneously, make whole pair of remainingComputer working is under ARINC659 bus table system cycle, and the time, asynchronous degree was controlled at clock level.
Each remaining passage utilizes FIFO in hardware design simultaneously, and each remaining passage resource is passed through to FIFOMutual with primary processor; The use of FIFO has solved remaining passage duty cycle tasks carrying with each number of resourcesAccording to speed difference problem, system task carry out without consider share storage race problem, without considerationOwing to inquiring about the loss problem of bus data (being less than 10Mbps) not in time, during without consideration resource accessBetween uncertainty, discharged task processing time of processor, improve processor efficiency.
Referring to Fig. 3, based on two remaining computer periodic Control methods of FIFO and ARINC659 bus,Comprise the following steps:
1) set up bus task list: the periodic duty that will carry out according to CPU, set up bus task list;
2) initialize:
ARINC659 bus initialization load bus task list;
External interface mode of operation is configured to possess to the mode of operation of FIFO buffer memory;
3) ARINC659 bus starts according to CPU in bus task list control command passage, monitor channelAfter, CPU starts execution cycle task; The periodic duty that ARINC659 bus is carried out according to CPU simultaneouslyCarry out synchronous or time delay command;
4) CPU prepares data: CPU direct reading out data from corresponding FIFO;
5) CPU receives and in bus task list, intersects transformation task, and CPU writes the data of preparationARINC659 bus data memory block;
6) CPU continues execution cycle task;
7) CPU receives and in bus task list, intersects transformation task, and CPU is from ARINC659 number of busesTransmit data according to reading in memory block to intersect;
8) CPU executing data processing, calculating and fault distinguishing task, by final external interface outputData write in corresponding FIFO;
9) CPU continues execution cycle task, between command channel and monitor channel CPU, passes through ARINC659Synchronization mechanism completes synchronous between CPU;
10) CPU receives task end mark in bus task list; Execution step 3.
In remaining passage, primary processor passes through access phase to the access of bus (being less than 10Mbps) interface resourceThe FIFO space of answering completes. Processor, in its duty cycle, is carried out corresponding task, only needs correspondingWhether the FIFO space of resource completes read data or data writing operation, and connect in time without paying close attention to bus dataReceive, whether because the distribution inequality of duty cycle causes obliterated data, to analog quantity (hereinafter to be referred as AIN)The access of discrete magnitude (hereinafter to be referred as DIN) is by the corresponding FIFO of access (AIN and DIN in inventionFIFO size be 1, can be regarded as REG register) obtain, and data immediate updating in FIFO,Renewal frequency is the exponential of system cycle time; It is right that the system task time of implementation of remaining passage is controlled atFIFO access time rank, according to there being strong time determinability;
ARINC659 bus is due to the fault-tolerant and high reliability of himself, ensured interchannel transfer of dataAccuracy, the synch command in bus line command table has ensured the close coupling degree that interchannel is synchronous; SynchronouslySpread out of completely and completed in real time by ARINC659 with intersection. Appointing of the cycle of bus line command table and primary processorBusiness cycle close-coupled, ARINC659 bus table interrupt signal is initial as system cycle, total by inciting somebody to actionLine command list is divided into different timeslices, and the different task of the corresponding duty cycle of each timeslice, completesThe hard real time certainty of the synchronous and tasks carrying of the clock level of whole pair of redundant system task.
Claims (4)
1. the two remaining computer periodic Control systems based on FIFO and ARINC659 bus, itsBe characterised in that: comprise command channel, monitor channel and fault logic treatment circuit CFL, command channel withMonitor channel structure is identical, and described command channel comprises CPU, external interface and multiple FIFO, described outsidePortion's interface is connected with CPU by the FIFO of corresponding kind, and the CPU in described command channel and monitoring are logicalCPU in road connects by ARINC659 bus.
2. the two remaining computers based on FIFO and ARINC659 bus according to claim 1Periodic Control system, is characterized in that: external interface comprise AIN, DIN, AOUT, DOUT andSYS-BUS, AIN interface is connected with FIFO/REG, DIN is connected with FIFO/REG, AOUT withFIFO connects, and DOUT is connected with FIFO/REG, and SYS-BUS is connected with FIFO.
3. the two remaining computer periodic Control methods based on FIFO and ARINC659 bus, itsBe characterised in that: comprise the following steps:
1) set up bus task list: the periodic duty that will carry out according to CPU, set up bus task list;
2) initialize:
ARINC659 bus initialization load bus task list;
External interface mode of operation is configured to possess to the mode of operation of FIFO buffer memory;
3) ARINC659 bus starts according to CPU in bus task list control command passage, monitor channelAfter, CPU starts execution cycle task; The periodic duty that ARINC659 bus is carried out according to CPU simultaneouslyCarry out synchronous or time delay command;
4) CPU prepares data: the data that gathered are put into corresponding FIFO, CPU by external interfaceDirect reading out data from corresponding FIFO;
5) CPU receives and in bus task list, intersects transformation task, and CPU writes the data of preparationARINC659 bus data memory block;
6) CPU continues execution cycle task, between command channel and monitor channel CPU, passes throughARINC659 synchronization mechanism completes synchronous between CPU;
7) CPU receives and in bus task list, intersects transformation task, and CPU is from ARINC659 number of busesTransmit data according to reading in memory block to intersect;
8) CPU executing data processing, calculating and fault distinguishing task, by final external interface outputData write in corresponding FIFO;
9) CPU continues execution cycle task, between command channel and monitor channel CPU, passes through ARINC659Synchronization mechanism completes synchronous between CPU;
10) CPU receives task end mark in bus task list; Execution step 3.
4. the two remaining computers based on FIFO and ARINC659 bus according to claim 3Periodic Control method, is characterized in that: external interface comprise AIN, DIN, AOUT, DOUT andSYS-BUS, AIN interface is connected with FIFO/REG, DIN is connected with FIFO/REG, AOUT withFIFO connects, and DOUT is connected with FIFO/REG, and SYS-BUS is connected with FIFO.
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| CN201510917933.1A CN105608039B (en) | 2015-12-10 | 2015-12-10 | A kind of double redundancy computer cycle control system and method based on FIFO and ARINC659 bus |
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| CN201510917933.1A CN105608039B (en) | 2015-12-10 | 2015-12-10 | A kind of double redundancy computer cycle control system and method based on FIFO and ARINC659 bus |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108228403A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | The redundancy management circuit and management method of a kind of redundant fault-tolerant computer system |
| CN108234260A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of task synchronization method based on ARINC659 buses |
| CN109104386A (en) * | 2018-09-04 | 2018-12-28 | 中国铁道科学研究院集团有限公司通信信号研究所 | A kind of timing transmission method of big data quantity communication |
| CN112644690A (en) * | 2020-11-05 | 2021-04-13 | 中国航空工业集团公司西安航空计算技术研究所 | Data cross transmission system of actuator control computer |
| CN114356828A (en) * | 2021-12-23 | 2022-04-15 | 中国航空工业集团公司西安航空计算技术研究所 | Method for asynchronous cross transmission between double-redundancy flight control computers |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030152182A1 (en) * | 2000-08-22 | 2003-08-14 | Pai B. Anand | Optical exchange method, apparatus and system for facilitating data transport between WAN, SAN and LAN and for enabling enterprise computing into networks |
| CN102541697A (en) * | 2010-12-31 | 2012-07-04 | 中国航空工业集团公司第六三一研究所 | Switching method for processing fault of dual-redundancy computer |
-
2015
- 2015-12-10 CN CN201510917933.1A patent/CN105608039B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030152182A1 (en) * | 2000-08-22 | 2003-08-14 | Pai B. Anand | Optical exchange method, apparatus and system for facilitating data transport between WAN, SAN and LAN and for enabling enterprise computing into networks |
| CN102541697A (en) * | 2010-12-31 | 2012-07-04 | 中国航空工业集团公司第六三一研究所 | Switching method for processing fault of dual-redundancy computer |
Non-Patent Citations (3)
| Title |
|---|
| 张锐 等: "ARINC659 总线在飞控余度管理技术中的应用", 《航空计算技术》 * |
| 汪迪娜 等: "ARINC659总线监控卡的设计与实现", 《微电子学与计算机》 * |
| 罗建珍 等: "双余度飞控计算机的设计与实现", 《航空计算技术》 * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108228403A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | The redundancy management circuit and management method of a kind of redundant fault-tolerant computer system |
| CN108234260A (en) * | 2016-12-14 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of task synchronization method based on ARINC659 buses |
| CN108234260B (en) * | 2016-12-14 | 2020-11-13 | 中国航空工业集团公司西安航空计算技术研究所 | Task synchronization method based on ARINC659 bus |
| CN109104386A (en) * | 2018-09-04 | 2018-12-28 | 中国铁道科学研究院集团有限公司通信信号研究所 | A kind of timing transmission method of big data quantity communication |
| CN109104386B (en) * | 2018-09-04 | 2021-02-19 | 中国铁道科学研究院集团有限公司通信信号研究所 | Time-sharing transmission method for large data volume communication |
| CN112644690A (en) * | 2020-11-05 | 2021-04-13 | 中国航空工业集团公司西安航空计算技术研究所 | Data cross transmission system of actuator control computer |
| CN112644690B (en) * | 2020-11-05 | 2023-10-20 | 中国航空工业集团公司西安航空计算技术研究所 | Data cross transmission system of actuator control computer |
| CN114356828A (en) * | 2021-12-23 | 2022-04-15 | 中国航空工业集团公司西安航空计算技术研究所 | Method for asynchronous cross transmission between double-redundancy flight control computers |
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