CN204043235U - A kind of multilevel semiconductor thermoelectric cooling assembly - Google Patents
A kind of multilevel semiconductor thermoelectric cooling assembly Download PDFInfo
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- CN204043235U CN204043235U CN201420508779.3U CN201420508779U CN204043235U CN 204043235 U CN204043235 U CN 204043235U CN 201420508779 U CN201420508779 U CN 201420508779U CN 204043235 U CN204043235 U CN 204043235U
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Abstract
The utility model relates to a kind of multilevel semiconductor thermoelectric cooling assembly, comprises ceramic matrix, flow deflector, N-type semiconductor, P-type semiconductor and flow guide bar; Multilevel semiconductor thermoelectric cooling assembly is formed by stacking to N level semiconductor thermoelectric cooling assembly by the first order, and consolidation ceramic matrix between layers; Ceramic matrix dwindles into pagoda shape gradually by lower floor height upper strata size; Ceramic substrate between every one-level adopts the method for designing of two-sided metallization; The consolidation of ceramic matrix rational and orderly flow deflector; N-type semiconductor and P-type semiconductor are cemented on flow deflector respectively, and the N-type semiconductor simultaneously in every one deck and P-type semiconductor are serially connected by flow deflector successively; Semiconductor is between layers connected by flow guide bar; N-type semiconductor in whole assembly and P-type semiconductor always spaced series are connected; The upper level galvanic couple logarithm of multilevel semiconductor thermoelectric cooling assembly is no more than 60% of one-level below.Such scheme can provide the larger temperature difference.
Description
Technical field
The present invention relates to a kind of semiconductor refrigerating assembly, particularly a kind of multilevel semiconductor thermoelectric cooling assembly.
Background technology
Semiconductor chilling plate, is also thermoelectric module, is a kind of heat pump.Its advantage does not have slide unit, and be applied in some spaces and be restricted, reliability requirement is high, without the occasion that cold-producing medium pollutes.Utilize the Peltier effect of semi-conducting material, when the galvanic couple that direct current is connected into by two kinds of different semi-conducting materials, heat can be absorbed at the two ends of galvanic couple respectively and release heat, the object of freezing can be realized.It is a kind of Refrigeration Technique producing negative thermal resistance, is characterized in movement-less part, and reliability is also higher.Utilize the mode of semiconductor refrigerating to solve refrigeration, heat dissipation problem, there is very high practical value.
Existing semiconductor refrigerating is a level assembly, that is one deck is only had, semiconductor refrigerating assembly by one group of NP galvanic couple to, up and down each a slice ceramic substrate and wire form, be mainly used in the industries such as car refrigerator, water dispenser, constant-temperature wine cabinet, cold and hot surface maximum temperature difference 70 degree.And for needing the occasion of the larger temperature difference just can not meet the demands.
Summary of the invention
The technical issues that need to address of the present invention are to provide a kind of a kind of multilevel semiconductor thermoelectric cooling assembly that can provide the larger temperature difference.
Technical problem to be solved by this invention realizes by the following technical solutions.
A kind of multilevel semiconductor thermoelectric cooling assembly, comprise ceramic matrix, flow deflector, N-type semiconductor and P-type semiconductor, described multilevel semiconductor thermoelectric cooling assembly also comprises flow guide bar; Described multilevel semiconductor thermoelectric cooling assembly is formed by stacking to N level semiconductor thermoelectric cooling assembly by the first order, and consolidation ceramic matrix between layers; Described ceramic matrix dwindles into pagoda shape gradually by lower floor height upper strata size; Ceramic substrate between described every one-level adopts the method for designing of two-sided metallization; The consolidation of described ceramic matrix rational and orderly flow deflector; Described N-type semiconductor and P-type semiconductor are cemented on flow deflector respectively, and the N-type semiconductor simultaneously in every one deck and P-type semiconductor are serially connected by flow deflector successively; Described semiconductor is between layers connected by flow guide bar; N-type semiconductor in described whole assembly and P-type semiconductor always spaced series are connected; ; The galvanic couple logarithm that the upper level of described multilevel semiconductor thermoelectric cooling assembly is made up of N-type semiconductor and P-type semiconductor is no more than 60% of one-level below.
Further, the progression of described multilevel semiconductor thermoelectric cooling assembly is 2,3,4,5 or 6 grades.
Further, described ceramic matrix and the consolidation style between flow deflector are for welding or sintering.
Further, the consolidation style between described flow deflector with semiconductor N P element is for welding.
Further, when described multilevel semiconductor thermoelectric cooling assembly is six grades, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31,17,7 and 2 right; When described multilevel semiconductor thermoelectric cooling assembly is Pyatyi, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31,17 and 7 right; When described multilevel semiconductor thermoelectric cooling assembly is level Four, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31 and 17 right; When described multilevel semiconductor thermoelectric cooling assembly is three grades, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71 and 31 right; When described multilevel semiconductor thermoelectric cooling assembly is two-stage, by bottom, to upper strata, inner NP galvanic couple is 127 and 71 right to number of the arrangement.
After adopting such structure, owing to being made up of multistage, according to semiconductor refrigerating component operation principle, after energising, NP galvanic couple, to by heat absorption and radiation processes, produces altitude temperature difference effect.Single-stage refrigeration sheet maximum temperature difference 70 DEG C.The upper level galvanic couple logarithm of multi-stage refrigerating sheet is no more than 60% of one-level below, so the heat that upper level produces can be taken away by next stage completely, often increase one-level, the temperature difference can increase about 10 degree, thus produces the higher temperature difference.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
The general structure schematic diagram that Fig. 1 is the present invention's narrow a kind of multilevel semiconductor thermoelectric cooling assembly when being six grades;
The general structure schematic diagram that Fig. 2 is the present invention's narrow a kind of multilevel semiconductor thermoelectric cooling assembly when being Pyatyi;
The general structure schematic diagram that Fig. 3 is the present invention's narrow a kind of multilevel semiconductor thermoelectric cooling assembly when being level Four;
The general structure schematic diagram that Fig. 4 is the present invention's narrow a kind of multilevel semiconductor thermoelectric cooling assembly when being three grades;
The general structure schematic diagram that Fig. 5 is the present invention's narrow a kind of multilevel semiconductor thermoelectric cooling assembly when being secondary;
Fig. 6 is the general structure schematic diagram of ordinary single-stage semiconductor temperature difference electric cooling assembly;
Fig. 7 be the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention bottom ceramic matrix above view;
Fig. 8 is the second layer ceramic matrix top and bottom view of the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention;
Fig. 9 is the third layer ceramic matrix top and bottom view of the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention;
Figure 10 is the 4th layer of ceramic matrix top and bottom view of the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention;
Figure 11 is the layer 5 ceramic matrix top and bottom view of the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention;
Figure 12 is the layer 6 ceramic matrix top and bottom view of the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention;
Figure 13 is the superiors' ceramic matrix lower view of the narrow a kind of multilevel semiconductor thermoelectric cooling assembly of the present invention;
In figure: 1. ceramic matrix; 101. ground floor ceramic matrixs; 102. second layer ceramic matrixs; 103. third layer ceramic matrixs; 104. the 4th layers of ceramic matrix; 105. layer 5 ceramic matrixs; 106. layer 6 ceramic matrixs; 107. layer 7 ceramic matrixs; 2.P type semiconductor; 3.N type semiconductor; 4. flow deflector; 5. flow guide bar.
Detailed description of the invention
The technological means realized to make the present invention, creation characteristic, reaching object and effect is easy to understand, below in conjunction with specific embodiment and diagram, setting forth the present invention further.
A kind of multilevel semiconductor thermoelectric cooling assembly, comprise ceramic matrix 1, flow deflector 4, N-type semiconductor 3 and P-type semiconductor 2, described multilevel semiconductor thermoelectric cooling assembly also comprises flow guide bar 5; Described multilevel semiconductor thermoelectric cooling assembly is formed by stacking to N level semiconductor thermoelectric cooling assembly by the first order, and consolidation ceramic matrix 1 between layers; Described ceramic matrix 1 dwindles into pagoda shape gradually by lower floor height upper strata size; Ceramic matrix 1 between described every one-level adopts the method for designing of two-sided metallization; The consolidation of described ceramic matrix 1 rational and orderly flow deflector 4; Described N-type semiconductor 3 and P-type semiconductor 2 are cemented on flow deflector 4 respectively, and the N-type semiconductor 3 simultaneously in every one deck and P-type semiconductor 2 are serially connected by flow deflector 4 successively; Described semiconductor is between layers connected by flow guide bar 5; N-type semiconductor 3 in described whole assembly and P-type semiconductor 2 always spaced series are connected; The galvanic couple logarithm that the upper level of described multilevel semiconductor thermoelectric cooling assembly is made up of N-type semiconductor 3 and P-type semiconductor 4 is no more than 60% of one-level below.
The progression of described multilevel semiconductor thermoelectric cooling assembly is 2,3,4,5 or 6 grades.
Described ceramic matrix 1 and the consolidation style between flow deflector 4 are for welding or sintering.
Described flow deflector 4 and the consolidation style between semiconductor are for welding.
When described multilevel semiconductor thermoelectric cooling assembly is six grades, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31,17,7 and 2 right; When described multilevel semiconductor thermoelectric cooling assembly is Pyatyi, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31,17 and 7 right; When described multilevel semiconductor thermoelectric cooling assembly is level Four, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31 and 17 right; When described multilevel semiconductor thermoelectric cooling assembly is three grades, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31 right; When described multilevel semiconductor thermoelectric cooling assembly is two-stage, by bottom, to upper strata, inner NP galvanic couple is 127 and 71 right to number of the arrangement.
More than show and describe general principle of the present invention, principal character and advantage.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; what describe in above-described embodiment and description just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the scope of protection of present invention.Application claims protection domain is defined by appending claims and equivalent thereof.
Claims (5)
1. a multilevel semiconductor thermoelectric cooling assembly, comprises ceramic matrix, flow deflector, N-type semiconductor and P-type semiconductor, it is characterized in that: described multilevel semiconductor thermoelectric cooling assembly also comprises flow guide bar; Described multilevel semiconductor thermoelectric cooling assembly is formed by stacking to N level semiconductor thermoelectric cooling assembly by the first order, and consolidation ceramic matrix between layers; Described ceramic matrix dwindles into pagoda shape gradually by lower floor height upper strata size; Ceramic substrate between described every one-level adopts the method for designing of two-sided metallization; The consolidation of described ceramic matrix rational and orderly flow deflector; Described N-type semiconductor and P-type semiconductor are cemented on flow deflector respectively, and the N-type semiconductor simultaneously in every one deck and P-type semiconductor are serially connected by flow deflector successively; Described semiconductor is between layers connected by flow guide bar; N-type semiconductor in described whole assembly and P-type semiconductor always spaced series are connected; The galvanic couple logarithm that the upper level of described multilevel semiconductor thermoelectric cooling assembly is made up of N-type semiconductor and P-type semiconductor is no more than 60% of one-level below.
2. multilevel semiconductor thermoelectric cooling assembly according to claim 1, is characterized in that: the progression of described multilevel semiconductor thermoelectric cooling assembly is 2,3,4,5 or 6 grades.
3. multilevel semiconductor thermoelectric cooling assembly according to claim 1, is characterized in that: described ceramic matrix and the consolidation style between flow deflector are for welding or sintering.
4. multilevel semiconductor thermoelectric cooling assembly according to claim 1, is characterized in that: the consolidation style between described flow deflector with semiconductor element NP is for welding.
5. multilevel semiconductor thermoelectric cooling assembly according to claim 1 and 2, is characterized in that: when described multilevel semiconductor thermoelectric cooling assembly is six grades, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31,17,7 and 2 right; When described multilevel semiconductor thermoelectric cooling assembly is Pyatyi, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31,17 and 7 right; When described multilevel semiconductor thermoelectric cooling assembly is level Four, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71,31 and 17 right; When described multilevel semiconductor thermoelectric cooling assembly is three grades, by bottom to upper strata inner NP galvanic couple to number of the arrangement be 127,71 and 31 right; When described multilevel semiconductor thermoelectric cooling assembly is two-stage, by bottom, to upper strata, inner NP galvanic couple is 127 and 71 right to number of the arrangement.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420508779.3U CN204043235U (en) | 2014-08-29 | 2014-08-29 | A kind of multilevel semiconductor thermoelectric cooling assembly |
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| CN201420508779.3U CN204043235U (en) | 2014-08-29 | 2014-08-29 | A kind of multilevel semiconductor thermoelectric cooling assembly |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105371522A (en) * | 2014-08-29 | 2016-03-02 | 陈树山 | Multistage semiconductor thermoelectric cooling assembly |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105371522A (en) * | 2014-08-29 | 2016-03-02 | 陈树山 | Multistage semiconductor thermoelectric cooling assembly |
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Effective date of registration: 20151210 Address after: 065400, Hebei County, Langfang City, Xianghe Province Yang Zhen Jin Village South Patentee after: XIANGHE DONGFANG ELECTRONIC Co.,Ltd. Address before: Lutai Qingfeng town 301500 Tianjin city Ninghe County Guangming District 7 Building 4 unit 302 Patentee before: Chen Shushan |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141224 |
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| CF01 | Termination of patent right due to non-payment of annual fee |