CN204029807U - A kind of low-temperature polysilicon film transistor array base palte, display unit - Google Patents
A kind of low-temperature polysilicon film transistor array base palte, display unit Download PDFInfo
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- CN204029807U CN204029807U CN201420357600.9U CN201420357600U CN204029807U CN 204029807 U CN204029807 U CN 204029807U CN 201420357600 U CN201420357600 U CN 201420357600U CN 204029807 U CN204029807 U CN 204029807U
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- array base
- base palte
- insulating barrier
- electrode
- grid
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 35
- 239000000203 mixture Substances 0.000 description 26
- 238000002360 preparation method Methods 0.000 description 11
- 229920002120 photoresistant polymer Polymers 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052750 molybdenum Inorganic materials 0.000 description 5
- 239000011733 molybdenum Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000002207 thermal evaporation Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 238000004062 sedimentation Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910001257 Nb alloy Inorganic materials 0.000 description 3
- 229910000583 Nd alloy Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- VVTQWTOTJWCYQT-UHFFFAOYSA-N alumane;neodymium Chemical compound [AlH3].[Nd] VVTQWTOTJWCYQT-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910000449 hafnium oxide Inorganic materials 0.000 description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 3
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000000839 emulsion Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- YZZNJYQZJKSEER-UHFFFAOYSA-N gallium tin Chemical compound [Ga].[Sn] YZZNJYQZJKSEER-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The utility model relates to a kind of low-temperature polysilicon film transistor array base palte and display unit.This array base palte, comprising: substrate; Be arranged on the polysilicon active layer on described substrate; Be arranged on the first insulating barrier on described active layer; Be arranged on a plurality of grids and grid line on described the first insulating barrier; Be arranged on the second insulating barrier on described grid; Be arranged on source electrode, drain electrode and data wire on described the second insulating barrier; And the pixel electrode being electrically connected to described drain electrode; Described source electrode covers described a plurality of grids.Grid multi-gate structure is integrated under source electrode line, has not only reduced leakage current, also improved the aperture opening ratio of panel.
Description
Technical field
The utility model relates to Display Technique field, particularly a kind of array base palte and display unit.
Background technology
In Display Technique field, (Low Temperature Poly-silicon is called for short: LTPS) technology application is comparatively extensive for amorphous silicon (α-Si) technology and low temperature polycrystalline silicon.Wherein, along with the development of Display Technique, LTPS technology relies on its high-effect and feature high definition, has obtained application more and more widely.
For LTPS structure, the size of leakage current is an important indicator.The excessive driving voltage that causes of leakage current cannot keep, and there will be the bad of demonstration aspect.At present, the method that reduces LTPS leakage current is to adopt double grid or multi-gate structure, example double-gate structure as shown in Figure 1.Although by adopting a plurality of grids, can effectively reduce the Electric Field Distribution in raceway groove, reduce hot carrier's effect and suppress leakage current.But grid generally adopts the good metal material of electric conductivity, such as molybdenum or molybdenum aluminium alloy etc., these materials itself are light tight.So adopt double grid or multi-gate structure to be unfavorable for the raising of aperture opening ratio.
Utility model content
The utility model provides a kind of low-temperature polysilicon film transistor array base palte and display unit, has not only reduced the generation of leakage current, has also improved the aperture opening ratio of panel.
For achieving the above object, the utility model provides a kind of low-temperature polysilicon film transistor array base palte, comprising: substrate; Be arranged on the polysilicon active layer on described substrate; Be arranged on the first insulating barrier on described active layer; Be arranged on a plurality of grids and grid line on described the first insulating barrier; Be arranged on the second insulating barrier on described grid; Be arranged on source electrode, drain electrode and data wire on described the second insulating barrier; And the pixel electrode being electrically connected to described drain electrode; Described source electrode covers described a plurality of grids.
Preferably, the active layer of described array base palte below is also provided with resilient coating.
Preferably, a plurality of grids of described array base palte are 2 to 5.
Preferably, described array base palte also comprises the public electrode arranging with layer with described pixel electrode.
Preferably, described array base palte also comprises the 3rd insulating barrier that is arranged on described pixel electrode top, and is arranged on the slit-shaped public electrode on described the 3rd insulating barrier.
Preferably, the second insulating barrier of described array base palte is resin material.
Preferably, the thickness of described the second insulating barrier is 1.5-2.0 μ m.
The utility model provides a kind of display unit, comprises above-mentioned low-temperature polysilicon film transistor array base palte.
The utlity model has following beneficial effect: grid multi-gate structure is integrated under source electrode line, has not only improved the aperture opening ratio of panel, also reduced leakage current.Between grid and source-drain electrode, increase the resin bed that dielectric constant is little, avoided the coupling capacitance because of grid and the generation of source signal line overlap, thereby reduced the generation of leakage current.
Accompanying drawing explanation
Fig. 1 is the plane graph of double-gate structure array base palte in prior art;
Fig. 2 A is the plane graph of the utility model array base palte the first embodiment;
Fig. 2 B be in Fig. 2 A A-B to profile;
Fig. 3 A is the utility model array base palte the first embodiment plane graph of composition technique for the first time;
Fig. 3 B be in Fig. 2 A A-B to profile;
Fig. 4 A is the utility model array base palte the first embodiment plane graph of composition technique for the second time;
Fig. 4 B be in Fig. 3 A A-B to profile;
Fig. 5 A is the utility model array base palte the first embodiment plane graph of composition technique for the third time;
Fig. 5 B be in Fig. 4 A A-B to profile;
Fig. 6 A is the plane graph of the 4th composition technique of the utility model array base palte the first embodiment;
Fig. 6 B be in Fig. 4 A A-B to profile;
Fig. 7 A is the plane graph of the 5th composition technique of the utility model array base palte the first embodiment;
Fig. 7 B be in Fig. 6 A A-B to profile;
Fig. 8 A is the plane graph of the 6th composition technique of the utility model array base palte the first embodiment;
Fig. 8 B be in Fig. 7 A A-B to profile;
Fig. 9 A is the plane graph of the 7th composition technique of the utility model array base palte the first embodiment;
Fig. 9 B be in Fig. 8 A A-B to profile.
Accompanying drawing identifier declaration:
1. substrate; 2. active layer; 3. the first insulating barrier; 4. the second insulating barrier; 5. source electrode; 6. drain electrode; 7. grid; 8. pixel electrode; 9. the 3rd insulating barrier; 10. public electrode
Embodiment
For making those skilled in the art understand better the technical solution of the utility model, the array base palte and the display unit that the utility model are provided below in conjunction with accompanying drawing are described in detail.
Embodiment mono-:
Embodiment mono-provides a kind of low-temperature polysilicon film transistor array base palte.As shown in Figure 2 A and 2B, wherein Fig. 2 A is the vertical view of embodiment array basal plate, and Fig. 2 B is that Fig. 2 A is along the profile of A-B direction.The array base palte of embodiment mono-comprises: substrate 1; Be arranged on the polysilicon active layer 2 on substrate 1; Be arranged on the first insulating barrier 3 on active layer 2; Be arranged on a plurality of grids 7 and grid line on the first insulating barrier 3; Be arranged on the second insulating barrier 4 on grid 7; Be arranged on source electrode 5, drain electrode 6 and the data wire on the second insulating barrier 4 and the pixel electrode 8 being electrically connected to described drain electrode 6; Described source electrode 5 covers described a plurality of grids 7.
As shown in Figure 2 B, described a plurality of grid is 3.Grid multi-gate structure is integrated under source electrode line, has improved the aperture opening ratio of panel.
At the array base palte of the present embodiment, also comprise the 3rd insulating barrier 9 being arranged on above described pixel electrode 8, and be arranged on the slit-shaped public electrode 10 on described the 3rd insulating barrier 9.
Wherein, described pixel electrode 8 and public electrode 10 all adopt at least one formation in indium oxide gallium zinc, indium zinc oxide (Indium Zinc Oxide is called for short IZO), tin indium oxide (Indium Tin Oxide is called for short ITO), indium oxide gallium tin.
Wherein, described the first insulating barrier 3, the second insulating barrier 4, the 3rd insulating barrier 9 can adopt at least one formation in Si oxide, silicon nitride, hafnium oxide or aluminum oxide; Described grid 7, source electrode 5 and drain electrode 6 at least one formation that can all adopt in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper; Described active layer 2 adopts low temperature polycrystalline silicon material to form.
As shown in Fig. 3-9, above-mentioned array base palte adopts following preparation method's preparation:
Step S1: deposition of amorphous silicon films on substrate, amorphous silicon is transformed into low temperature polycrystalline silicon, by composition technique, form the figure that comprises active layer 2.
In this step, as shown in Fig. 3 A and 3B, on described substrate 1, use chemical vapour deposition (CVD) (CVD) method deposited amorphous silicon layer.Preferably, adopting quasi-molecule laser annealing (ELA) method is low temperature polycrystalline silicon by amorphous silicon crystallization; Then carry out photoetching and etch step and form needed described graphical low-temperature polycrystalline silicon layer.
Step S2: the figure that forms the first insulating barrier 3 on the substrate of completing steps S1.
In this step, as shown in Fig. 4 A and 4B, the thickness range that adopts chemical vapour deposition (CVD) (Chemical Vapor Deposition is called for short CVD) method to form the first insulating barrier 3, the first insulating barriers 3 on the substrate 1 of completing steps S1 is
the general transparent material (Si oxide, silicon nitride, hafnium oxide or aluminum oxide) that adopts of the first insulating barrier 3 forms.
Step S3: deposit grid metallic film on the substrate of completing steps S2, form the figure that comprises grid 7 and grid line by composition technique.
In this step, as shown in Fig. 4 A and 4B, on the substrate 1 of completing steps S2, form gate metal film, metallic film can adopt at least one in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper, by composition technique, form the figure that comprises grid 7 and grid line, described grid 7 is connected with described grid line.Take grid 7 as mask plate, active layer is adulterated.Described grid is three grids or many gate patterns, is pectination and distributes, and multi-gate structure is integrated under source electrode line.
Wherein, form metallic film and adopt sedimentation, sputtering method or thermal evaporation, the thickness range of metallic film is
in described composition technique, first on metallic film, apply one deck photoresist, adopt mask plate that described photoresist is exposed, development, etching, peeled off, to form the figure that comprises grid 7 and grid line.
Multi-gate structure is integrated under source signal line, has not only reduced the generation of leakage current, also improved the aperture opening ratio of panel.
Step S4: the general 3 μ m resin beds of rotary coating one deck on the substrate of completing steps S3, form the second insulating barrier 4.By composition technique, on the first insulating barrier 3 and the second insulating barrier 4, form via hole.
In this step, as shown in Figure 5 A and 5B, at the substrate 1 of completing steps S3, adopt method coating one deck resin bed of rotary coating, form the second insulating barrier 4.By composition technique, on the first insulating barrier 3 and the second insulating barrier 4, form via hole.
Between grid 7 and source-drain electrode, increase the resin bed that dielectric constant is little, avoided the coupling capacitance because of grid and the generation of source signal line overlap.
Step S5: sedimentary origin leaks metallic film on the substrate of completing steps S4, forms the figure that comprises source electrode 5 and drain electrode 6 by composition technique.
In this step, as shown in Figure 6 A and 6B, on the substrate 1 of completing steps S4, form metallic film, by composition technique, form the figure that comprises source electrode 5, drain electrode 6 and data wire, described source electrode 5 and drain electrode 6 are positioned at the both sides, top of the second insulating barrier 4, and the via hole by the second insulating barrier 4 and the first insulating barrier 3 is connected with active layer 2 doped regions.
Wherein, form metallic film and adopt sedimentation, sputtering method or thermal evaporation.In described composition technique, first on metallic film, apply one deck photoresist, adopt mask plate that described photoresist is exposed, development, etching, peeled off, to form the figure that comprises source electrode 5, drain electrode 6 and data wire.Metallic film can adopt at least one in molybdenum, molybdenum niobium alloy, aluminium, aluminium neodymium alloy, titanium or copper.
Step S6: deposit transparent conductive film on the substrate of completing steps S5, by composition technique, form the figure that comprises pixel electrode 8, described pixel electrode 8 is electrically connected to described drain electrode 6.
In this step, as shown in Fig. 7 A and 7B, on the substrate of completing steps S5, form pixel electrode film, by composition technique, form the figure that comprises pixel electrode 8.Described pixel electrode 8 is positioned at the top of drain electrode the 6 and second insulating barrier 4, and described pixel electrode 8 is electrically connected to described drain electrode 6.
Wherein, form pixel electrode film and adopt chemical vapour deposition technique, sputtering method or thermal evaporation, the thickness range of pixel electrode film is
in described composition technique, first on pixel electrode film, apply one deck photoresist, adopt mask plate that described photoresist is exposed, development, etching, peeled off, to form the figure of pixel electrode 8.
Step S7: deposit the 3rd insulating barrier 9 on the substrate of completing steps S6, form via hole by composition technique.
In this step, as shown in Fig. 8 A and 8B, on the substrate 1 of completing steps S6, form passivation layer film, by composition technique, form the 3rd insulating barrier 9 (PVX) figure, described the 3rd insulating barrier 9 figures cover described source electrode 5, drain electrode 6 and pixel electrode 8.
Wherein, form the 3rd insulating barrier 9 films and adopt sedimentation, sputtering method or thermal evaporation, the thickness range of passivation layer film is
in described composition technique, first on the 3rd insulating barrier 9 films, apply one deck photoresist, adopt mask plate that described photoresist is exposed, development, etching, peeled off, to form the figure that comprises the 3rd insulating barrier 9 and via hole.Similar with the first insulating barrier 3, the general transparent material (Si oxide, silicon nitride, hafnium oxide or aluminum oxide) that adopts of the 3rd insulating barrier 9 forms.
Now, the 3rd insulating barrier 9 is formed on the top of data wire, source electrode 5 and drain electrode 6 and extends to the peripheral leads region of array base palte, peripheral leads region division at array base palte has data wire to drive signal leading electrode, the 3rd insulating barrier 9 drives the position of signal leading electrode to offer via hole in respective data lines, and described data wire and data wire drive signal leading electrode to bind together by via hole.
Step S8: deposit transparent conductive film on the substrate of completing steps S7, forms the figure that comprises public electrode 10 by composition technique.
In this step, as shown in Fig. 9 A and 9B, on the substrate 1 of completing steps S7, form public electrode film, by composition technique, above the 3rd insulating barrier 9, form the figure that comprises public electrode 10.Wherein, form public electrode film and adopt sedimentation, sputtering method or thermal evaporation.In described composition technique, first on public electrode film, apply one deck photoresist, adopt mask plate that described photoresist is exposed, development, etching, peeled off, to form the figure that comprises public electrode 10.The gap electrode that public electrode 10 distributes for being pectination.
In the preparation method of above-mentioned array base palte, when forming each layer of structure, can also be by reduce the number of times of composition technique by modes such as halftoning or gray tone mask plates, this is no longer going to repeat them, finally forms array base palte, as shown in Figure 2.
Embodiment bis-
Low-temperature polysilicon film transistor array base palte and embodiment mono-that the present embodiment provides are similar, and its difference part is: a plurality of grids 7 that the array base palte of the present embodiment comprises are 2.Certainly, those skilled in the art also can select to adopt 4 grids or 5 grids as required.
The preparation method of the array base palte in the preparation method of the array base palte of the present embodiment and embodiment mono-is similar, and this is no longer going to repeat them.
Embodiment tri-
Low-temperature polysilicon film transistor array base palte and embodiment mono-that the present embodiment provides are similar, and its difference part is: described active layer 2 belows are also provided with resilient coating.
The preparation method of the array base palte in the preparation method of the array base palte of the present embodiment and embodiment mono-is similar, and this is no longer going to repeat them.
Embodiment tetra-
Low-temperature polysilicon film transistor array base palte and embodiment mono-that the present embodiment provides are similar, and its difference part is: public electrode and the pixel electrode of the array base palte of the present embodiment are arranged on same layer, form the structure of IPS.
The preparation method of the array base palte in the preparation method of the array base palte of the present embodiment and embodiment mono-is similar, and this is no longer going to repeat them.
Embodiment five
Low-temperature polysilicon film transistor array base palte and embodiment mono-that the present embodiment provides are similar, and its difference part is: the second insulating barrier 4 that the array base palte described in the present embodiment comprises is resin material.Resin material comprises polymethyl methacrylate and emulsion.The thickness of the second insulating barrier 4 is 1.5-2.0 μ m.
The preparation method of the array base palte in the preparation method of the array base palte of the present embodiment and embodiment mono-is similar, and this is no longer going to repeat them.
The utility model embodiment also provides a kind of display unit, and it comprises above-mentioned any one array base palte.Described display unit can be: any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
Be understandable that, above execution mode is only used to principle of the present utility model is described and the illustrative embodiments that adopts, yet the utility model is not limited to this.For those skilled in the art, in the situation that not departing from spirit of the present utility model and essence, can make various modification and improvement, these modification and improvement are also considered as protection range of the present utility model.
Claims (9)
1. a low-temperature polysilicon film transistor array base palte, comprising: substrate; Be arranged on the polysilicon active layer on described substrate; Be arranged on the first insulating barrier on described active layer; Be arranged on a plurality of grids and grid line on described the first insulating barrier; Be arranged on the second insulating barrier on described grid; The pixel electrode that is arranged on source electrode, drain electrode and the data wire on described the second insulating barrier and is electrically connected to described drain electrode; It is characterized in that: described source electrode covers described a plurality of grids.
2. array base palte according to claim 1, is characterized in that: described active layer below is also provided with resilient coating.
3. array base palte according to claim 1 and 2, is characterized in that: described a plurality of grids are 2 to 5.
4. array base palte according to claim 3, is characterized in that: also comprise the public electrode arranging with layer with described pixel electrode.
5. array base palte according to claim 3, is characterized in that: also comprise the 3rd insulating barrier that is arranged on described pixel electrode top, and be arranged on the slit-shaped public electrode on described the 3rd insulating barrier.
6. array base palte according to claim 3, is characterized in that: also comprise the public electrode arranging with layer with described grid.
7. array base palte according to claim 3, is characterized in that: described the second insulating barrier is resin material.
8. array base palte according to claim 7, is characterized in that: the thickness of described the second insulating barrier is 1.5-2.0 μ m.
9. a display unit, is characterized in that, comprises the array base palte described in claim 1 to 8 any one.
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| CN201420357600.9U CN204029807U (en) | 2014-06-30 | 2014-06-30 | A kind of low-temperature polysilicon film transistor array base palte, display unit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420357600.9U CN204029807U (en) | 2014-06-30 | 2014-06-30 | A kind of low-temperature polysilicon film transistor array base palte, display unit |
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| CN204029807U true CN204029807U (en) | 2014-12-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103646A (en) * | 2014-06-30 | 2014-10-15 | 京东方科技集团股份有限公司 | Low temperature poly-silicon thin film transistor array substrate and fabrication method thereof and display device |
-
2014
- 2014-06-30 CN CN201420357600.9U patent/CN204029807U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104103646A (en) * | 2014-06-30 | 2014-10-15 | 京东方科技集团股份有限公司 | Low temperature poly-silicon thin film transistor array substrate and fabrication method thereof and display device |
| WO2016000363A1 (en) * | 2014-06-30 | 2016-01-07 | 京东方科技集团股份有限公司 | Low temperature poly-silicon thin film transistor array substrate and manufacturing method therefor and display device |
| US10002889B2 (en) | 2014-06-30 | 2018-06-19 | Boe Technology Group Co., Ltd. | Low-temperature polysilicon thin film transistor array substrate and method of fabricating the same, and display device |
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