CN203984392U - The line drive that a kind of transmission time is controlled - Google Patents
The line drive that a kind of transmission time is controlled Download PDFInfo
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- CN203984392U CN203984392U CN201320760729.XU CN201320760729U CN203984392U CN 203984392 U CN203984392 U CN 203984392U CN 201320760729 U CN201320760729 U CN 201320760729U CN 203984392 U CN203984392 U CN 203984392U
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Abstract
The line drive that transmission time is controlled, is used for exporting the offset current that is referred to the electric current on ground and is referred to ground, comprises the MOS output transistor being coupling between a constant current source and an electric current output node; Be coupling in a MOS output complementary transistor between described constant-current source and a complementary current output node; Control circuit provides output transistor and is proportional to the output current that is applied to the input voltage signal of inputting node, the simultaneously intrinsic asymmetry of on/off switch in compensating MOS transistor.
Description
Technical field:
The present invention relates to drive circuit, particularly the control of the reflection loss of the harmonic component of drive circuit, common-mode noise, output.Particularly, the present invention relates to the instantaneous distortion of data pulse and the control of reflection of current switch/driver to data line transmission.More specifically, the present invention relates to, make the minimized part of transient state aberration and signal reflex, and the minimized part of electromagnetic interference (EMI) that carry high frequency in unscreened conductor (being greater than 50 megahertzes) data are produced.
Background technology:
High-frequency data transmission line tool has great advantage, the maskless twisted-pair feeder particularly using in local area computer network.But high-frequency data pulse meeting causes unacceptable EMI, is also subject to the impact of impedance mismatching loss---this problem is aggravated the increase due to transmission frequency.The main source of electromagnetic interference is:
(a) common-mode noise on transmission line, from the coupling capacitance that outputs to input and intermediate node of (i) transmitter; (ii) as the noise signal of the power supply of output reference voltage;
(b) the ring distortion of pulse and over swing distortion (being referred to as " transient distortion ");
(c) asymmetry between rising edge of a pulse and trailing edge.
In general, transmission line does not produce any ac magnetic field containing the conditional request of electromagnetic interference in certain distance.Because transmission line carries signal and complement code thereof simultaneously, should not have problems in theory.The equal and opposite in direction at certain distance, single spin-echo that the field at certain distance that input signal produces and signal complement code produce, therefore, it is invalid that the stack of these two fields will cause exchanging.In other words, the wire of a pair of twisted-pair feeder carries signal and complement code thereof, and due to the AC signal of equal amplitude/opposite phase, the ac magnetic field producing on certain distance is zero.Now, the factor of any skew-symmetry of breaking signal/signal complement code will cause a non-vanishing ac magnetic field, thereby produces the EMI mating with signal frequency.This situation may occur, and for example, two signals that are referred to a power supply are time dependent.Following situation also can occur, by capacitive coupling or other method, on right one or two wire of transmission line that time dependent signal is fed to.If contain ring distortion or over swing distortion at porch, this will be particularly unfavorable.(these transient distortions can not be eliminated, and a high amplitude and high-frequency net signal will be provided.) if trailing edge and the rising edge of pulse be asymmetric, can produce so the alternating-current field of non-zero.For example, if rising edge is more more precipitous than trailing edge, so the rising pulse of holding wire by the falling pulse of adding corresponding complementary holding wire to produce a time dependent non-zero signal.In the prior art, these different signals can increase the generation of EMI, and this problem is intrinsic.For reducing to disturb, on the transmission line that is coupled with reflector and receiver, introduce LRC filter.(in addition, choking-winding and isolating transformer are often used in the two ends of transmission line.)
But prior art is introduced LRC filter, to solve EMI and the impedance mismatch problem of high-frequency transmission.These problems include but not limited to dispersion phenomenon and the ringing of signal.Because the LRC filter that prior art adopts has limit bandwidth, this cannot fully reduce EMI and the reflection loss of whole bandwidth, no matter tuning do good again of carrier frequency.The frequency level of development is at 62.5MHz at present; The rising and falling time of data pulse is about 600 psecs.This rise/fall time is very fast, can cause the generation of EMI to contain transient distortion.LRC filter is invalid solving high-frequency transient distortion problem, can and in fact aggravate this problem.Finally will consider, the burst transmissions circuit with very fast rising and falling time is very serious---in this sense, be applicable to low-frequency node and can be used as the entrance of very short high-frequency circuit of rise/fall time.If circuit will carry such signal, need an adjunct circuit highly insuring to pay close attention to inside circuit and connect.If the rise/fall time can lengthen, the requirement of this respect can be relaxed (transmission frequency is in 62.5MHz or higher limited field).
Fig. 1 has shown a typical prior art systems, and it comprises an ECL switch/driver as reflector---comprise output V
owith complementary output V
ob.(Fig. 1 a has specifically shown ECL switch/driver.) LRC filter (F1 and F2) is placed on transmission line, to reduce EMI and impedance matching be provided.In addition, choking-winding T2 and T4 follow isolating transformer T1 and T3 in the drawings.Choking-winding is used for reducing common-mode noise.As seen from the figure, with the switch/driver of ECL circuit structure, through high potential power V
cCon any noise of drawing all can be transmitted line V
oand V
ob absorbs.In general, high frequency noise can cause EMI problem.This will be more reliable, make output and complementary output jointly be referred to low potential power source GND, instead of be referred to V
cC.External reference is coupled to CND and is compared V
cCcan less impact of being drawn.But output signal is referred to V in general ECL driver
cC.
By being offset a switch/driver based on metal-oxide-semiconductor, the current impulse that generation is referred to low potential power source GND is desirable.Fig. 2 a shows the MOS type switch/driver of the ECL circuit that is similar to Fig. 1 in prior art.The electric current I of switching between two branch roads
mrevised by known technology, use current regulator/generator here, it is operated in high potential power V
cCand between the common source node of PMOS output transistor QA and QB.Output transistor QA and QB are by being coupling in V
cCwith CMOS inverter between GND switches, and controlled by input signal E and complementary input signal EB respectively.Above-mentioned is the CMOS inverter of standard, and the deflection by default PMOS and nmos device is to provide respectively the symmetrical grid that outputs signal to QA and QB in response to symmetrical input signal E and EB.(above-mentioned deflection makes PMOS channel width be greater than NMOS channel.These conditions depend on specific manufacture process; In a typical prior art, if P channel width is 3 times of N raceway groove, symmetrical CMOS input signal can generate symmetrical CMOS output signal).In view of this structure, the control gate of each driving transistors is pulled to V
cC---driving transistors is turn-offed completely, or GND.Therefore, electric current I
mor by QA to GND, resistance by being coupled to QA drain electrode to GND---make V
o=I
m(R
o/ 2) and V
ob=GND, or by QB to GND---make to obtain opposite signal on signal transmssion line.This circuit has advantage from the viewpoint that reduces common-mode noise, due to V
oand V
ob is coupled to more stable power supply GND.
Except V
cCfluctuation beyond, the input signal that another main common-mode noise source is switch/driver is to the coupling capacitance of other nodes.With reference to Fig. 1, this coupling occurs on the base stage node of transistor QX and QY, thus output V
oand V
ob inputs identical common-mode noise by producing with high frequency.No matter relate to which kind of drive circuit, the coupling capacitance of indelible I/O is minimized to be needed.Once approach this level, the demand that reduces common-mode noise minimizes concern the voltage swing of input signal itself.With reference to the ECL switching circuit of figure 1, the swing of this minimum must enough make the complete conducting of NPN transistor or shutoff.That is to say, export constant current I for a driver with good ON/OFF ratio
fmust pass through QX or QY completely.This requires the minimum input amplitude of oscillation of input signal E and EB to be about 0.3V, but the amplitude of oscillation that used in actual applications more approaches 0.8V.
Aspect minimized to the input amplitude of oscillation, the driver based on metal-oxide-semiconductor does not have ECL unit good.A complete rail-to-rail amplitude of oscillation is generally used for switch mos transistor.This can be regarded as the situation of circuit shown in Fig. 2 a.It can also be seen that from Fig. 2 a, use a complete rail-to-rail voltage swing to make a fuss over a trifling matter for the ON/OFF of QA and QB.QA cuts off needed just its grid voltage and is greater than V
s-V
t, wherein V
sthe common-mode sources voltage of this circuit, and V
tit is the grid voltage (being threshold voltage) that makes MOS transistor QA conducting.The occurrence of common-mode sources pole tension depends on circuit power I
mdefinite character and gain when QA, QB conducting.Under any circumstance, biasing QA grid, for example, arrive common-mode sources pole tension, i.e. the V of QA
gs=0, to guarantee that QA is not conducting.QB follows similar principle.
Fig. 2 b shows the switch/drive circuit figure that selects Fig. 1 a of machine-processed prior art with current source.In this mechanism, a PMOS transistor Q7 is operated in saturation mode, and its grid produces bias voltage V outward by sheet
bIASto set up an image current I who is independent of working temperature and power supply voltage supply
m, be still subject to the impact of chip manufacturing proces.For the consideration to control switch current, can be at CMOS level and V
cCbetween insert PMOS transistor (QC and QD).This method has guaranteed that " shutoff " voltage that is applied to QA and QB control node can make V
gsbe approximately zero, and voltage swing declines in the time of QC (or QD) conducting.The minimizing of input amplitude of oscillation voltage can reduce the coupling capacitance of high-frequency noise on transmission line effectively.(but the problem of vibration and over swing distortion still exists, this is that this circuit at MOS and ECL circuit exist equally because these problems depend on the rise/fall time fast.)
This circuit also has a problem to be overcome, the advantage of the common-mode noise of the switch/driver in order to acquisition based on metal-oxide-semiconductor.The waveform of the signal that this problem relates to, the On current of MOS transistor is applied to the complex way of the voltage influence of its grid node, particularly the response curve on bipolar transistor.That is to say, be different from simple transfer function---Ktanh (V
iN/ V
t)---the bipolar transistor of Fig. 1 is described to as voltage V
iNthe function of the control node switching, the right transfer function of MOS type difference transistor is quite complicated, because it relates to transistorized several mode of operation.For example, " unlatching " device may be in its zone of saturation, and " shutoff " installs in its subthreshold value---weak opposite-type region.This means, do not mate with the curent change of " shutoff " device in amplitude in the variation of the increment current of MOS type " unlatching " device.Consequently, for the symmetrical input pulse on E and EB (due to design reasons, according to Fig. 2 a and Fig. 2 b, QA and QB control the symmetrical input pulse of node), in the circuit of Fig. 2 a and Fig. 2 b, pass through resistance R
ooutput current pulse will can not be symmetrical.Especially, the rising edge of " unlatching " current impulse is different from the trailing edge of " shutoff " current impulse very much.This problem is to solve in the switch/driver based on metal-oxide-semiconductor of any one concern EMI.
As mentioned above, the switch/driver based on metal-oxide-semiconductor does not solve the problem of transient state aberration.This,, in based on ECL or this prior art based on MOS, all requires extremely short switching time, for example 0.6 nanosecond.Fortunately, only need to extend the time in three factors, just can eliminate transient state aberration.(owing to being approximately 62.5 megahertzes in the transmission frequency of this problem, pulse length is 8 nanoseconds, if rise/fall time lengthening to 2 nanoseconds, receiver is enough processed pulse effectively so.) unfortunately, the prolongation of rise/fall time is easy in principle, and does difficulty.For example, placing RC time constant (electric capacity low pass filter) by the output at switch/driver is impossible with the rise/fall time extending, because can make the output impedance of reflector change.This is a serious problem, because the impedance mismatch under these frequencies can cause reflection loss.
Therefore, what the present invention needed is a HF switch/driver with reference to the pulse of low potential power source rail generation current, and one can be according to the switch/driver that rises edge and trailing edge thereon at the synchronous input voltage of E and EB and transmit symmetrical current impulse.The present invention what is also needed is one and has the well switch/driver of the output pulse of " opening " and " pass " ratio in response to the minimum input voltage amplitude of oscillation to produce.What finally, the present invention needed is one produce the output pulse that rising and falling time increases and can not increase the switch/driver of output impedance.
Summary of the invention:
The present invention be one for transmitting circuit and the method for the high-frequency data pulse that is referred to low potential power source rail.A part in circuit is a difference current switching circuit based on metal-oxide-semiconductor, and it comprises an output transistor control circuit for overcoming the asymmetry of the pulse of being introduced by transistor.This symmetrical voltage that can guarantee output response input produces symmetrical current pulse.Output transistor control circuit of the present invention, will make amplitude of oscillation lower voltage, and therefore reduce the coupling capacitance of input signal on output node.Finally, this novel switch/driver of the present invention (current feedback circuit) combines to be coupled to a tapped delay line, to can produce a compound output pulse, the slope rising and falling time long enough of this pulse makes to eliminate the transient state aberration on transmission line.By using this compound method, the present invention has avoided the output impedance of degraded signal generator, there is no significant electromagnetic interference (EMI), and the present invention does not use LRC filter on transmission line at high band simultaneously.
Technical solution of the present invention:
Construct the manufacture method that an extendible driver is standard with the array of current switch, and conventionally recommend for this method of reason of physical layout.The deviation carrying between switch element is a problem that needs consideration at this.In a controlled mode, the present invention has deliberately increased inclination time between each switch element to introduce natural inclination.That is to say, the input capacitance of switch/driver is as the RC delay line in input.The result of doing is like this, do not need extra power supply and only needs minimum layout device, just can obtain symmetrical waveform.
Above-mentioned conclusion is, make the array of novel balanced balanced current switch/driver be coupled to a tapped delay line, can obtain the good transmission time of controlling, low common-mode noise and a minimum reflection, all and can complete simultaneously and need to be on ready-made device external filters.Sort circuit has a wide range of applications on high frequency analog signals generates, and is specially adapted to drive the Double-strand transmission line using in high-speed digital communication system.This compound mode can be used VLSI CMOS technique, and can expand to the different geometries with minimum channel length.
The present invention proposes a kind of line drive of transmission time control, be used for exporting the offset current that is referred to the electric current on ground and is referred to ground, described line drive comprises: (a) MOS output transistor, and it is coupling between a constant current source and an electric current output node; (b) a MOS output complementary transistor, it is coupling between described constant-current source and a complementary current output node; (c) a voltage input node is coupled between described output transistor and described output complementary transistor; (d) a complementary voltage input node is coupled between described output transistor and output complementary transistor; (e) control circuit, it provides described output transistor and is proportional to the output current that is applied to the input voltage signal of inputting node to described output node, wherein, described control circuit is by the intrinsic asymmetry of on/off switch in compensating MOS transistor.
Further, control circuit comprises: (a) high-order output transistor driver is coupled between the power supply of high potential and the control node of described output transistor; (b) the output transistor driver of a low level is coupled between the power supply of electronegative potential and the control node of described output transistor; (c) first inverter and second inverter; Wherein, the input of the first described inverter is directly connected to input node, exports the control node that is directly connected to high-order output transistor driver, and the input of the second described inverter is directly connected to complementary voltage input, exports the control node that is directly connected to low level output complementary transistor driver.
Further, described the first inverter is a CMOS level that contains P raceway groove and N raceway groove, and the second described inverter is a CMOS level that contains P raceway groove and N raceway groove.
Further, the output transistor driver of high-order output transistor driver and low level is nmos pass transistor.
Further, described output transistor and output complementary transistor are PMOS transistors.
Further, the P raceway groove of described the first inverter is less than the N raceway groove of described the first inverter, and the P raceway groove of the second inverter is greater than the N raceway groove of described the second inverter.
Further, the P raceway groove of the first described inverter is about 60% of N channel width, and the N raceway groove of the second described inverter is about 50% of P channel width.
Contrast patent documentation: CN102065030A transmission line driver and driving method 200910224505.5, CN102739182A line drive 201110087390.7
Brief description of the drawings:
Fig. 1 (prior art) uses ECL switch/driver to describe as the schematic diagram of the transmission line of the output stage of reflector.
Fig. 2 a (prior art) is the metal-oxide-semiconductor switch/driver based on prior art.
Fig. 2 b (prior art) is and the similarly metal-oxide-semiconductor switch/driver based on prior art (different is the voltage swing that introducing device reduces output transistor gates) of Fig. 2 a.
Fig. 3 a is the general independent switch/drive circuit based on metal-oxide-semiconductor of the present invention.
Fig. 3 b is the special independent switch/drive circuit based on metal-oxide-semiconductor of the present invention.
Fig. 4 be each node of the switch/drive circuit at Fig. 3 b of the present invention in response to the pulse signal of input by the voltage of output transistor control circuit shaping.
Fig. 5 is coupled to according to the independent switch/driver of of the present invention pair of array the circuit diagram that tapped delay line is exported to produce the recombination current pulse of the rising and falling time of expanding.
Fig. 6 has shown delay list entries and the corresponding compound output pulse of Fig. 5 array.
Fig. 7 is the preferred embodiment according to independent switch/driver of the present invention.
Fig. 8 is the principle schematic according to preferred delay line of the present invention.
Embodiment:
Fig. 7 shows according to the preferred embodiment of metal-oxide-semiconductor balance cock of the present invention and line drive.The switching of electric current is by completing below, and PMOS transistor Q7 is operated in saturation range and produces voltage bias outward by circuit, with the leakage current that provides to be independent of the Q7 of working temperature, supply voltage and chip manufacturing variation.Form inverter I1 and I2 clearly illustrates respectively in the drawings by CMOS level.More generally structure briefly description in Fig. 3 a and 3b of the present invention.
Following independently switch/driver will be described.
Independent switch/driver of the present invention is shown in Fig. 3 a.These independently switch/driver based on metal-oxide-semiconductor, and switch constant current (I) to the I of branch
oor I
ob one of them.The variation of above-mentioned electric current and temperature, supply voltage and manufacture process is irrelevant.The constant method that ensures this electric current is known, and its external action is shown in Fig. 3 a.This switching is opened and is turn-offed and realize by controlling output transistor Q5 and Q6.(this is that appearance is intelligible: electric current output node I in operation
oand I
ob is connected to off chip resistor, and resistance is generally 50 ohm.) key concept of this new-type circuit is to control the mode of MOS transistor Q5 and Q6 to overcome the intrinsic asymmetry of on/off switch in MOS output transistor uses.The voltage of each transistorized control grid is between a pair of MOS transistor.Every pair of MOS transistor is controlled by custom-designed NMOS/PMOS inverter I1 to I4.
Transistor Q2 and Q4 allow the grid of Q5 or Q6 to be pulled to GND, and Q1, Q3 transistor can select to move the grid of Q5 and Q6 to V
cC(deducting threshold voltage).In fact this reduced voltage swing, this be because Q1 and Q3 because " body " effect has higher V
ts.Although voltage swing reduces, this voltage swing is enough greatly to maintain effectively good ON/OFF current ratio.Key of the present invention is the passage of inverter I1 to I4.Be different from and guarantee that CMOS output signal and its input signal have the object of identical waveform (even through reversion), generally manufacturing the target that inverter (its PMOS transistor channels is wider than nmos pass transistor) reaches is the CMOS output that produces distortion.This can expect: on E and EB, input signal and signal complement code will be symmetrical pulse.In the present invention, inverter I1 to I4 is through deflection, thus the output signal of generation distortion, so that compensation Q5 and the intrinsic asymmetry of Q6.In this way, the input of the symmetry on E and EB will be created in I
oand I
othe symmetrical output current pulse of B.
By specific test, the present invention may be better understood, as described in Fig. 3 b, and one of them is PMOS transistor for Q5 and Q6, and four are controlled transistor Q1, Q2, Q3 and Q4 is nmos pass transistor.In such structure, inverter I1 and I3 provide the transmission channel of H → L at a high speed and low speed L → H to the grid of Q1 and Q3.On the contrary, inverter I2 and I4 provide high speed L → H and at a slow speed the passage of L → H to the grid of Q2 and Q4.In addition, Q2 and Q4 have higher gain compared with pull up transistor Q1 and Q3 of its complementation.Such work in combination makes to need a symmetrical shaping to drive signal to produce the switching current from I port to IB port.Fig. 4 shows the shaping pulse of the novel output Drive and Control Circuit of Fig. 3 b.As seen from the figure, the signal and the signal complement code that are input to E and EB are symmetrical, and have certain rise time.V
gi(i=1,2,3,4,5 or 6) are transistor Q
ibe subject to the voltage of the control node of E and EB input action.Please pay special attention to, the rise time of the input pulse of transistor Q5 and Q6 is greater than its fall time.Find through test, above-mentioned method causes in circuit from I
oto I
othe symmetrical switching current of B.It has compensated the difference between Q5 and the turn-on and turn-off curve of Q6 (and all MOS transistor).
The transient response of the difference of current switch/driver of Fig. 3 b and common mode output improves a lot compared to existing technology.In practice, the output current of a single driver and its complementary current to GND, and make potential pulse be coupled to transmission line by an isolating transformer resistively couple of 50 ohm by outside sheet.
The following production method that the explanation transmission time is controlled.
The present invention's independent switch/driver that is coupled by the way, to generate the in check composite pulse of rising and falling time.In this way, can extend rising and falling time and eliminate largely transient state aberration.Especially, if burst transmissions is successively, the pulse of output needs about 2 nanoseconds from logic low to logic high so, and EMI is also inhibited like this.As shown in Figure 5, independently single step postpones, and owing to being greater than the ON time of continuous pulse generator, successively delay line provides.As Fig. 5, each switch is wherein to SW1/SW9, SW2/SW10, and SW3/SW11, etc., represent switch/driver of the present invention.(each independently switch/drive table is shown the switch element of two separation, and corresponding part produces output I by an input E
o, or produce output I by input EB
ob, illustrates at Fig. 3 a and Fig. 3 b.)。Fig. 5 shows and uses 8 levels to obtain output I from input signal E
o(from EB to I
ob) general technology.But this technology is not used the upper limit or the lower limit of the quantity of level.Fig. 6 shows the mode of separately being transmitted by eight switch/drivers in the input voltage pulse of E, and it also shows produced output current pulse.An identical structural transmission EB is to eight complementary switch/drivers.Simple filtration after this dual array, has the pulse of level and smooth rising and falling characteristic to generate, and was 2 nanoseconds on its total time.
As previously mentioned, I1 and I3 are through design, and its N raceway groove is narrower than P raceway groove, and this has aggravated " normally " deflection between PMOS and nmos pass transistor.For manufacture of the present invention, suitable P/N deflection can obtain in the following manner: (a) offer PMOS transistor of inverter I1, its channel width is 60% left and right of nmos pass transistor channel width; (b) offer PMOS transistor of inverter I2, its channel width is 220% left and right of nmos pass transistor channel width.Another pair of phase inverters with above-mentioned be identical (that is, I3 is identical with I1, and I4 is identical with I2).As shown in Figure 4, this H → L level conversion speed of guaranteeing the output of inverter I1 and I3 exceedes L → H level conversion.For inverter I2 and I4, on the one hand, make the size of P raceway groove and N raceway groove asymmetric, to proofread and correct nature deflection.(in preferred embodiment, except the channel length of NMOS driver transistor is 1.3 μ, the passage length of all crystals pipe is all 1.0 μ).
Although it should be noted that some transistors have identical channel length, the NMOS driver in the output transistor Q5 shown in Fig. 7 and Q6 has different channel lengths.Especially, the channel width of Q1 and Q3 be Q2 and Q4 channel width 45%.This has guaranteed that driving transistors is in the present invention due to the needed larger gain of shaping pulse.Q1 narrow raceway groove relative to Q3 also guaranteed V in the time of Q3 conducting
cCand between the grid voltage of transistor Q5, there is significant voltage drop.This can cause the reduction of voltage swing conversely, and therefore reduced output lead on draw.
The test of preferred embodiment of the present invention is used both-end 100 ohm balanced loads (practical application of expection will reach high current drives with 32 cellular arraies), experiment demonstration, and the reduction of voltage swing can reduce common-mode noise output.The introducing of introducing the driving signal of shaping in advance and the minimizing of voltage swing has further suppressed common-mode noise output.This improvement can remain within the scope of wider temperature and supply voltage.In addition, these result of the tests show, this circuit can not be subject to the impact of Duty Cycle Distortion, and have outstanding performance performance during up to 160MBPS at least in data transmission rate.Finally, the result of simulation shows, preferred embodiment of the present invention can be scaled to a meticulousr geometry (channel length is less than or equal to 0.8 μ), and not too large loss in performance.
In above-mentioned discussion for the structure of example of the present invention that is shown in Fig. 3 a and Fig. 3 b.Switch/the driver of composition independency of the present invention forms an array and is coupled to a tapped delay line, to control the ramp time of output signal, and needn't increase filter, the output impedance of transmission line is changed.Fig. 8 shows in Fig. 5 switch/driver in the implementation of the time delay of E port and the input of single step.Delay in the input of continuous switch/driver realizes by introducing RC time constant, and the electric capacity that wherein " C " represents is actually the input capacitance of switch/driver.(obviously, known mode has the option that increases electric capacity.) by select suitable resistor for array, pulse rising and decline curve can regulate according to any required shape.It should be noted that the effect due to delay switch, waveform is not be concerned about; All needs be extend rising and falling time to set in advance.Therefore, be dull (although being should having the ability of those skilled in the art) although calculate the resistance on a specific compound boundary edge of generation, be easy to determine the approximate resistance that will use.In preferred embodiment, obtain linear rising edge and the trailing edge of composite pulse with following resistance: R1=500 ohm, R2=571 ohm, R3=667 ohm, R4=800 ohm, R5=1000 ohm, R6=1333 ohm, R7=2000 ohm, R8=4000 ohm.The effective input capacitance of each switch/driver is about 0.1pF.
Because the rise time of composite pulse is 250ps, the efficiently sampling rate of equivalent sampling system will be 4.0 gigahertzs.The transmission system (or 100 ohm) of considering 50 ohm of both-ends, the parasitic capacitance of the 5pf of generation needs the low pass filter of 1.27GHz, and makes sample frequency decay 10.8db.In addition, other factor, the limit bandwidth (being 350MHz in the situation of Double-strand transmission) of for example isolating transformer, will further make waveform level and smooth.
Obviously, those skilled in the art can be applying in example widely.Although preferred embodiment of the present invention is, one of these application---this example is the upper scheme that preferably completes of the present invention---not in office where face is made restriction.
Claims (7)
1. the line drive of a transmission time control, it is characterized in that: line drive of the present invention is used for exporting the offset current that is referred to the electric current on ground and is referred to ground, described line drive comprises: (a) MOS output transistor, and it is coupling between a constant current source and an electric current output node; (b) a MOS output complementary transistor, it is coupling between described constant-current source and a complementary current output node; (c) a voltage input node is coupled between described output transistor and described output complementary transistor; (d) a complementary voltage input node is coupled between described output transistor and output complementary transistor; (e) control circuit, it provides described output transistor and is proportional to the output current that is applied to the input voltage signal of inputting node to described output node, wherein, described control circuit is by the intrinsic asymmetry of on/off switch in compensating MOS transistor.
2. the line drive controlled of a kind of transmission time according to claim 1, is characterized in that: control circuit comprises: (a) high-order output transistor driver is coupled between the power supply of high potential and the control node of described output transistor; (b) the output transistor driver of a low level is coupled between the power supply of electronegative potential and the control node of described output transistor; (c) first inverter and second inverter; Wherein, the input of the first described inverter is directly connected to input node, exports the control node that is directly connected to high-order output transistor driver, and the input of the second described inverter is directly connected to complementary voltage input, exports the control node that is directly connected to low level output complementary transistor driver.
3. the line drive of a kind of transmission time control according to claim 2, is characterized in that: described the first inverter is a CMOS level that contains P raceway groove and N raceway groove, and the second described inverter is a CMOS level that contains P raceway groove and N raceway groove.
4. the line drive of a kind of transmission time control according to claim 3, is characterized in that: the output transistor driver of high-order output transistor driver and low level is nmos pass transistor.
5. the line drive of a kind of transmission time control according to claim 4, is characterized in that: described output transistor and output complementary transistor are PMOS transistors.
6. the line drive of a kind of transmission time control according to claim 5, is characterized in that: the P raceway groove of described the first inverter is less than the N raceway groove of described the first inverter, and the P raceway groove of the second inverter is greater than the N raceway groove of described the second inverter.
7. the line drive of a kind of transmission time control according to claim 6, is characterized in that: the P raceway groove of the first described inverter is about 60% of N channel width, and the N raceway groove of the second described inverter is about 50% of P channel width.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320760729.XU CN203984392U (en) | 2013-11-27 | 2013-11-27 | The line drive that a kind of transmission time is controlled |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320760729.XU CN203984392U (en) | 2013-11-27 | 2013-11-27 | The line drive that a kind of transmission time is controlled |
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| Publication Number | Publication Date |
|---|---|
| CN203984392U true CN203984392U (en) | 2014-12-03 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320760729.XU Expired - Lifetime CN203984392U (en) | 2013-11-27 | 2013-11-27 | The line drive that a kind of transmission time is controlled |
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| CN (1) | CN203984392U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103780246A (en) * | 2013-11-27 | 2014-05-07 | 苏州贝克微电子有限公司 | Wire driver of transmission time control |
| CN108023798A (en) * | 2016-11-02 | 2018-05-11 | 恩智浦美国有限公司 | CAN module and its method |
| CN111869070A (en) * | 2018-04-16 | 2020-10-30 | 三电汽车部件株式会社 | Power conversion device |
-
2013
- 2013-11-27 CN CN201320760729.XU patent/CN203984392U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103780246A (en) * | 2013-11-27 | 2014-05-07 | 苏州贝克微电子有限公司 | Wire driver of transmission time control |
| CN108023798A (en) * | 2016-11-02 | 2018-05-11 | 恩智浦美国有限公司 | CAN module and its method |
| CN108023798B (en) * | 2016-11-02 | 2021-06-22 | 恩智浦美国有限公司 | CAN module and method thereof |
| CN111869070A (en) * | 2018-04-16 | 2020-10-30 | 三电汽车部件株式会社 | Power conversion device |
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Address after: 215000 Building 1, No. 150, Jici Road, science and Technology City, high tech Zone, Suzhou City, Jiangsu Province Patentee after: Suzhou Baker Microelectronics Co.,Ltd. Address before: Room 1404, building 3, No. 209, Zhuyuan Road, high tech Zone, Suzhou, Jiangsu 215011 Patentee before: SUZHOU BAKER MICROELECTRONICS Co.,Ltd. |
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