CN203968394U - A kind of Underground Mine 3G wireless network base station - Google Patents
A kind of Underground Mine 3G wireless network base station Download PDFInfo
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- CN203968394U CN203968394U CN201420275895.5U CN201420275895U CN203968394U CN 203968394 U CN203968394 U CN 203968394U CN 201420275895 U CN201420275895 U CN 201420275895U CN 203968394 U CN203968394 U CN 203968394U
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Abstract
The utility model relates to Underground Mine communication apparatus technical field, a kind of Underground Mine 3G wireless network base station is provided, it comprises shell, master control borad and power panel, wherein, master control borad is provided with the power circuit being electrically connected with described power panel, described power circuit comprises first order power circuit, second level power circuit and third level power circuit, wherein, the circuit voltage stabilizing of the 18V that first order power circuit provides power panel or 12V is depressured to 9V, the voltage voltage stabilizing of the 9V that second level power circuit provides first order power circuit is depressured to 5V, the voltage step-down of the 5V that third level power circuit provides second level power circuit is transformed into 1.2V, the output of 2.5V and 3.3V, simultaneously, the first filter circuit is set in power circuit, the second filter circuit and the 3rd filter circuit, respectively circuit voltage is protected, guarantee the fail safe that base station, down-hole is used, improve the explosion-proof performance of base station.
Description
Technical field
The utility model belongs to Underground Mine communication apparatus technical field, relates in particular to a kind of Underground Mine 3G wireless network base station.
Background technology
At present, colliery mainly contains two kinds of mining types, underground mining and strip mining transformation, for burying darker coal resources, China generally adopts the mode of underground mining, and wherein, well depth is generally just more than 400 meters, its geological conditions and environmental condition more complicated, such as mine gas, water, fire, mine dust and toxic gas etc.Due to may exist moist of down-hole or contain certain inflammable and explosive gaseous environment, use danger electric or that electric equipment existence is larger, therefore, the electric equipment using in down-hole all needs to carry out technological processing for explosion protection feature, and common technological processing for explosion protection feature mode mainly contains flame proof method and intrinsic safety method at present.
Along with the development of mechanics of communication, the communication apparatus using on public network is progressively transplanted in Underground Mine environment, such as common communication base station, handheld terminal etc., and wherein, the technological processing for explosion protection feature of base station is the work of an outbalance.
Utility model content
The purpose of this utility model is to provide a kind of explosion-proof performance stronger, the Underground Mine 3G wireless network base station that coefficient of safety is higher.
The utility model is to realize like this, a kind of Underground Mine 3G wireless network base station, described Underground Mine 3G wireless network base station is provided with shell, in described shell, be provided with master control borad and power panel, described master control borad is provided with the power circuit being electrically connected with described power panel, described power circuit comprises first order power circuit, second level power circuit and third level power circuit, wherein:
Described first order power circuit comprises rectification circuit, described rectification circuit connects pin 1 and the pin 2 of integrated chip J10, be connected in parallel the 4th pin GND of the first step-down conversion chip U1 of the pin 3 of described integrated chip J10 and pin 4 and described rectification circuit, between the 4th pin GND of described the first step-down conversion chip U1 and described rectification circuit, form successively the first current node, the second current node and the 3rd current node, the described first current node other end is electrically connected with the 2nd pin IN of described the first step-down conversion chip U1 by the 4th current node, described the 4th current node other end is electrically connected the 7th pin EN of described the first step-down conversion chip U1 by the 5th current node, described the 5th current node is electrically connected with the 4th pin GND of described the first step-down conversion chip U1 by described the 3rd current node, the other end of described the second current node extends ground connection, the 3rd pin SW ground connection of described the first step-down conversion chip U1, the 1st pin BS electrical connection 9V voltage output end VCC_9.0V of described the first step-down conversion chip U1, the output of the 5th pin FB of described the first step-down conversion chip U1 forms the 6th current node between the 1st pin BS of described the first step-down conversion chip U1 and described 9V voltage output end VCC_9.0V, between the 1st pin BS of described the 6th current node and described the first step-down conversion chip U1, be electrically connected with successively capacitor C 2 and inductance L 1, the 6th pin COMP of described the first step-down conversion chip U1 is electrically connected with the 8th pin SS of the first step-down conversion chip U1 by capacitor C 4 and capacitor C 6:
Described second level power circuit comprises the second step-down conversion chip U21, the 2nd pin IN of described the second step-down conversion chip U21 is electrically connected with the 9V voltage output end VCC_9.0V of described first order power circuit, between the 7th pin EN of the 2nd pin IN of described the second step-down conversion chip U21 and described the second step-down conversion chip U21, form the 8th current node and the 9th current node, described the 8th current node is by capacitor C 150 ground connection, described the 9th current node is electrically connected with the 4th pin GND of described the second step-down conversion chip U21 by capacitor C 151, the 1st pin BS electrical connection 5V voltage output end VCC_5.0V of described the second step-down conversion chip U21, between the 1st pin BS of described the second step-down conversion chip U21 and 5V voltage output end VCC_5.0V, form the tenth current node, the 11 current node, the 12 current node and the 13 current node, wherein, described the tenth current node, shunt capacitance C153 and capacitor C 154 between the 11 current node, between described the 12 current node and the 13 current node, be provided with the first filter circuit, the 6th pin COMP of described the second step-down conversion chip U21 is electrically connected with the 8th pin SS of described the second step-down conversion chip U21 by capacitor C 155 and capacitor C 156,
Described third level power circuit comprises the 3rd step-down conversion chip U20, the 7th pin VCC of described the 3rd step-down conversion chip U20, the 5th pin VINDCDC3, the 36th pin VINDCDC3, the 6th pin VINDCDC3, the 14th pin VSYSIN, the 11st pin HOT_RESET, the 19th pin VINLDO, the 12nd pin DEFLDO1, the 22nd pin LEO_EN, the 23rd pin DCDC3_EN, the 24th pin DCDC2_EN and the 25th pin DCDC1_EN are electrically connected respectively the described 5V voltage output end VCC_5.0V of described second level power circuit, the 0th pin GND of described the 3rd step-down conversion chip U20, the 15th pin VBACKUP, the 16th pin VRTC, the 26th pin TRESPWEON, the 13rd pin DEFLDO2, the 3rd pin PGND3, the 34th pin PGND2, the 10th pin DEFDCDC1, the 8th pin PGND1, the 40th pin AGND1 and the 17th pin AGND2 be ground connection respectively, the 28th pin INT of described the 3rd step-down conversion chip U20, pin VDCDC2 and the 35th pin L2 are electrically connected respectively 3.3V voltage output end VCC_3.3V, the 2nd pin VDCDC3 of described the 3rd step-down conversion chip U20, the 4th pin L3, the 27th pin RESPWRON, the 38th pin PWRFAIL_SNS, the 31st pin PWRFAIL and the 21st pin LOWBAT electrical connection 2.5V voltage output end VCC_2.5V, the 39th pin LOWBAT_SNS connects voltage output end VCC_2.5V by resistance R 17100, described the 20th pin VLDO1 electrical connection LDO_2.8V end, the 18th pin VLDO2 of described the 3rd step-down conversion chip U20 and the 17th pin AGEND2 electrical connection LDO_3.3V end, between the 17th pin AGND2 of described the 3rd step-down conversion chip U20 and described LDO_3.3V end, be provided with the second filter circuit, between described the second filter circuit and described LDO_2.8V end, be provided with the 3rd filter circuit.
As a kind of improved plan, described rectification circuit comprises diode D1, the positive terminal of described diode D1 connects pin 1 and the pin 2 of integrated chip J10, the positive terminal of the negative pole end electrical connection diode D2 of described diode D1, the negative pole end contact resistance R1 of described diode D2, the positive terminal of the other end electrical connection diode D10 of described resistance R 1, forms the 7th current node between the negative pole end of described diode D10 and described the 4th pin GND.
As a kind of improved plan, between described the first current node and described the 4th current node, be electrically connected a capacitor C 1, between described the 5th current node and described the 3rd current node, be electrically connected capacitor C 3, between described the 3rd pin SW and described earth terminal, be electrically connected diode D3, between described capacitor C 4 and C6, be electrically connected resistance R 5.
As a kind of improved plan, described the first filter circuit comprises the diode D10 being electrically connected with the 12 current node and the diode D4 being electrically connected with described the 11 current node, ground connection after described diode D10 and diode D4 parallel connection, series resistor R152 between described diode D4 and the 11 current node.
As a kind of improved plan, described the second filter circuit is composed in parallel by capacitor C 61 and capacitor C 15, and the 3rd filter circuit is made up of capacitor C 16 and C62.
Because Underground Mine 3G wireless network base station comprises shell, master control borad and power panel, wherein, master control borad is provided with the power circuit being electrically connected with described power panel, described power circuit comprises first order power circuit, second level power circuit and third level power circuit, wherein, the circuit voltage stabilizing of the 18V that first order power circuit provides power panel or 12V is depressured to 9V, the voltage voltage stabilizing of the 9V that second level power circuit provides first order power circuit is depressured to 5V, the voltage step-down of the 5V that third level power circuit provides second level power circuit is transformed into 1.2V, the output of 2.5V and 3.3V, simultaneously, the first filter circuit is set in power circuit, the second filter circuit and the 3rd filter circuit, respectively circuit voltage is protected, guarantee the fail safe that base station, down-hole is used, improve the explosion-proof performance of base station.
Brief description of the drawings
Fig. 1 is the structural representation of the Underground Mine 3G wireless network base station that provides of the utility model;
Fig. 2 is the circuit diagram of the first order power circuit that provides of the utility model;
Fig. 3 is the circuit diagram of the second level power circuit that provides of the utility model;
Fig. 4 is the circuit diagram of the third level power circuit that provides of the utility model;
Wherein, 1-shell, 2-master control borad, 3-power panel, 4-power circuit, 41-first order power circuit, 42-second level power circuit, 43-third level power circuit, 5-the first current node, 6-the second current node, 7-the 3rd current node, 8-the 4th current node, 9-the 5th current node, 10-the 6th current node, 11-the 7th current node, 12-the 8th current node, 13-the 9th current node, 14-the tenth current node, 15-the 11 current node, 16-the 12 current node, 17-the 13 current node.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
Fig. 1 shows the structural representation of the Underground Mine 3G wireless network base station that the utility model provides, and for convenience of explanation, has only provided the content relevant to the utility model in figure, wherein:
Underground Mine 3G wireless network base station is provided with shell 1, in described shell 1, be provided with master control borad 2 and power panel 3, described master control borad 2 is provided with the power circuit 4 being electrically connected with described power panel 3, described power circuit 4 comprises first order power circuit 41, second level power circuit 42 and third level power circuit 43, wherein:
As shown in Figure 2, described first order power circuit 41 comprises rectification circuit, described rectification circuit connects pin 1 and the pin 2 of integrated chip J10, be connected in parallel the 4th pin GND of the first step-down conversion chip U1 of the pin 3 of described integrated chip J10 and pin 4 and described rectification circuit, between the 4th pin GND of described the first step-down conversion chip U1 and described rectification circuit, form successively the first current node 5, the second current node 6 and the 3rd current node 7, described first current node 5 other ends are electrically connected with the 2nd pin IN of described the first step-down conversion chip U1 by the 4th current node 8, described the 4th current node 8 other ends are electrically connected the 7th pin EN of described the first step-down conversion chip U1 by the 5th current node 9, described the 5th current node 9 is electrically connected with the 4th pin GND of described the first step-down conversion chip U1 by described the 3rd current node 7, the other end of described the second current node 6 extends ground connection, the 3rd pin SW ground connection of described the first step-down conversion chip U1, the 1st pin BS electrical connection 9V voltage output end VCC_9.0V of described the first step-down conversion chip U1, the output of the 5th pin FB of described the first step-down conversion chip U1 forms the 6th current node 10 between the 1st pin BS of described the first step-down conversion chip U1 and described 9V voltage output end VCC_9.0V, between the 1st pin BS of described the 6th current node 10 and described the first step-down conversion chip U1, be electrically connected with successively capacitor C 2 and inductance L 1, the 6th pin COMP of described the first step-down conversion chip U1 is electrically connected with the 8th pin SS of the first step-down conversion chip U1 by capacitor C 4 and capacitor C 6:
As shown in Figure 3, described second level power circuit comprises the second step-down conversion chip U21, the 2nd pin IN of described the second step-down conversion chip U21 is electrically connected with the 9V voltage output end VCC_9.0V of described first order power circuit, between the 7th pin EN of the 2nd pin IN of described the second step-down conversion chip U21 and described the second step-down conversion chip U21, form the 8th current node 12 and the 9th current node 13, described the 8th current node 12 is by capacitor C 150 ground connection, described the 9th current node 13 is electrically connected with the 4th pin GND of described the second step-down conversion chip U21 by capacitor C 151, the 1st pin BS electrical connection 5V voltage output end VCC_5.0V of described the second step-down conversion chip U21, between the 1st pin BS of described the second step-down conversion chip U21 and 5V voltage output end VCC_5.0V, form the tenth current node 14, the 11 current node 15, the 12 current node the 16 and the 13 current node 17, wherein, described the tenth current node 14, shunt capacitance C153 and capacitor C 154 between the 11 current node 15, the other end of described capacitor C 153 and capacitor C 154 is ground connection respectively, between described the 12 current node the 16 and the 13 current node 17, be provided with the first filter circuit, the 6th pin COMP of described the second step-down conversion chip U21 is electrically connected with the 8th pin SS of described the second step-down conversion chip U21 by capacitor C 155 and capacitor C 156,
As shown in Figure 4, described third level power circuit comprises the 3rd step-down conversion chip U20, the 7th pin VCC of described the 3rd step-down conversion chip U20, the 5th pin VINDCDC3, the 36th pin VINDCDC3, the 6th pin VINDCDC3, the 14th pin VSYSIN, the 11st pin HOT_RESET, the 19th pin VINLDO, the 12nd pin DEFLDO1, the 22nd pin LEO_EN, the 23rd pin DCDC3_EN, the 24th pin DCDC2_EN and the 25th pin DCDC1_EN are electrically connected respectively the described 5V voltage output end VCC_5.0V of described second level power circuit, the 0th pin GND of described the 3rd step-down conversion chip U20, the 15th pin VBACKUP, the 16th pin VRTC, the 26th pin TRESPWEON, the 13rd pin DEFLDO2, the 3rd pin PGND3, the 34th pin PGND2, the 10th pin DEFDCDC1, the 8th pin PGND1, the 40th pin AGND1 and the 17th pin AGND2 be ground connection respectively, the 28th pin INT of described the 3rd step-down conversion chip U20, pin VDCDC2 and the 35th pin L2 are electrically connected respectively 3.3V voltage output end VCC_3.3V, the 2nd pin VDCDC3 of described the 3rd step-down conversion chip U20, the 4th pin L3, the 27th pin RESPWRON, the 38th pin PWRFAIL_SNS, the 31st pin PWRFAIL and the 21st pin LOWBAT electrical connection 2.5V voltage output end VCC_2.5V, the 39th pin LOWBAT_SNS connects voltage output end VCC_2.5V by resistance R 17100, described the 20th pin VLDO1 electrical connection LDO_2.8V end, the 18th pin VLDO2 of described the 3rd step-down conversion chip U20 and the 17th pin AGEND2 electrical connection LDO_3.3V end, between the 17th pin AGND2 of described the 3rd step-down conversion chip U20 and described LDO_3.3V end, be provided with the second filter circuit, between described the second filter circuit and described LDO_2.8V end, be provided with the 3rd filter circuit.
In the utility model, shown in Fig. 2, rectification circuit comprises diode D1, the positive terminal of described diode D1 connects pin 1 and the pin 2 of integrated chip J10, the positive terminal of the negative pole end electrical connection diode D2 of described diode D1, the negative pole end contact resistance R1 of described diode D2, the positive terminal of the other end electrical connection diode D10 of described resistance R 1, forms the 7th current node 11 between the negative pole end of described diode D10 and described the 4th pin GND.
Simultaneously, in the above-described embodiments, between described the first current node and described the 4th current node, be electrically connected a capacitor C 1, between described the 5th current node and described the 3rd current node, be electrically connected capacitor C 3, between described the 3rd pin SW and described earth terminal, be electrically connected diode D3, between described capacitor C 4 and C6, be electrically connected resistance R 5.
In the utility model, as shown in Figure 3, described the first filter circuit comprises the diode D10 being electrically connected with the 12 current node and the diode D4 being electrically connected with described the 11 current node, ground connection after described diode D10 and diode D4 parallel connection, series resistor R152 between described diode D4 and the 11 current node.
In the utility model, as shown in Figure 4, described in its concrete circuit connection is achieved as follows:
(1), the 7th pin VCC of the 3rd step-down conversion chip U20 with between be electrically connected resistance R 170, after the 5th pin VINDCDC3, the 36th pin VINDCDC3 of the 3rd step-down conversion chip U20 and the circuit parallel connection of the 6th pin VINDCDC3 with between the described 5V voltage output end VCC_5.0V of described second level power circuit and resistance R 170, be electrically connected, form current node, resistance R 170 forms another current node with the 7th pin VCC of described the 3rd step-down conversion chip U20, the rear ground connection of this current node serial connection capacitor C 149;
(2), the described 5V voltage output end VCC_5.0V of the 14th pin VSYSIN of the 3rd step-down conversion chip U20 and second level power circuit forms current node, and be electrically connected with it by resistance R 165, the other end of this current node is by the rear ground connection of serial connection capacitor C 146;
(3), the 15th pin VBACKUP of the 3rd step-down conversion chip U20 is connected in series the rear ground connection of capacitor C 147, the rear ground connection of the 16th pin VRTC serial connection capacitor C 148 of the 3rd step-down conversion chip U20;
(4), after the 11st pin HOT_RESET series resistor R164 of the 3rd step-down conversion chip U20, be electrically connected with the described 5V voltage output end VCC_5.0V of second level power circuit;
(5), the 38th pin PWRFAIL_SNS of the 3rd step-down conversion chip U20, the 31st pin PWRFAIL and the 21st pin are respectively by being electrically connected with voltage output end VCC_2.5V after resistance R 160, resistance R 159 and resistance R 168 parallel connections;
(6), the 26th pin of the 3rd step-down conversion chip U20 is connected in series the rear ground connection of capacitor C 124, ground connection after the 13rd pin DEFLDO2 series resistor R157;
(7), after the 12nd pin DEFLDO1 series resistor R156 of the 3rd step-down conversion chip U20 with the circuit of described the 19th pin VINLDO voltage output end VCC_5.0V that is connected in parallel, after the 22nd pin LEO_EN series resistor R156, be electrically connected with voltage output end VCC_5.0V;
(8), after the 28th pin INT series resistor R138 of the 3rd step-down conversion chip U20, connect voltage output end VCC_3.3V;
(9), the 29th pin SDAT of the 3rd step-down conversion chip U20 connects the Data Control line of SDA composition, the clock output line of the 30th pin SCLK composition, formation SDA and SCL composition I
2c bus;
(10), the 23rd pin DCDC3_EN, the 24th pin DCDC2_EN of the 3rd step-down conversion chip U20 and the 25th pin DCDC1_EN be respectively after corresponding series resistor R163, resistance R 162, resistance R 161, the described 5V voltage output end VCC_5.0V of the described second level of electrical connection in parallel power circuit;
(11), between the 2nd pin VDCDC3 of the 3rd step-down conversion chip U20 and described 2.5V voltage output end VCC_2.5V, form successively three current node, the 4th filter circuit after in parallel between latter two current node, the 4th filter circuit is made up of capacitor C 157 and C159 parallel connection, its other end ground connection, the other end of last current node is series resistor R175 and resistance R 179 successively, wherein after the 4th pin L3 tandem electric inductance L43, is electrically connected with first of above-mentioned three current node;
(12), between the pin VDCDC2 of the 3rd step-down conversion chip U20 and 3.3V voltage output end VCC_3.3V, form successively three current node, the 5th filter circuit in parallel between latter two current node, the 5th filter circuit is by capacitor C 161 and capacitor C 162 and form, its other end ground connection, is electrically connected first current node in these three current node after the 35th pin L2 tandem electric inductance L43;
(13), the 9th pin VDCDC1 of the 3rd step-down conversion chip U20 is by the 6th filter circuit electrical connection 1.2V voltage output end VCC_1.2V, wherein, the 6th filter circuit is composed in parallel by capacitor C 158 and capacitor C 160, its other end ground connection, is electrically connected with the 6th filter circuit after the 7th pin L1 tandem electric inductance L42;
(14), the 27th pin RESPWRON of the 3rd step-down conversion chip U20 is electrically connected 2.5V voltage output end VCC_2.5V by resistance R 151.
(15), the second filter circuit composes in parallel by capacitor C 61 and capacitor C 15, the 3rd filter circuit is made up of capacitor C 16 and C62.
For the ease of understanding, the following type configure parameter that provides each element in the utility model:
In first order power circuit shown in Fig. 2:
Diode D1, D2, D3 are SK34,3A;
The capacitance of capacitor C 1 is 2.2uF, and rated voltage is 35V, and the capacitance of capacitor C 2, C3 and C4 is 10nF, and the capacitance of capacitor C 5 is 1uF, and capacitor C 6 is patch capacitor, and its capacitance is 0.1uF;
The resistance value of resistance R 1 is 4.7K ohm, and the resistance value of resistance R 2 is 8.7K ohm, and resistance R 3 and R4 are reserved resistance, and wherein, resistance R 1 and resistance R 2 are Chip-R 0805;
Inductance L 1 adopts the MSS1038_123KL of 4A, 10uH.
Wherein, the first order power circuit input capacitance shown in Fig. 2 and output capacitance and be less than 4.7uF;
In second level power circuit shown in Fig. 3:
Diode D9 is SK34,3A, diode D10 rated voltage 5.6V, power 5W;
The capacitance of capacitor C 150 is 1uF, and rated voltage is 35V, and the capacitance of capacitor C 151, C152 is 10nF, and the capacitance of capacitor C 153 is 1uF, and capacitor C 156 is patch capacitor, and its capacitance is 0.1uF;
The resistance value of resistance R 167 is 8.7K ohm, the resistance value of resistance R 172 is 2.27K ohm, the resistance value of resistance R 173 is 1K ohm, the resistance value of resistance R 174 is 5.6K ohm, the resistance value of resistance R 152 is 10K ohm, wherein, resistance R 167, resistance R 172, resistance R 173, resistance R 174 are Chip-R 0805;
Inductance L 41 also adopts the MSS1038_123KL of 4A, 10uH.
Wherein, the second level power circuit input capacitance shown in Fig. 3 is no more than the output capacitance of first order power circuit;
In third level power circuit shown in Fig. 4:
The capacitance of capacitor C 140, C147 is 1uF, the capacitance of capacitor C 160, C162, C61, C62 is 10nF, and the capacitance of capacitor C 159, C158, C161, C15, C16 is 0.1uF, and capacitor C 124 is 1500pF, the capacitance of capacitor C 148 and capacitor C 149 is 2.2uF;
The resistance value of resistance R 164 is 100K ohm, the resistance value of resistance R 175 is 3.2K ohm, the resistance value of resistance R 179 is 1K ohm, and the resistance value of resistance R 151, R156 and R165 is 10K ohm, and the resistance value of resistance R 138, R160, R159, R161, R162 and R168 is 1K ohm;
Inductance L 42, inductance L 43 and inductance L 44 adopt 2.2uH, and electric current is 2A, ME3220 model.
In the utility model, Underground Mine 3G wireless network base station comprises shell, master control borad and power panel, wherein, master control borad is provided with the power circuit being electrically connected with described power panel, described power circuit comprises first order power circuit, second level power circuit and third level power circuit, wherein, the circuit voltage stabilizing of the 18V that first order power circuit provides power panel or 12V is depressured to 9V, the voltage voltage stabilizing of the 9V that second level power circuit provides first order power circuit is depressured to 5V, the voltage step-down of the 5V that third level power circuit provides second level power circuit is transformed into 1.2V, the output of 2.5V and 3.3V, simultaneously, the first filter circuit is set in power circuit, the second filter circuit and the 3rd filter circuit, respectively circuit voltage is protected, guarantee the fail safe that base station, down-hole is used, improve the explosion-proof performance of base station.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any amendments of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (5)
1. a Underground Mine 3G wireless network base station, it is characterized in that, described Underground Mine 3G wireless network base station is provided with shell, in described shell, be provided with master control borad and power panel, described master control borad is provided with the power circuit being electrically connected with described power panel, described power circuit comprises first order power circuit, second level power circuit and third level power circuit, wherein:
Described first order power circuit comprises rectification circuit, described rectification circuit connects pin 1 and the pin 2 of integrated chip J10, be connected in parallel the 4th pin GND of the first step-down conversion chip U1 of the pin 3 of described integrated chip J10 and pin 4 and described rectification circuit, between the 4th pin GND of described the first step-down conversion chip U1 and described rectification circuit, form successively the first current node, the second current node and the 3rd current node, the described first current node other end is electrically connected with the 2nd pin IN of described the first step-down conversion chip U1 by the 4th current node, described the 4th current node other end is electrically connected the 7th pin EN of described the first step-down conversion chip U1 by the 5th current node, described the 5th current node is electrically connected with the 4th pin GND of described the first step-down conversion chip U1 by described the 3rd current node, the other end of described the second current node extends ground connection, the 3rd pin SW ground connection of described the first step-down conversion chip U1, the 1st pin BS electrical connection 9V voltage output end VCC_9.0V of described the first step-down conversion chip U1, the output of the 5th pin FB of described the first step-down conversion chip U1 forms the 6th current node between the 1st pin BS of described the first step-down conversion chip U1 and described 9V voltage output end VCC_9.0V, between the 1st pin BS of described the 6th current node and described the first step-down conversion chip U1, be electrically connected with successively capacitor C 2 and inductance L 1, the 6th pin COMP of described the first step-down conversion chip U1 is electrically connected with the 8th pin SS of the first step-down conversion chip U1 by capacitor C 4 and capacitor C 6:
Described second level power circuit comprises the second step-down conversion chip U21, the 2nd pin IN of described the second step-down conversion chip U21 is electrically connected with the 9V voltage output end VCC_9.0V of described first order power circuit, between the 7th pin EN of the 2nd pin IN of described the second step-down conversion chip U21 and described the second step-down conversion chip U21, form the 8th current node and the 9th current node, described the 8th current node is by capacitor C 150 ground connection, described the 9th current node is electrically connected with the 4th pin GND of described the second step-down conversion chip U21 by capacitor C 151, the 1st pin BS electrical connection 5V voltage output end VCC_5.0V of described the second step-down conversion chip U21, between the 1st pin BS of described the second step-down conversion chip U21 and 5V voltage output end VCC_5.0V, form the tenth current node, the 11 current node, the 12 current node and the 13 current node, wherein, described the tenth current node, shunt capacitance C153 and capacitor C 154 between the 11 current node, between described the 12 current node and the 13 current node, be provided with the first filter circuit, the 6th pin COMP of described the second step-down conversion chip U21 is electrically connected with the 8th pin SS of described the second step-down conversion chip U21 by capacitor C 155 and capacitor C 156,
Described third level power circuit comprises the 3rd step-down conversion chip U20, the 7th pin VCC of described the 3rd step-down conversion chip U20, the 5th pin VINDCDC3, the 36th pin VINDCDC3, the 6th pin VINDCDC3, the 14th pin VSYSIN, the 11st pin HOT_RESET, the 19th pin VINLDO, the 12nd pin DEFLDO1, the 22nd pin LEO_EN, the 23rd pin DCDC3_EN, the 24th pin DCDC2_EN and the 25th pin DCDC1_EN are electrically connected respectively the described 5V voltage output end VCC_5.0V of described second level power circuit, the 0th pin GND of described the 3rd step-down conversion chip U20, the 15th pin VBACKUP, the 16th pin VRTC, the 26th pin TRESPWEON, the 13rd pin DEFLDO2, the 3rd pin PGND3, the 34th pin PGND2, the 10th pin DEFDCDC1, the 8th pin PGND1, the 40th pin AGND1 and the 17th pin AGND2 be ground connection respectively, the 28th pin INT of described the 3rd step-down conversion chip U20, pin VDCDC2 and the 35th pin L2 are electrically connected respectively 3.3V voltage output end VCC_3.3V, the 2nd pin VDCDC3 of described the 3rd step-down conversion chip U20, the 4th pin L3, the 27th pin RESPWRON, the 38th pin PWRFAIL_SNS, the 31st pin PWRFAIL and the 21st pin LOWBAT electrical connection 2.5V voltage output end VCC_2.5V, the 39th pin LOWBAT_SNS connects voltage output end VCC_2.5V by resistance R 17100, described the 20th pin VLDO1 electrical connection LDO_2.8V end, the 18th pin VLDO2 of described the 3rd step-down conversion chip U20 and the 17th pin AGEND2 electrical connection LDO_3.3V end, between the 17th pin AGND2 of described the 3rd step-down conversion chip U20 and described LDO_3.3V end, be provided with the second filter circuit, between described the second filter circuit and described LDO_2.8V end, be provided with the 3rd filter circuit.
2. Underground Mine 3G wireless network base station according to claim 1, it is characterized in that, described rectification circuit comprises diode D1, the positive terminal of described diode D1 connects pin 1 and the pin 2 of integrated chip J10, the positive terminal of the negative pole end electrical connection diode D2 of described diode D1, the negative pole end contact resistance R1 of described diode D2, the positive terminal of the other end electrical connection diode D10 of described resistance R 1, forms the 7th current node between the negative pole end of described diode D10 and described the 4th pin GND.
3. Underground Mine 3G wireless network base station according to claim 1, it is characterized in that, between described the first current node and described the 4th current node, be electrically connected a capacitor C 1, between described the 5th current node and described the 3rd current node, be electrically connected capacitor C 3, between described the 3rd pin SW and described earth terminal, be electrically connected diode D3, between described capacitor C 4 and C6, be electrically connected resistance R 5.
4. Underground Mine 3G wireless network base station according to claim 1, it is characterized in that, described the first filter circuit comprises the diode D10 being electrically connected with the 12 current node and the diode D4 being electrically connected with described the 11 current node, ground connection after described diode D10 and diode D4 parallel connection, series resistor R152 between described diode D4 and the 11 current node.
5. Underground Mine 3G wireless network base station according to claim 1, is characterized in that, described the second filter circuit is composed in parallel by capacitor C 61 and capacitor C 15, and the 3rd filter circuit is made up of capacitor C 16 and C62.
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| CN201420275895.5U CN203968394U (en) | 2014-05-27 | 2014-05-27 | A kind of Underground Mine 3G wireless network base station |
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| CN201420275895.5U CN203968394U (en) | 2014-05-27 | 2014-05-27 | A kind of Underground Mine 3G wireless network base station |
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