CN203910834U - Graphite carrier - Google Patents
Graphite carrier Download PDFInfo
- Publication number
- CN203910834U CN203910834U CN201420319818.5U CN201420319818U CN203910834U CN 203910834 U CN203910834 U CN 203910834U CN 201420319818 U CN201420319818 U CN 201420319818U CN 203910834 U CN203910834 U CN 203910834U
- Authority
- CN
- China
- Prior art keywords
- graphite
- hollow
- hollow out
- silicon chips
- out region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 229910002804 graphite Inorganic materials 0.000 title claims abstract description 40
- 239000010439 graphite Substances 0.000 title claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims description 27
- 239000010703 silicon Substances 0.000 claims description 27
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 9
- 238000007747 plating Methods 0.000 abstract description 4
- 239000012495 reaction gas Substances 0.000 abstract 1
- 239000006117 anti-reflective coating Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 208000007578 phototoxic dermatitis Diseases 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Chemical Vapour Deposition (AREA)
Abstract
The utility model discloses a graphite carrier which comprises a graphite plate, a plurality of hollow-out areas uniformly arranged in the graphite plate, and space stop bars between adjacent hollow-out areas for separating the hollow-out areas. Slots are arranged in the space stop bars for installing metallic hooks, and silicon chips are placed in the hollow-out areas through the metallic hooks. The hollow-out areas are of square shapes with four chamfered angles, and the edge length of the square is 162-166mm, and the diameter of the chamfered angles is 212-216mm. Larger silicon chips can be supported in the hollow-out area through the metallic hooks to meet requirements of larger silicon chips. Since the size of the hollow-out areas of a graphite frame is similar to the size of the silicon chips and the gaps between the two are smaller, the possibility of reaction gas extending from the positive side to the back side of the silicon chips is small, the color difference of the edges of the silicon chips during flat PECVD film plating is minimized, and lowering quality due to reverse plating of the back side is reduced.
Description
Technical field
The utility model relates to technical field of solar batteries, relates in particular to a kind of graphite carrying plate.
Background technology
In order to improve the sunken photosensitiveness in crystal silicon cell front, normal surface-texturing and the antireflective coating technology of adopting in industry, to reduce battery front side to sun reflection of light.Wherein, antireflective coating generally adopts plasma enhancing vapour deposition (PECVD) to prepare.In preparing the process of antireflective coating, silicon chip need be placed on graphite carrying plate, then paper film support plate is placed in to PECVD equipment, carry out afterwards deposition process.
Yet developing rapidly of photovoltaic industry, needs constantly to reduce Material Cost, improves the power of solar battery sheet, reduces production costs, and improves energy output.
In order to obtain the higher power of battery, can be by adopting more large-area silicon chip to prepare solar battery sheet.
Yet if use larger sized silicon chip, existing graphite carrying plate just can not be suitable for again.
Therefore, be necessary graphite carrying plate to improve.
Utility model content
Main purpose of the present utility model is to provide a kind of graphite carrying plate, thereby is applicable to larger sized silicon chip, further improves the conversion efficiency of solar cell.
For achieving the above object, the utility model provides a kind of graphite carrying plate, for board-like PECVD operation, comprising:
Graphite cake, is evenly provided with some hollow outs region on described graphite cake, spaced apart by spacer bar between adjacent hollow out region;
On described spacer bar, be provided with draw-in groove, for metal hanger is installed; Silicon chip is positioned in described hollow out region by described metal hanger; Wherein:
Described hollow out region is four jiaos of squares with chamfering, and the foursquare length of side is 162-166mm, and the diameter of chamfering is 212-216mm.
Preferably, described silicon chip is put into behind described hollow out region, and the distance of the described hollow out edges of regions of described silicon chip edge distance is 1-3mm.
Preferably, the spacing between adjacent hollow out region is 7-9mm.
Preferably, be provided with two draw-in grooves on each spacer bar, described two draw-in groove positions are placed in the middle, and the spacing between two draw-in grooves is 80mm.
Preferably, described silicon chip is of a size of: length of side 160mm*160mm, chamfering diameter is 210mm.
The quantity in the hollow out region preferably, arranging on described graphite cake is 5 row 10 row or 5 row 9 row.
The utility model, owing to adopting above technical scheme, makes it compared with prior art, has following advantage and good effect:
1) graphite carrying plate that the utility model provides comprises graphite cake, is evenly provided with some hollow outs region on described graphite cake, spaced apart by spacer bar between adjacent hollow out region; On described spacer bar, be provided with draw-in groove, for metal hanger is installed; Silicon chip is positioned in described hollow out region by described metal hanger; Wherein: described hollow out region is four jiaos of squares with chamfering, the foursquare length of side is 162-166mm, and the diameter of chamfering is 212-216mm.Thereby can larger sized silicon chip be supported in hollow out region by metal hanger, to adapt to the requirement of larger sized silicon chip; Due to the very little less reacting gas in the very approaching gap between the two of graphite frame vacancy section domain sizes and die size, there is the probability of the silicon chip back side that front side of silicon wafer spreads simultaneously, the aberration of silicon chip edge while therefore also having reduced panel PECVD plated film, has reduced due to the anti-phenomenon of plating the quality of products causing in the back side.
Accompanying drawing explanation
The schematic diagram of the graphite carrying plate of the 5*10 specification that Fig. 1 provides for the utility model embodiment;
Fig. 2 is the partial enlarged drawing in hollow out region;
Fig. 3 is the partial enlarged drawing of spacer bar;
The schematic diagram of the graphite carrying plate of the 5*9 specification that Fig. 4 provides for the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only for explaining the utility model, and be not used in restriction the utility model.
Please refer to Fig. 1 and Fig. 3 to Fig. 4, the graphite carrying plate that the utility model provides, for board-like PECVD operation, comprise graphite cake 1, on graphite cake 1, be evenly provided with some hollow outs region 2, in the present embodiment, the quantity in the hollow out region 2 arranging on graphite cake 1 is 5 row 10 row, as shown in Figure 1; Spaced apart by spacer bar 3 between adjacent hollow out region 2; On spacer bar 3, be provided with draw-in groove 4, for metal hanger is installed; Silicon chip is positioned in hollow out region 2 by metal hanger; Wherein, vacancy section 2 is four jiaos of squares with chamfering, and the foursquare length of side is 162-166mm, and the diameter of chamfering is 212-216mm.Wherein, the partial enlarged drawing in hollow out region as shown in Figure 2.
It is that the silicon chip that 160mm*160mm, chamfering diameter are 210mm carries out plated film that the graphite carrying plate that the utility model provides can carry the length of side.Use after the silicon chip of this size, the power of single solar cell can improve greatly.
Preferably, silicon chip is put into behind hollow out region 2, and silicon chip edge is 1-3mm apart from the distance at 2 edges, hollow out region.Because graphite frame vacancy section domain sizes and die size approach the probability that the very little less reacting gas in gap between the two has the silicon chip back side that front side of silicon wafer spreads very much, therefore the aberration of silicon chip edge in the time of can reducing panel PECVD plated film, reduces due to the anti-phenomenon of plating the quality of products causing in the back side.
In the present embodiment, the spacing d between adjacent hollow out region 2 is 7-9mm, is preferably 8mm; As shown in Figure 2.
Wherein, on each spacer bar 3, be provided with 4, two draw-in groove 4 positions of two draw-in grooves placed in the middle, and the spacing between two draw-in grooves 4 is 80mm, as shown in Figure 3.
When the quantity in the hollow out region 2 arranging on graphite cake 1 is 5 row 10 row, graphite cake 1 is of a size of 1860mm*1000mm.
Certainly, in other embodiments, the quantity in the hollow out region 2 arranging on graphite cake 1 is 5 row 9 row, and as shown in Figure 4, now, graphite cake 1 is of a size of 1690mm*1000mm.
The foregoing is only preferred embodiment of the present utility model, not thereby limit the scope of the claims of the present utility model.Obviously, those skilled in the art can carry out various changes and modification and not depart from spirit and scope of the present utility model utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model is also intended to comprise these changes and modification interior.
Claims (6)
1. a graphite carrying plate, for board-like PECVD operation, is characterized in that, comprising:
Graphite cake, is evenly provided with some hollow outs region on described graphite cake, spaced apart by spacer bar between adjacent hollow out region;
On described spacer bar, be provided with draw-in groove, for metal hanger is installed; Silicon chip is positioned in described hollow out region by described metal hanger; Wherein:
Described hollow out region is four jiaos of squares with chamfering, and the foursquare length of side is 162-166mm, and the diameter of chamfering is 212-216mm.
2. graphite carrying plate as claimed in claim 1, is characterized in that, described silicon chip is put into behind described hollow out region, and the distance of the described hollow out edges of regions of described silicon chip edge distance is 1-3mm.
3. graphite carrying plate as claimed in claim 1, is characterized in that, the spacing between adjacent hollow out region is 7-9mm.
4. graphite carrying plate as claimed in claim 1, is characterized in that, is provided with two draw-in grooves on each spacer bar, and described two draw-in groove positions are placed in the middle, and the spacing between two draw-in grooves is 80mm.
5. graphite carrying plate as claimed in claim 1, is characterized in that, described silicon chip is of a size of: length of side 160mm*160mm, chamfering diameter is 210mm.
6. graphite carrying plate as claimed in claim 1, is characterized in that, the quantity in the hollow out region arranging on described graphite cake is 5 row 10 row or 5 row 9 row.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420319818.5U CN203910834U (en) | 2014-06-16 | 2014-06-16 | Graphite carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420319818.5U CN203910834U (en) | 2014-06-16 | 2014-06-16 | Graphite carrier |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203910834U true CN203910834U (en) | 2014-10-29 |
Family
ID=51785085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420319818.5U Expired - Lifetime CN203910834U (en) | 2014-06-16 | 2014-06-16 | Graphite carrier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203910834U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465465A (en) * | 2014-12-19 | 2015-03-25 | 百力达太阳能股份有限公司 | Graphite carrier for plate type PECVD |
-
2014
- 2014-06-16 CN CN201420319818.5U patent/CN203910834U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465465A (en) * | 2014-12-19 | 2015-03-25 | 百力达太阳能股份有限公司 | Graphite carrier for plate type PECVD |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20141029 |
|
| CX01 | Expiry of patent term |