CN203910802U - Active pixel with variable capacitance at floating node and image sensor - Google Patents

Active pixel with variable capacitance at floating node and image sensor Download PDF

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Publication number
CN203910802U
CN203910802U CN201420307796.0U CN201420307796U CN203910802U CN 203910802 U CN203910802 U CN 203910802U CN 201420307796 U CN201420307796 U CN 201420307796U CN 203910802 U CN203910802 U CN 203910802U
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China
Prior art keywords
floating node
active area
type
pixel
transistor
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Expired - Fee Related
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CN201420307796.0U
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Chinese (zh)
Inventor
郭同辉
旷章曲
唐冕
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Beijing Superpix Micro Technology Co Ltd
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Beijing Superpix Micro Technology Co Ltd
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Abstract

The utility model discloses an active pixel with variable capacitance at the floating node and an image sensor. The active pixel comprises a photosensitive element in a semiconductor substrate, a transmitting transistor between the sensitive element and the floating node, a reset transistor connected to the floating node, a source-following transistor connected to the floating node, a switching transistor and a column line, wherein an active region of the floating node comprises an N-type heavily doped active region and an N-type lightly doped active region, both the N-type heavily doped active region and the N-type lightly doped active region are placed in a P well, and the side surface of the N-type lightly doped active region makes contact with the N-type heavily doped active region. The dynamic scope of the image sensor is broadened, and the signal to noise ratio is increased.

Description

Floating node has source image pixel and the imageing sensor of variable capacitance
Technical field
The utility model relates to a kind of image sensor pixel, relates in particular to source image pixel and imageing sensor that a kind of floating node has variable capacitance.
Background technology
Imageing sensor has been widely used in digital camera, cell phone, medicine equipment, automobile and other application scenarios.Particularly manufacture the fast development of CMOS (CMOS (Complementary Metal Oxide Semiconductor)) image sensor technologies, make people have higher requirement to the output image quality of imageing sensor.
In the prior art, the floating node place of cmos image sensor pixel generally all adopts fixed capacity, as shown in Figure 1, is to adopt the transistorized active pixel of cmos image sensor four, in the art also referred to as 4T active pixel.The components and parts of 4T active pixel comprise: transistor 104 and switching transistor 105 are followed in photodiode 101, transmission transistor 102, reset transistor 103, source.Photodiode 101 receives the light of extraneous incident, produce photosignal, turn-on transistor 102, after being transferred to floating node FD (Floating Diffusing), photosignal closes transistor 102, this photosignal is followed transistor 104 by source and is detected, opening switch transistor 105, reads signal by row bit line 106 simultaneously.Wherein, the photosignal amount producing in photodiode 101 is directly proportional to incident illumination amount, and the signal that transistor 104 detects in FD place is also proportional with the quantity of illumination.
The photoelectric respone of such imageing sensor is linear, is called as linear transducer in this area.The quantity of illumination scope that linear transducer detects is little, particularly under high lighting environment, be beyond recognition out information in kind, can not gather from half-light thread environment and change to the whole signals high light thread environment, in the field of business to be called dynamic range little, thereby reduced the output image quality of transducer.
Utility model content
The purpose of this utility model is to provide a kind of higher pixel dynamic range and signal to noise ratio, and floating node has source image pixel and the imageing sensor of variable capacitance.
The purpose of this utility model is achieved through the following technical solutions:
Active pixel of the present utility model, comprise that being placed in photo-sensitive cell, the transmission transistor between photo-sensitive cell and floating node of semiconductor substrate, the reset transistor that is connected floating node, the source that connects floating node follows transistor and switching transistor and row bit line, the active area of described floating node comprises N-type heavy doping active area and N-type light dope active area, described N-type heavy doping active area and N-type light dope active area are all positioned at P trap, and a side of described N-type light dope active area contacts with described N-type heavy doping active area.
Imageing sensor of the present utility model, this imageing sensor comprises above-mentioned active pixel.
The technical scheme being provided by above-mentioned the utility model can be found out, the floating node that the utility model embodiment provides has source image pixel and the imageing sensor of variable capacitance, because the active area of active pixel floating node comprises N-type heavy doping active area and N-type light dope active area, N-type heavy doping active area and N-type light dope active area are all positioned at P trap, and a side of N-type light dope active area contacts with N-type heavy doping active area, improve the dynamic range of imageing sensor, also increased signal to noise ratio simultaneously.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of four transistors (4T) active pixel of cmos image sensor in prior art.
Fig. 2 is the schematic diagram of four transistors (4T) active pixel of the cmos image sensor of the utility model embodiment.
Fig. 3 is the floating node active area cross sectional representation of the active pixel of the utility model embodiment.
Fig. 4 is that the utility model embodiment transmits photoelectricity electric charge front and back potential well schematic diagram under low lighting environment.
Fig. 5 is that the utility model embodiment transmits photoelectricity electric charge front and back potential well schematic diagram under high lighting environment.
Fig. 6 is the schematic diagram that is related to of the floating node total capacitance of active pixel of the utility model embodiment and the quantity of electric charge.
Embodiment
To be described in further detail the utility model embodiment below.
Active pixel of the present utility model, its preferably embodiment be:
Comprise that being placed in photo-sensitive cell, the transmission transistor between photo-sensitive cell and floating node of semiconductor substrate, the reset transistor that is connected floating node, the source that connects floating node follows transistor and switching transistor and row bit line, the active area of described floating node comprises N-type heavy doping active area and N-type light dope active area, described N-type heavy doping active area and N-type light dope active area are all positioned at P trap, and a side of described N-type light dope active area contacts with described N-type heavy doping active area.
Described N-type light dope active area comprises is located at surperficial P type silicon, described P type silicon is heavily doped region, described P type silicon below is N-type light doping section, described N-type light doping section exhaust completely electromotive force higher than described photo-sensitive cell exhaust electromotive force completely, and lower than the reset potential of described N-type heavy doping active area.
The thickness of described P type silicon is 0.08 – 0.14um.
The impurity concentration of described P type silicon is 5E19-2E20/cm -3.
The impurity concentration of described N-type light doping section is 6E16-1E17/cm -3.
Described N-type heavy doping active area impurity concentration is 1E19-1E20/cm -3.
Imageing sensor of the present utility model, its preferably embodiment be:
This imageing sensor comprises above-mentioned active pixel.
This imageing sensor is cmos image sensor.
Image sensor pixel of the present utility model, has solved prior art and can not gather the problem that changes to the whole signals high light thread environment from half-light thread environment, to expand the dynamic range of image sensor pixel.In pixel of the present utility model, if intensity of illumination higher than a certain threshold value, light dope active area partition capacitance just can join floating node.With low lighting environment comparison, under high lighting environment, thereby the electric capacity at floating node place increases the signal saturated capacity increase that makes floating node, has improved the dynamic range of imageing sensor, has also increased signal to noise ratio simultaneously.
Specific embodiment:
In cmos image sensor, in order to obtain high-quality image, the utility model is started with from improving the photoelectric respone character of 4T pixel, photoelectric respone sensitivity curve while compressing high lighting environment, increase the photoelectricity electric charge saturated capacity at the floating node FD place of pixel, postpone the saturation time of pixel, expand the dynamic range of transducer.For example, when low lighting environment, the electric capacity of FD is 1.2fF, and the voltage swing of FD is 1V, and electric charge saturated capacity is 7491 so, lucky when saturated the corresponding quantity of illumination be Q 1; If when high lighting environment, the electric capacity of FD is increased to 2fF, and electric charge saturated capacity is increased to 12484, lucky when saturated the corresponding quantity of illumination be Q 2; Thereby sensor pixel can detect illumination zone and increase to 1.67 original (Q 2/ Q 1=12484/7491=1.67) doubly, dynamic range expands original 1.67 times to.The image sensor pixel of working has in this way detected the detailed information how in kind under high lighting environment, thereby has promoted the image quality of transducer output.
In order to realize the technical purpose of above-mentioned expansion dynamic range of sensor, the utility model has been introduced special technique to FD active area on the basis of four transistor pixels, as shown in Figure 2:
101 is photodiode, TX connects the grid of transmission transistor 102, and RX connects the grid of reset transistor 103, and the drain electrode of transistor 103 is used contact hole 203 to be connected with power supply Vdd, SX is connected with the grid of switching transistor 105, and row bit line 106 is signalling channel sense wire.Pixel FD of the present utility model active area is comprised of two parts: N-type heavy doping active area FD1 and N-type light dope active area FD2; Wherein, contact hole 201 is positioned at active area FD1, and the grid that this contact hole is followed transistor 104 by metal wire 202 and source is connected.
Fig. 3 shows the structural representation that active area FD of the present utility model indicates CC ' cross section in Fig. 2.Two parts FD1 of active area FD and FD2 are produced in P trap 304, and 301 is N-type heavy doping active area, and this district's technique is identical with conventional transistor source leakage technique.In the FD2 of active area, 302 of semiconductor silicon surface is that (impurity concentration is 5E19-2E20/cm in P type heavily doped region -3), thickness is 0.08-0.14um, this district is contacting with P trap near STI (Shallow Trench Isolation) side (right side); Below 302 district 303 is N-type light doping section, and wherein a side (left side) in this district contacts with above-mentioned N-type heavy doping active area 301.In the N-type ion concentration photodiode of light doping section 303, slightly high (high impurity concentration can reach 6E16-1E17/cm to N-type ion concentration -3), transistor 103 is opened while carrying out reset operation, and light doping section 303 can be completely depleted.
Fig. 4 shows the potential well graph of a relation that transmits photoelectricity electric charge front and back under low lighting environment.Under low lighting environment, when pixel exposure finishes, photodiode 101 is collected a small amount of electric charge, and has completed FD reset operation, as shown in figure as left in Fig. 4; V wherein pin1for photodiode exhausts electromotive force, V completely pin2for light doping section 303 exhausts electromotive force, V completely fDfor the reference potential after resetting, Vdd is power supply, and the height of above-mentioned electromotive force meets Vdd>V fD>V pin2>V pin1relation, C fD1for the parasitic total capacitance in heavily doped region, C fD2for the parasitic total capacitance in light doping section 303; After FD reset operation completes, the electric charge in photodiode 101 is transferred to floating node FD, as shown in figure as right in Fig. 4.Under low lighting environment, the collected a small amount of electric charge of photodiode 101 is all transferred to the FD1 part of floating node, the low electric charge that do not occupy of FD2 partition capacitance electromotive force, and the light of pixel is CG1=q/C to electric conversion gain fD1(q is the electric weight of an electronics), photoelectric respone linear gradient is proportional to CG1.
Under high lighting environment, when pixel exposure finishes, photodiode 101 is collected a large amount of electric charges, and FD completed reset operation, as shown in figure as left in Fig. 5; After FD reset operation completes, transmission transistor 102 all transfers to floating node FD by the electric charge in 101 potential wells, and electric charge is held by FD1 and FD2 potential well simultaneously; Now FD total capacitance is C fD1with C fD2and, so the light of pixel is CG2=q/ (C to electric conversion gain fD1+ C fD2), photoelectric respone linear gradient is proportional to CG2.As can be known from Fig. 5, FD1 partition capacitance joins the least charge amount needing in FD total capacitance and is
Q C=C FD1(V FD-V pin2)
Due to adding of FD2 partition capacitance, the electric charge maximum that FD holds can increase
Qa=C FD2(V pin2-V pin1)
Fig. 6 is the schematic diagram that is related to of floating node FD total capacitance and its quantity of electric charge.In low surround, FD total capacitance is C min=C fD1; In high surround, FD total capacitance is C max=C fD1+ C fD2; Qc is C fD2join the critical charge amount of FD total capacitance, Q fthe maximum amount of charge that can hold for FD.
Therefore, as described above, the pixel Photoresponse under low lighting environment and high lighting environment is proportional to respectively CG1 and CG2, under high lighting environment due to C fD2join floating node, increased the electric charge saturated capacity of FD, postponed the saturation time of pixel, therefore expanded the dynamic range of pixel.
The above; it is only preferably embodiment of the utility model; but protection range of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement, within all should being encompassed in protection range of the present utility model.Therefore, protection range of the present utility model should be as the criterion with the protection range of claims.

Claims (5)

1. an active pixel, comprise that being placed in photo-sensitive cell, the transmission transistor between photo-sensitive cell and floating node of semiconductor substrate, the reset transistor that is connected floating node, the source that connects floating node follows transistor and switching transistor and row bit line, it is characterized in that, the active area of described floating node comprises N-type heavy doping active area and N-type light dope active area, described N-type heavy doping active area and N-type light dope active area are all positioned at P trap, and a side of described N-type light dope active area contacts with described N-type heavy doping active area.
2. active pixel according to claim 1, is characterized in that, described N-type light dope active area comprises is located at surperficial P type silicon, and described P type silicon is heavily doped region, and described P type silicon below is N-type light doping section.
3. active pixel according to claim 2, is characterized in that, the thickness of described P type silicon is 0.08 – 0.14um.
4. an imageing sensor, is characterized in that, this imageing sensor comprises the active pixel described in claim 1,2 or 3.
5. imageing sensor according to claim 4, is characterized in that, this imageing sensor is cmos image sensor.
CN201420307796.0U 2014-06-10 2014-06-10 Active pixel with variable capacitance at floating node and image sensor Expired - Fee Related CN203910802U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022133A (en) * 2014-06-10 2014-09-03 北京思比科微电子技术股份有限公司 Active pixel with floating diffusing node provided with variable capacitance and image sensor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104022133A (en) * 2014-06-10 2014-09-03 北京思比科微电子技术股份有限公司 Active pixel with floating diffusing node provided with variable capacitance and image sensor
CN104022133B (en) * 2014-06-10 2017-02-08 北京思比科微电子技术股份有限公司 Active pixel with floating diffusing node provided with variable capacitance and image sensor

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