CN203896332U - Six-bit digital delay line - Google Patents
Six-bit digital delay line Download PDFInfo
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- CN203896332U CN203896332U CN201420140703.XU CN201420140703U CN203896332U CN 203896332 U CN203896332 U CN 203896332U CN 201420140703 U CN201420140703 U CN 201420140703U CN 203896332 U CN203896332 U CN 203896332U
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- delay line
- delay
- line
- selector switch
- phases
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Abstract
The utility model discloses a six-bit digital delay line. The delay line comprises an emission/reception input isolation switch, six delay line units and an emission/reception output isolation switch connected in order. Each delay line unit is composed of a corresponding delay line unit input selection switch, a delay line unit phase delay line, a delay line unit phase reference line and a delay line unit output selector switch connected in order. The delay line unit phase delay line is composed of ceramic substrates. Because the ceramic substrates are employed as a new delay line unit phase delay line, the delay line unit volume is decreased, only a single layer circuit can achieve the six-bit digital delay line.
Description
Technical field
The utility model relates to microwave communication field, is specifically related to a kind of six bit digital delay lines.
Background technology
Compared with single slice integration technique, Planar integration digital delay line has the advantages such as technological requirement is low, flexible design, is application form main in current engineering.The time delay of conventional planar integrated digital delay line is to realize by the electrical length of transmission line, therefore, the volume of delay cell increases along with the increase of figure place, thereby cause that delay line components volume is excessive, difficult design degree increases and the problem such as debug difficulties, is conventionally difficult to realize the integrated digital delay line of six bit planes.
For reducing the volume of delay line unit, in multilayer board delay line based on transmission line loading capacitance technology, in succession report, can effectively realize Ku wave band six bit digital delay lines, but this technology is due to reason, the also still prematurity at present such as multi-layer sheet circuit technology complexity, design difficulty be large.
Summary of the invention
The purpose of this utility model is to provide a kind of six bit digital delay lines, has realized six bit digital delay lines of individual layer circuit.
One embodiment of the present of invention are to provide a kind of six bit digital delay lines, comprise connected successively transmitting/receiving input isolating switch, six delay line and transmitting/receiving output isolating switch; Every delay line is by the corresponding delay line input selector switch being connected successively, delay line delay line phase, delay line phase reference line and delay line output selector switch composition; Delay line delay line phase is made up of ceramic substrate.
The technical scheme of the application's six bit digital delay lines, owing to adopting ceramic substrate as new delay line delay line phase, reduces delay line volume, only needs individual layer circuit can realize six bit digital delay lines.
Brief description of the drawings
Accompanying drawing described herein is used to provide further understanding of the present application, forms the application's a part, and the application's schematic description and description is used for explaining the application, and forms the improper restriction to the application.In the accompanying drawings:
Fig. 1 schematically shows according to the structural representation of the six bit digital delay lines of an embodiment of the application;
Fig. 2 schematically shows according to the structural representation of 8 λ delay line delay line phases of the coupled line structure of an embodiment of the application.
In these accompanying drawings, represent same or analogous part with identical reference number;
Wherein, 1, transmitting/receiving input isolating switch; 2, transmitting/receiving output isolating switch; 3,32 λ delay line; 4,1 λ delay line; 5,4 λ delay line; 6,16 λ delay line; 7,8 λ delay line; 8,2 λ delay line; 9, six bit digital delay line switch control modules; 10,32 λ delay line input selector switches; 11,32 λ delay line delay line phases; 12,32 λ delay line phase reference lines; 13,32 λ delay line output selector switch; 14,1 λ delay line input selector switch; 15,1 λ delay line delay line phase; 16,1 λ delay line phase reference line; 17,1 λ delay line output selector switch; 18,4 λ delay line input selector switches; 19,4 λ delay line delay line phases; 20,4 λ delay line phase reference lines; 21,4 λ delay line output selector switch; 22,16 λ delay line input selector switches; 23,16 λ delay line delay line phases; 24,16 λ delay line phase reference lines; 25,16 λ delay line output selector switch; 26,8 λ delay line input selector switches; 27,8 λ delay line delay line phases; 28,8 λ delay line phase reference lines; 29,8 λ delay line output selector switch; 30,2 λ delay line input selector switches; 31,2 λ delay line delay line phases; 32,2 λ delay line phase reference lines; 33,2 λ delay line output selector switch; 34, input microstrip line; 35, coupling line; 36, output microstrip line.
Embodiment
For making the application's object, technical scheme and advantage clearer, below in conjunction with drawings and the specific embodiments, the application is described in further detail.
In the following description, quoting of " embodiment ", " embodiment ", " example ", " example " etc. shown to embodiment or the example so described can comprise special characteristic, structure, characteristic, character, element or limit, but be not that each embodiment or example must comprise special characteristic, structure, characteristic, character, element or limit.In addition, reuse phrase " according to the application embodiment " and, although be likely to refer to identical embodiment, not must refer to identical embodiment.
For the sake of simplicity, omitted and well known to a person skilled in the art some technical characterictic in below describing.
According to the application embodiment, a kind of X-band Planar integration six bit digital delay lines are provided, as shown in Figure 1, can comprise connected successively transmitting/receiving input isolating switch 1, six delay line and transmitting/receiving output isolating switches 2; Every delay line is by the corresponding delay line input selector switch being connected successively, delay line delay line phase, delay line phase reference line and delay line output selector switch composition; Delay line delay line phase is made up of ceramic substrate.
Wherein, six delay line are respectively 32 λ delay line 3,1 λ delay line 4,4 λ delay line 5,16 λ delay line 6,8 λ delay line 7 and 2 λ delay line 8;
32 λ delay line 3 are made up of 32 λ delay line input selector switch 10,32 λ delay line delay line phase 11,32 λ delay line phase reference line 12 and 32 λ delay line output selector switch 13;
1 λ delay line 4 is made up of 1 λ delay line input selector switch 14,1 λ delay line delay line phase 15,1 λ delay line phase reference line 16 and 1 λ delay line output selector switch 17;
4 λ delay line 5 are made up of 4 λ delay line input selector switch 18,4 λ delay line delay line phase 19,4 λ delay line phase reference line 20 and 4 λ delay line output selector switch 21;
16 λ delay line 6 are made up of 16 λ delay line input selector switch 22,16 λ delay line delay line phase 23,16 λ delay line phase reference line 24 and 16 λ delay line output selector switch 25;
8 λ delay line 7 are made up of 8 λ delay line input selector switch 26,8 λ delay line delay line phase 27,8 λ delay line phase reference line 28 and 8 λ delay line output selector switch 29;
2 λ delay line 8 are made up of 2 λ delay line input selector switch 30,2 λ delay line delay line phase 31,2 λ delay line phase reference line 32 and 2 λ delay line output selector switch 33.
According to the application embodiment, delay line delay line phase adopts ceramic substrate to make, ceramic substrate has the performance of coupled line structure, and therefore, delay line delay line phase can be made up of input microstrip line 34, coupling line 35 and output microstrip line 36; By as shown in Figure 2, taking 8 λ delay line 7 as example, be made up of 8 λ delay line input selector switch 26,8 λ delay line delay line phase 27,8 λ delay line phase reference line 28 and 8 λ delay line output selector switch 29,8 λ delay line delay line phases 27 are made up of input microstrip line 34, coupling line 35 and output microstrip line 36; 8 λ delay line input selector switch 26 and 8 λ delay line output selector switch 29 are at 8 λ, between delay line delay line phase 27 and 8 λ delay line phase reference line 28 transmission lines, switch, obtain two kinds of different phase-shift phases, produced the phase difference (time delay) of radiofrequency signal; By regulating the physical length of coupling line 35, the time of delay that can realize different multiples wavelength.
According to the application embodiment, delay line phase reference line can be made up of microwave substrate.
According to the application embodiment, microwave substrate can be RF60 substrate or Rogers5880 substrate.
According to the application embodiment, 32 λ delay line delay line phases 11 can be connected to form by 48 λ delay line delay line phases 27; 16 λ delay line delay line phases 23 can be connected to form by 28 λ delay line delay line phases 27; Utilize the coupling performance of delay line delay line phase, by can adopt delay line phase cascade in 8 λ delay line and the rational deployment of delay line components to 32 λ delay line delay line phase 11 and 16 λ delay line delay line phases 23, X-band six bit digital delay lines are further realized.
Be to utilize switch to choose different routes to reach the operation principle that postpones object according to delay line, the application selects signal transmission path by the I/O switch that switches each delay line between the two in deferred mode (delay line phase) and benchmark state (phase reference line); Six bit digital delay line switches are controlled by six bit digital delay line switch control modules 9, respectively the I/O switch of six delay line is controlled by six bit digital delay line switch control modules 9, because each delay line has deferred mode and ground state two states, make delay line there are 6 degree combinations of 2, thereby realize the control of the different time of delays to signal; The mode of operation of six bit digital delay lines is controlled by transmitting/receiving input isolating switch 1 and transmitting/receiving output isolating switch 2; All circuit wafers and switch adopt the mode of eutectic to be sintered to cavity.
According to the application embodiment, when transmitting/receiving input isolating switch 1 and transmitting/receiving output isolating switch 2 are all located at transmitting branch, transmitting branch conducting, receiving branch isolation, delay line is operated in emission mode, otherwise, transmitting/receiving input isolating switch 1 and transmitting/receiving output isolating switch 2 are all located at receiving branch, receiving branch conducting, transmitting branch isolation, delay line is operated in receiving mode; Signal is inputted after isolating switch 1 by transmitting/receiving, to pass through successively 32 λ delay line 3,1 λ delay line 4,1 λ delay line 5,16 λ delay line 6,8 λ delay line 7 and 2 λ delay line 8, finally output after transmitting/receiving output isolating switch 2.
Because the application adopts individual layer circuit, therefore can carry out gain compensation to the Insertion Loss of high-order delay line introducing by increasing amplifier, thereby obtain the index requests such as satisfactory gain flatness.
For the application's Planar integration six bit digital delay lines, the application provides a kind of novel delay line, the delay line phase of this delay line is made up of ceramic substrate, delay line volume is reduced greatly, thereby provide a kind of important channel for the integrated six bit digital delay lines of design plane; Planar integration six bit digital delay lines on this basis only need single layer board technique, and technological requirement is simple; Aspect method for designing, owing to having adopted individual layer circuit structure, adopt three dimensional field emulation technology to be easy to design required time of delay, therefore there is the advantages such as design is easy, easy tuning.
The embodiment that the foregoing is only the application, is not limited to the application, and for a person skilled in the art, the application can have various modifications and variations.All within the application's spirit and principle, any amendment of doing, be equal to replacement, improvement etc., within all should being included in the application's claim scope.
Claims (3)
1. six bit digital delay lines, is characterized in that: comprise connected successively transmitting/receiving input isolating switch, six delay line and transmitting/receiving output isolating switch; Described every delay line is by the corresponding delay line input selector switch being connected successively, delay line delay line phase, delay line phase reference line and delay line output selector switch composition; Described delay line delay line phase is made up of ceramic substrate;
Described delay line phase reference line is made up of microwave substrate;
Described six delay line are respectively 32 λ delay line, 1 λ delay line, 4 λ delay line, 16 λ delay line, 8 λ delay line and 2 λ delay line;
Described 32 λ delay line are made up of 32 λ delay line input selector switches, 32 λ delay line delay line phases, 32 λ delay line phase reference lines and 32 λ delay line output selector switch;
Described 1 λ delay line is made up of 1 λ delay line input selector switch, 1 λ delay line delay line phase, 1 λ delay line phase reference line and 1 λ delay line output selector switch;
Described 4 λ delay line are made up of 4 λ delay line input selector switches, 4 λ delay line delay line phases, 4 λ delay line phase reference lines and 4 λ delay line output selector switch;
Described 16 λ delay line are made up of 16 λ delay line input selector switches, 16 λ delay line delay line phases, 16 λ delay line phase reference lines and 16 λ delay line output selector switch;
Described 8 λ delay line are made up of 8 λ delay line input selector switches, 8 λ delay line delay line phases, 8 λ delay line phase reference lines and 8 λ delay line output selector switch;
Described 2 λ delay line are made up of 2 λ delay line input selector switches, 2 λ delay line delay line phases, 2 λ delay line phase reference lines and 2 λ delay line output selector switch.
2. six bit digital delay lines according to claim 1, is characterized in that: described microwave substrate is RF60 substrate or Rogers 5880 substrates.
3. six bit digital delay lines according to claim 1, is characterized in that: described 32 λ delay line delay line phases are connected to form by 48 λ delay line delay line phases; Described 16 λ delay line delay line phases are connected to form by 28 λ delay line delay line phases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420140703.XU CN203896332U (en) | 2014-03-27 | 2014-03-27 | Six-bit digital delay line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420140703.XU CN203896332U (en) | 2014-03-27 | 2014-03-27 | Six-bit digital delay line |
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| Publication Number | Publication Date |
|---|---|
| CN203896332U true CN203896332U (en) | 2014-10-22 |
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| CN201420140703.XU Expired - Fee Related CN203896332U (en) | 2014-03-27 | 2014-03-27 | Six-bit digital delay line |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762479A (en) * | 2016-03-24 | 2016-07-13 | 成都集思科技有限公司 | Multilayer PCB delay line |
-
2014
- 2014-03-27 CN CN201420140703.XU patent/CN203896332U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105762479A (en) * | 2016-03-24 | 2016-07-13 | 成都集思科技有限公司 | Multilayer PCB delay line |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141022 Termination date: 20190327 |
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| CF01 | Termination of patent right due to non-payment of annual fee |