CN105762479A - Multilayer PCB delay line - Google Patents

Multilayer PCB delay line Download PDF

Info

Publication number
CN105762479A
CN105762479A CN201610170594.XA CN201610170594A CN105762479A CN 105762479 A CN105762479 A CN 105762479A CN 201610170594 A CN201610170594 A CN 201610170594A CN 105762479 A CN105762479 A CN 105762479A
Authority
CN
China
Prior art keywords
circuit board
blind hole
layer circuit
inner layer
ground
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610170594.XA
Other languages
Chinese (zh)
Inventor
不公告发明人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHENGDU INTEGRATED SYSTEM TECHNOLOGY Co Ltd
Original Assignee
CHENGDU INTEGRATED SYSTEM TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHENGDU INTEGRATED SYSTEM TECHNOLOGY Co Ltd filed Critical CHENGDU INTEGRATED SYSTEM TECHNOLOGY Co Ltd
Priority to CN201610170594.XA priority Critical patent/CN105762479A/en
Publication of CN105762479A publication Critical patent/CN105762479A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P9/00Delay lines of the waveguide type
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0296Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298Multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor

Abstract

The invention discloses a multilayer PCB delay line comprising a circuit board group. The circuit board group comprises a top circuit board, a plurality of internal circuit boards, and a ground circuit board. Insulating boards are arranged between the top circuit board and the highest internal circuit board, between adjacent internal circuit boards, and between the lowest internal circuit board and the ground circuit board. A transition blind hole passes through the center of the circuit board group vertically. A first ground blind hole is arranged between the highest internal circuit board and the ground circuit board. Second ground blind holes are arranged between each internal circuit board and the ground circuit board. A planar circuit is stacked via multilayer board technology so that physical dimension is decreased. Further, the internal circuit boards use strip line circuits and have time delay more than that of the strip line circuits. The strip line is connected with a microstrip line via the transition blind hole, is low in echo loss, and has phase linearity satisfying application.

Description

Multi-layer PCB board delay line
Technical field
The present invention relates to a kind of multi-layer PCB board delay line.
Background technology
Delay line ultimate principle: switching delay line utilizes switch to choose different routes to reach the purpose of phase shift or delay, simply the difference of the switching routes of digital phase shifter is less, not over 360o, and the switching routes of delay line is generally long, mostly is the integral multiple of operation wavelength.For same TEM mould transmission medium, propagation delay time and phase shift have determine for relation, and the certainty of measurement of phase shift is general higher, and therefore general phase-shift characterisitc identifies the delay character of route.
Switching delay line principle is as shown in Figure 1, every delay cell is added two transmission routes by 4 SPDT switch and forms, 2 pairs of SPDT switch switch between the transmission line of two different electrical length, obtain phase-shift phase two kinds different, produce the phase contrast (time delay) of radiofrequency signal:
(1)
Wherein β is phase constant, VPFor phase velocity, f is working frequency points, the length of transmission line of L2 and L1 respectively two different paths.
From formula (1) it can be seen that the delay length of delay line is determined by the phase contrast postponing path and reference path.Therefore, the delay of a high position to be obtained, postpone path and be necessary for sufficiently long electrical length.But, in actual circuit, electrical length is more long, also implies that bigger physical size.In limited space, it is achieved high-order delay has also become a great problem.
Summary of the invention
It is an object of the invention to provide a kind of multi-layer PCB board delay line, planar circuit is stacked by multiple-plate technique, reduce physical size.
For solving above-mentioned technical problem, the present invention provides a kind of multi-layer PCB board delay line, including circuit board group, circuit board group includes a top layer circuit board, some inner layer circuit boards and a grounded circuit plate, between top layer circuit board and the inner layer circuit board of the top, between adjacent inner layer circuit board, and it is equipped with insulation board between the inner layer circuit board of bottom and grounded circuit plate.The center of circuit board group is provided with one longitudinally through transition blind hole therein;It is provided with the first ground connection blind hole between inner layer circuit board and the grounded circuit plate of the top, between each inner layer circuit board and connection circuit plate, is respectively equipped with the second ground connection blind hole.
Further, what top layer circuit board adopted is microstrip circuitry, and what inner layer circuit board adopted is strip-line circuit;Microstrip line on top layer circuit board is connected by transition blind hole with the strip line on each inner layer circuit board.
Further, the first ground connection blind hole and the second ground connection blind hole are with transition blind hole for hollow rounded distribution.
The invention have the benefit that the application is by stacking planar circuit by multiple-plate technique, reduce physical size.Further, what the inner layer circuit board of the application adopted is strip-line circuit, and time delay is more than microstrip circuitry.Strip line realizes transition with microstrip circuitry by transition blind hole and is connected, and its return loss is little, and phase linearity meets application.
Accompanying drawing explanation
Fig. 1 is switching delay line principle schematic;
Fig. 2 is the structural representation of preferred embodiment;
Fig. 3 is the top view of preferred embodiment.
Wherein: 1, top layer circuit board;11, the first ground connection blind hole;12, microstrip line;2, insulation board;3, inner layer circuit board;31, the second ground connection blind hole;32, strip line;4, grounded circuit plate;41, the 3rd ground connection blind hole;5, transition blind hole.
Detailed description of the invention
Below the specific embodiment of the present invention is described; so that those skilled in the art understand the present invention; it is to be understood that; the invention is not restricted to the scope of detailed description of the invention; to those skilled in the art; as long as various changes limit and in the spirit and scope of the present invention determined, these changes are apparent from, and all utilize the innovation and creation of present inventive concept all at the row of protection in appended claim.
Multi-layer PCB board delay line (PCB: printed circuit board) as shown in Figure 2, including circuit board group, circuit board group includes a top layer circuit board 1, some inner layer circuit boards 3 and a grounded circuit plate 4, between the inner layer circuit board 3 of top layer circuit board 1 and the top, between adjacent inner layer circuit board 3, and it is equipped with insulation board 2 between the inner layer circuit board 3 of bottom and grounded circuit plate 4.The center of circuit board group is provided with one longitudinally through transition blind hole 5 therein;Being provided with the first ground connection blind hole 11 between inner layer circuit board 3 and the grounded circuit plate 4 of the top, be respectively equipped with the second ground connection blind hole 31 between each inner layer circuit board 3 and connection circuit plate, grounded circuit plate 4 is by the 3rd ground connection blind hole 41 ground connection.
An embodiment according to the application, what top layer circuit board 1 adopted is microstrip circuitry, and what inner layer circuit board 3 adopted is strip-line circuit;Microstrip line 12 on top layer circuit board 1 is connected by transition blind hole 5 with the strip line 32 on each inner layer circuit board 3.
An embodiment according to the application, as it is shown on figure 3, the first ground connection blind hole 11 and the second ground connection blind hole 31 are with transition blind hole 5 for hollow rounded distribution.
In this application, the sheet material of employing is Rogers4350B and prepreg 4450F, and the two dielectric constant is close and is prone to multi-layer sheet lamination.Further, in this application, top layer microstrip line 121250 Ω live width is 0.54mm, and is only 0.24mm in the strip line 3250 Ω live width of internal layer.
The application, by being stacked by multiple-plate technique by planar circuit, reduces physical size.Further, what the inner layer circuit board 3 of the application adopted is strip-line circuit, and time delay is more than microstrip circuitry.Strip line realizes transition with microstrip line by transition blind hole 5 and is connected, and its return loss is little, and phase linearity meets application.

Claims (3)

1. a multi-layer PCB board delay line, including circuit board group, described circuit board group includes a top layer circuit board, some inner layer circuit boards and a grounded circuit plate, between described top layer circuit board and the inner layer circuit board of the top, between adjacent described inner layer circuit board, and it is equipped with insulation board between the inner layer circuit board of bottom and grounded circuit plate;It is characterized in that, the center of described circuit board group is provided with one longitudinally through transition blind hole therein;It is provided with the first ground connection blind hole between inner layer circuit board and the grounded circuit plate of described the top, between each inner layer circuit board and described connection circuit plate, is respectively equipped with the second ground connection blind hole.
2. multi-layer PCB board delay line according to claim 1, it is characterised in that what described top layer circuit board adopted is microstrip circuitry, what described inner layer circuit board adopted is strip-line circuit;Microstrip line on described top layer circuit board is connected by transition blind hole with the strip line on described each inner layer circuit board.
3. multi-layer PCB board delay line according to claim 1 and 2, it is characterised in that described first ground connection blind hole and the second ground connection blind hole are with transition blind hole for hollow rounded distribution.
CN201610170594.XA 2016-03-24 2016-03-24 Multilayer PCB delay line Pending CN105762479A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610170594.XA CN105762479A (en) 2016-03-24 2016-03-24 Multilayer PCB delay line

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610170594.XA CN105762479A (en) 2016-03-24 2016-03-24 Multilayer PCB delay line

Publications (1)

Publication Number Publication Date
CN105762479A true CN105762479A (en) 2016-07-13

Family

ID=56346393

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610170594.XA Pending CN105762479A (en) 2016-03-24 2016-03-24 Multilayer PCB delay line

Country Status (1)

Country Link
CN (1) CN105762479A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904594A (en) * 2019-02-12 2019-06-18 上海航天电子有限公司 A kind of spaceborne simulation multi-beam receiving antenna of miniaturization ADS-B

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100060379A1 (en) * 2008-09-05 2010-03-11 Asustek Computer Inc. Delay line for printed circuit broad
CN203896332U (en) * 2014-03-27 2014-10-22 成都集思科技有限公司 Six-bit digital delay line
CN204836774U (en) * 2015-06-26 2015-12-02 成都集思科技有限公司 Multilayer PCB board delay line

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100060379A1 (en) * 2008-09-05 2010-03-11 Asustek Computer Inc. Delay line for printed circuit broad
CN203896332U (en) * 2014-03-27 2014-10-22 成都集思科技有限公司 Six-bit digital delay line
CN204836774U (en) * 2015-06-26 2015-12-02 成都集思科技有限公司 Multilayer PCB board delay line

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109904594A (en) * 2019-02-12 2019-06-18 上海航天电子有限公司 A kind of spaceborne simulation multi-beam receiving antenna of miniaturization ADS-B

Similar Documents

Publication Publication Date Title
JP5405851B2 (en) A system for interconnecting two substrates, each containing at least one transmission line
US20130327565A1 (en) Printed circuit board
CN203760616U (en) Power divider multilayer microstrip circuit
US9054404B2 (en) Multi-layer circuit board with waveguide to microstrip transition structure
WO2019128215A1 (en) Strip line directional coupler and coupling degree adjustment method thereof
US6861923B2 (en) Power divider/combiner with a multilayer structure
CN109314290A (en) A kind of phase shifter, phase shift array and communication equipment
CN101436696A (en) Microstrip filter
CN104319448A (en) Multi-layer power distribution network of high-frequency printed boards based on accessory resistive films
EP2862228B1 (en) Balun
CN106532216A (en) 2N-1-path band-shaped power amplifier
CN105762479A (en) Multilayer PCB delay line
KR20190088523A (en) Circuits and Techniques for Via-Leased Beam Formers
CN105390777B (en) A kind of broad-band chip integrated waveguide SIW phase shifters for loading rectangular air slot
CN204836774U (en) Multilayer PCB board delay line
ITTO20080619A1 (en) MULTILAYER STRUCTURE DEVICE WITH A VERTICAL TRANSITION BETWEEN A MICRO STRIP AND A STRIPLINE
CN204045707U (en) Novel combiner
Markley et al. An ultra-compact microstrip crossover inspired by contra-directional even and odd mode propagation
US9178262B2 (en) Feed network comprised of marchand baluns and coupled line quadrature hybrids
SE520792C2 (en) Langeport four-port hybrid microstrip circuit
KR100852003B1 (en) Ground structure using via-holes on pcb and circuit device having the ground structure
CN108900183B (en) Low-loss switch circuit based on dielectric integrated suspension line
US7049905B2 (en) High power directional coupler
JP2010258659A (en) Directional coupler
CN105072800A (en) Structure for realizing microwave coaxial transmission at different layer of PCB board

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160713

WD01 Invention patent application deemed withdrawn after publication