CN204290939U - A kind of six bit digital delay lines based on three-dimensional ceramic substrate - Google Patents
A kind of six bit digital delay lines based on three-dimensional ceramic substrate Download PDFInfo
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- CN204290939U CN204290939U CN201420802185.3U CN201420802185U CN204290939U CN 204290939 U CN204290939 U CN 204290939U CN 201420802185 U CN201420802185 U CN 201420802185U CN 204290939 U CN204290939 U CN 204290939U
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Abstract
The utility model discloses the six bit digital delay lines based on three-dimensional ceramic substrate, comprise the transmitting/receiving input isolating switch, six delay line and the transmitting/receiving that are connected successively and export isolating switch; The delay line phase of every delay line switch is all arranged on ceramic substrate, and is connected with the through hole on ground plane by being arranged at ceramic substrate by multidigit delay line delay line phase; This six bit digital delay line has less volume, and the high-k of pottery makes the volume of delay line reduce further; The maturation of ceramic process makes this delay line have very high machining accuracy, possesses better performance; And utilize the rational deployment of 1 λ, 2 λ, 4 λ, 8 λ, 16 λ, 32 λ delay cells, achieve the integrated of six bit digital delay lines.
Description
Technical field
The utility model relates to field of microwave communication, is specifically related to a kind of six bit digital delay lines based on three-dimensional ceramic substrate.
Background technology
The advantages such as technological requirement is low although Planar integration digital delay line has, flexible design, it is application form main in current engineering, but the time delay of conventional planar integrated digital delay line is realized by the electrical length of transmission line, therefore, the volume of delay cell increases along with the increase of figure place, thus cause that delay line components volume is excessive, difficult design degree increases and the problem such as debug difficulties, be usually difficult to realize the integrated digital delay line of six bit planes.
For reducing the volume of delay line unit, the multilayer board delay line of Based PC B technology is reported in succession, but what adopt due to this technology is thick-film technique, and machining accuracy is not high, therefore can only be applied in comparatively low-frequency range.In addition, the multi-layer sheet delay circuit based on LTCC technology is also reported in succession, can be applied to higher frequency band, but limit by technological level, and LTCC machining accuracy is not high, and processing cost is high.
Utility model content
The purpose of this utility model is to provide a kind of six bit digital delay lines based on three-dimensional ceramic substrate, solves the problem that existing delay line volume is large, machining accuracy is not high.
To achieve these goals, the utility model is by the following technical solutions:
Based on six bit digital delay lines of three-dimensional ceramic structure, comprise the transmitting/receiving input isolating switch, 1 λ delay line, 2 λ delay line, 4 λ delay line, 8 λ delay line, 16 λ delay line, 32 λ delay line and the transmitting/receiving that are connected successively and export isolating switch; 1 λ delay line, 2 λ delay line, 4 λ delay line, 8 λ delay line, 16 λ delay line and 32 λ delay line are all connected with six bit digital delay line switch control modules;
1 λ delay line is made up of 1 λ delay line input selector switch, 1 λ delay line delay line phase, 1 λ delay line phase reference line and 1 λ delay line output selector switch;
2 λ delay line are made up of 2 λ delay line input selector switches, 2 λ delay line delay line phases, 2 λ delay line phase reference lines and 2 λ delay line output selector switch;
4 λ delay line are made up of 4 λ delay line input selector switches, 4 λ delay line delay line phases, 4 λ delay line phase reference lines and 4 λ delay line output selector switch;
8 λ delay line are made up of 8 λ delay line input selector switches, 8 λ delay line delay line phases, 8 λ delay line phase reference lines and 8 λ delay line output selector switch;
16 λ delay line are made up of 16 λ delay line input selector switches, 16 λ delay line delay line phases, 16 λ delay line phase reference lines and 16 λ delay line output selector switch;
32 λ delay line are made up of 32 λ delay line input selector switches, 32 λ delay line delay line phases, 32 λ delay line phase reference lines and 32 λ delay line output selector switch;
1 λ delay line delay line phase is arranged on ceramic substrate, comprises 1 input of λ delay line delay line phase microstrip line, 1 λ delay line delay line phase transmission line and the 1 λ delay line delay line phase be connected successively and exports microstrip line;
2 λ delay line delay line phases are arranged on ceramic substrate, comprise 2 input of λ delay line delay line phase microstrip line, 2 λ delay line delay line phase coupling lines and the 2 λ delay line delay line phases be connected successively and export microstrip line;
4 λ delay line delay line phases are arranged on ceramic substrate, comprise 4 input of λ delay line delay line phase microstrip line, 4 λ delay line delay line phase coupling lines and the 4 λ delay line delay line phases be connected successively and export microstrip line;
8 λ delay line delay line phases comprise the 8 λ delay line delay line phase input microstrip lines be connected successively, 22 λ delay line delay line phases, 14 λ delay line delay line phase and 8 λ delay line delay line phases export microstrip line; Described 2 λ delay line delay line phases and 4 λ delay line delay line phases are all arranged on ceramic substrate, and are connected successively with the through hole on ground plane by the through hole be arranged on ceramic substrate;
16 λ delay line delay line phases comprise the 16 λ delay line delay line phase input microstrip lines be connected successively, 22 λ delay line delay line phases, 34 λ delay line delay line phases and 16 λ delay line delay line phases export microstrip line; Described 22 λ delay line delay line phases and 34 λ delay line delay line phases are all arranged on ceramic substrate respectively, and are connected successively with the through hole of ground plane by being arranged at the through hole on ceramic substrate;
32 λ delay line delay line phases comprise the 32 λ delay line delay line phase input microstrip lines be connected successively, 24 λ delay line delay line phases, 38 λ delay line delay line phases and 32 λ delay line delay line phases export microstrip line; Described 24 λ delay line delay line phases and 38 λ delay line delay line phases are all arranged on ceramic substrate respectively, and are connected successively with the through hole on ground plane by the through hole be arranged on ceramic substrate.
Further, 8 λ delay line delay line phase input microstrip lines and 8 λ delay line delay line phases export microstrip line and are all arranged on ceramic substrate, and are positioned at same plane; Described 16 λ delay line delay line phase input microstrip lines and 16 λ delay line delay line phases export microstrip line and are all arranged on ceramic substrate, and are positioned at same plane; Described 32 λ delay line delay line phase input microstrip lines and 32 λ delay line delay line phases export microstrip line and are all arranged on ceramic substrate, and are positioned at same plane.
Further, 1 λ delay line phase reference line, 2 λ delay line phase reference lines, 4 λ delay line phase reference lines, 8 λ delay line phase reference lines, 16 λ delay line phase reference lines and 32 λ delay line phase reference lines are all arranged on microwave base plate.
The structure of the multilayer delay line based on three-dimensional ceramic structure that the application proposes, has less volume relative to the delay line of planar structure, and the high-k of pottery makes the volume of delay line reduce further; The maturation of ceramic process makes this delay line have very high machining accuracy, possesses better performance; And utilize the rational deployment of 1 λ, 2 λ, 4 λ, 8 λ, 16 λ, 32 λ delay cells, achieve the integrated of six bit digital delay lines.
Accompanying drawing explanation
Fig. 1 is the theory diagram of an embodiment of the six bit digital delay lines based on three-dimensional ceramic structure of the application.
Fig. 2 is the structure chart of an embodiment of the 4 λ delay line based on three-dimensional ceramic structure of the application.
Fig. 3 is the structure chart of an embodiment of the 8 λ delay line based on three-dimensional ceramic structure of the application.
Fig. 4 is the structure chart of an embodiment of the 16 λ delay line based on three-dimensional ceramic structure of the application.
Fig. 5 is the structure chart of an embodiment of the 32 λ delay line based on three-dimensional ceramic structure of the application.
Wherein, 1, transmitting/receiving input isolating switch; 2, transmitting/receiving exports isolating switch; 3, six bit digital delay line switch control modules; 4,1 λ delay line; 5,1 λ delay line input selector switch; 6,1 λ delay line output selector switch; 7,1 λ delay line delay line phase; 8,1 λ delay line phase reference line; 9,2 λ delay line; 10,2 λ delay line input selector switches; 11,2 λ delay line output selector switch; 12,2 λ delay line delay line phases; 13,2 λ delay line phase reference lines; 14,4 λ delay line; 15,4 λ delay line input selector switches; 16,4 λ delay line output selector switch; 17,4 λ delay line delay line phases; 18,4 λ delay line phase reference lines; 19,8 λ delay line; 20,8 λ delay line input selector switches; 21,8 λ delay line output selector switch; 22,8 λ delay line delay line phases; 23,8 λ delay line phase reference lines; 24,16 λ delay line; 25,16 λ delay line input selector switches; 26,16 λ delay line output selector switch; 27,16 λ delay line delay line phases; 28,16 λ delay line phase reference lines; 29,32 λ delay line; 30,32 λ delay line input selector switches; 31,32 λ delay line output selector switch; 32,32 λ delay line delay line phases; 33,32 λ delay line phase reference lines; 34,4 λ delay line delay line phase input microstrip lines; 35,4 λ delay line delay line phase coupling lines; 36,4 λ delay line delay line phases export microstrip line; 37,8 λ delay line delay line phase input microstrip lines; 38,8 λ delay line delay line phases export microstrip line; 39, ceramic substrate; 40, through hole; 41, ground plane; 42,16 λ delay line delay line phase input microstrip lines; 43,16 λ delay line delay line phases export microstrip line; 44,32 λ delay line delay line phase input microstrip lines; 45,32 λ delay line delay line phases export microstrip line.
Embodiment
For making the object of the application, technical scheme and advantage clearly, below in conjunction with drawings and the specific embodiments, the application is described in further detail.
See Fig. 1, Figure 1 shows that the theory diagram of an embodiment of the six bit digital delay lines based on three-dimensional ceramic structure; This six bit digital delay line inputs isolating switch 1 by transmitting/receiving, transmitting/receiving exports isolating switch 2,1 λ delay line 4,2 λ delay line 9,4 λ delay line 14,8 λ delay line 19,16 λ delay line 24,32 λ delay line 29, six bit digital delay line switch control module 3 and forms; Transmitting/receiving input is kept apart 1 pass and is connected successively with 1 λ delay line 4,2 λ delay line 9,4 λ delay line 14,8 λ delay line 19,16 λ delay line 24,32 λ delay line 29 and transmitting/receiving output isolating switch 2; Six bit digital delay line switch control modules 3 are connected with 32 λ delay line 29 with 1 λ delay line 4,2 λ delay line 9,4 λ delay line 14,8 λ delay line 19,16 λ delay line 24.
Wherein, 1 λ delay line 4 is made up of 1 λ delay line input selector switch 5,1 λ delay line delay line phase 7,1 λ delay line phase reference the line 8 and 1 λ delay line output selector switch 6 be connected successively; 2 λ delay line 9 are made up of 2 λ delay line input selector switch 10,2 λ delay line delay line phase 12,2 λ delay line phase reference the line 13 and 2 λ delay line output selector switch 11 be connected successively; 4 λ delay line 14 are made up of 4 λ delay line input selector switch 15,4 λ delay line delay line phase 17,4 λ delay line phase reference the line 18 and 4 λ delay line output selector switch 16 be connected successively; 8 λ delay line 19 are made up of 8 λ delay line input selector switch 20,8 λ delay line delay line phase 22,8 λ delay line phase reference the line 23 and 8 λ delay line output selector switch 21 be connected successively; 16 λ delay line 24 are made up of 16 λ delay line input selector switch 25,16 λ delay line delay line phase 27,16 λ delay line phase reference the line 28 and 16 λ delay line output selector switch 26 be connected successively; 32 λ delay line 29 are made up of 32 λ delay line input selector switch 30,32 λ delay line delay line phase 32,32 λ delay line phase reference the line 33 and 32 λ delay line output selector switch 31 be connected successively.
Wherein, 1 λ delay line delay line phase 7 is arranged on ceramic substrate 39, comprises 1 input of λ delay line delay line phase microstrip line, 1 λ delay line delay line phase transmission line and the 1 λ delay line delay line phase be connected successively and exports microstrip line.
2 λ delay line delay line phases 12 are arranged on ceramic substrate 39, comprise 2 input of λ delay line delay line phase microstrip line, 2 λ delay line delay line phase coupling lines and the 2 λ delay line delay line phases be connected successively and export microstrip line.
As shown in Figure 2,4 λ delay line delay line phases 17 are made up of 4 λ delay line delay line phases input microstrip line 34,4 λ delay line delay line phase the coupling line 35 and 4 λ delay line delay line phases output microstrip lines 36 be connected successively.
As shown in Figure 3,8 λ delay line delay line phases 22 are made up of 8 λ delay line delay line phases input microstrip line 37,8 λ delay line delay line phases output microstrip line 38,2 λ delay line delay line phase 12,2 λ delay line delay line phase 12 and 4 λ delay line delay line phases 17; 2 λ delay line delay line phases 12 are arranged on ceramic substrate 39, and by the through hole 40 on dielectric layer (i.e. ceramic substrate) and ground plane 41(and metal level) on through hole 40 be connected with 2 λ delay line delay line phases 12 of below; 2 λ delay line delay line phases 12 of below are by the through hole 40 on dielectric layer (i.e. ceramic substrate) and ground plane 41(and metal level) on through hole 40 be connected with 4 λ delay line delay line phases 17; 4 λ delay line delay line phases 17 export microstrip line 38 by the through hole 40 on the through hole 40 on dielectric layer (i.e. ceramic substrate) and ground plane (41 i.e. metal level) with 8 λ delay line delay line phases again and are connected; 8 λ delay line delay line phase input microstrip line 37 and 8 λ delay line delay line phases export microstrip line 38 and are positioned at same plane.
As shown in Figure 4,16 λ delay line delay line phases 27 are made up of 22 λ delay line delay line phases 12 and 34 λ delay line delay line phases 17; 22 λ delay line delay line phases 12 with 34 λ delay line delay line phases 17 respectively by the through hole 40 on dielectric layer (i.e. ceramic substrate) and ground plane 41(and metal level) on through hole 40 be connected successively; Each 2 λ delay line delay line phase 12 and 4 λ delay line delay line phases 17 are arranged on ceramic substrate 39 all separately.
As shown in Figure 5,32 λ delay line delay line phases 32 are made up of 24 λ delay line delay line phases 17 and 38 λ delay line delay line phases 22; 24 λ delay line delay line phases 17 with 38 λ delay line delay line phases 22 respectively by the through hole 40 on dielectric layer (i.e. ceramic substrate) and ground plane 41(and metal level) on through hole 40 be connected successively; Each 4 λ delay line delay line phase 17 and 8 λ delay line delay line phases 22 are arranged on ceramic substrate 39 all separately.
Be the operation principle utilizing switch to choose different routes to reach delay object according to delay line, the six bit digital delay lines of the application select signal transmission path by the I/O switch switching each delay line between the two in deferred mode (delay line phase) and benchmark state (phase reference line), in six bit digital delay lines, the I/O switch of each delay line is controlled by six bit digital delay line switch control modules 3, the phase reference line of delay line is made in conventional microwave substrate, as RF60 or Rogers 5880 etc., the delay line phase of delay line is made in ceramic substrate, is individual layer mask-making technology, by 1 λ delay line 4,2 λ delay line 9,4 λ delay line 14,8 λ delay line 19,16 λ delay line 24 is realized six bit digital delay lines with the rational deployment that 32 λ delay line 29 are connected successively, 1 λ delay line delay line phase 7 is made up of transmission line, 2 λ delay line delay line phase 12 and 4 λ delay line delay line phases 17 are made up of the coupling line of compact conformation, 8 λ delay line delay line phases 22 to be connected realization by being arranged on ceramic substrate 39 and the through hole 40 on ground plane 41 successively by 22 λ delay line delay line phases 12 and 14 λ delay line delay line phase 17, 16 λ delay line delay line phases 27 to be connected realization by being arranged on ceramic substrate 39 and the through hole 40 on ground plane 41 successively by 22 λ delay line delay line phases 12 and 34 λ delay line delay line phases 17, 32 λ delay line delay line phases 32 to be connected realization by being arranged on ceramic substrate 39 and the through hole 40 on ground plane 41 with 38 λ delay line delay line phases 22 successively by 34 λ delay line delay line phases 17, the mode of operation of six bit digital delay lines inputs isolating switch 1 by transmitting/receiving and transmitting/receiving output isolating switch 2 controls, all circuit wafers and switch adopt the mode of eutectic to be sintered to cavity.
Transmitting/receiving input isolating switch 1 and transmitting/receiving export isolating switch 2 and are all located at transmitting branch conducting, receiving branch is isolated, then delay line is operated in emission mode, otherwise, transmitting/receiving input isolating switch 1 and transmitting/receiving export isolating switch 2 and are all located at receiving branch conducting, transmitting branch is isolated, then delay line is operated in receiving mode; Signal is by after transmitting/receiving input isolating switch 1,1 λ delay line 1,2 λ delay line 9,4 λ delay line 14,8 λ delay line 19,16 λ delay line 24 and 32 λ delay line 29 will be passed through successively, and eventually pass through after transmitting/receiving exports isolating switch 2 and export.
For 4 λ delay line 14, delay line circuit as shown in Figure 2, be made up of input selector switch, delay line phase, phase reference line and output selector switch, two switches switch between delay line phase and phase reference line transmission line, obtain two kinds of different phase-shift phases, produce the phase difference (time delay) of radiofrequency signal; And by regulating the physical length of coupling line 39, the time of delay of different multiples wavelength can be realized.
The six bit digital delay lines of the application are controlled the I/O switch of six delay line respectively by six bit digital delay line switch control modules, because each delay line has deferred mode and ground state two states, make delay line have 26 kinds of combinations, thus realize the control to the different time of delays of signal.
Claims (3)
1., based on six bit digital delay lines of three-dimensional ceramic substrate, comprise the transmitting/receiving input isolating switch, 1 λ delay line, 2 λ delay line, 4 λ delay line, 8 λ delay line, 16 λ delay line, 32 λ delay line and the transmitting/receiving that are connected successively and export isolating switch; Described 1 λ delay line, 2 λ delay line, 4 λ delay line, 8 λ delay line, 16 λ delay line and 32 λ delay line are all connected with six bit digital delay line switch control modules;
Described 1 λ delay line is made up of 1 λ delay line input selector switch, 1 λ delay line delay line phase, 1 λ delay line phase reference line and 1 λ delay line output selector switch;
Described 2 λ delay line are made up of 2 λ delay line input selector switches, 2 λ delay line delay line phases, 2 λ delay line phase reference lines and 2 λ delay line output selector switch;
Described 4 λ delay line are made up of 4 λ delay line input selector switches, 4 λ delay line delay line phases, 4 λ delay line phase reference lines and 4 λ delay line output selector switch;
Described 8 λ delay line are made up of 8 λ delay line input selector switches, 8 λ delay line delay line phases, 8 λ delay line phase reference lines and 8 λ delay line output selector switch;
Described 16 λ delay line are made up of 16 λ delay line input selector switches, 16 λ delay line delay line phases, 16 λ delay line phase reference lines and 16 λ delay line output selector switch;
Described 32 λ delay line are made up of 32 λ delay line input selector switches, 32 λ delay line delay line phases, 32 λ delay line phase reference lines and 32 λ delay line output selector switch;
It is characterized in that:
Described 1 λ delay line delay line phase is arranged on ceramic substrate, comprises 1 input of λ delay line delay line phase microstrip line, 1 λ delay line delay line phase transmission line and the 1 λ delay line delay line phase be connected successively and exports microstrip line;
Described 2 λ delay line delay line phases are arranged on ceramic substrate, comprise 2 input of λ delay line delay line phase microstrip line, 2 λ delay line delay line phase coupling lines and the 2 λ delay line delay line phases be connected successively and export microstrip line;
Described 4 λ delay line delay line phases are arranged on ceramic substrate, comprise 4 input of λ delay line delay line phase microstrip line, 4 λ delay line delay line phase coupling lines and the 4 λ delay line delay line phases be connected successively and export microstrip line;
Described 8 λ delay line delay line phases comprise the 8 λ delay line delay line phase input microstrip lines be connected successively, 22 λ delay line delay line phases, 14 λ delay line delay line phase and 8 λ delay line delay line phases export microstrip line; Described 2 λ delay line delay line phases and 4 λ delay line delay line phases are all arranged on ceramic substrate, and are connected successively with the through hole on ground plane by the through hole be arranged on ceramic substrate;
Described 16 λ delay line delay line phases comprise the 16 λ delay line delay line phase input microstrip lines be connected successively, 22 λ delay line delay line phases, 34 λ delay line delay line phases and 16 λ delay line delay line phases export microstrip line; Described 22 λ delay line delay line phases and 34 λ delay line delay line phases are all arranged on ceramic substrate respectively, and are connected successively with the through hole of ground plane by being arranged at the through hole on ceramic substrate;
Described 32 λ delay line delay line phases comprise the 32 λ delay line delay line phase input microstrip lines be connected successively, 24 λ delay line delay line phases, 38 λ delay line delay line phases and 32 λ delay line delay line phases export microstrip line; Described 24 λ delay line delay line phases and 38 λ delay line delay line phases are all arranged on ceramic substrate respectively, and are connected successively with the through hole on ground plane by the through hole be arranged on ceramic substrate.
2. the six bit digital delay lines based on three-dimensional ceramic substrate according to claim 1, it is characterized in that: described 8 λ delay line delay line phase input microstrip lines and 8 λ delay line delay line phases export microstrip line and are all arranged on ceramic substrate, and are positioned at same plane; Described 16 λ delay line delay line phase input microstrip lines and 16 λ delay line delay line phases export microstrip line and are all arranged on ceramic substrate, and are positioned at same plane; Described 32 λ delay line delay line phase input microstrip lines and 32 λ delay line delay line phases export microstrip line and are all arranged on ceramic substrate, and are positioned at same plane.
3. the six bit digital delay lines based on three-dimensional ceramic substrate according to claim 1, is characterized in that:
1 λ delay line phase reference line, 2 λ delay line phase reference lines, 4 λ delay line phase reference lines, 8 λ delay line phase reference lines, 16 λ delay line phase reference lines and 32 λ delay line phase reference lines are all arranged on microwave base plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420802185.3U CN204290939U (en) | 2014-12-18 | 2014-12-18 | A kind of six bit digital delay lines based on three-dimensional ceramic substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420802185.3U CN204290939U (en) | 2014-12-18 | 2014-12-18 | A kind of six bit digital delay lines based on three-dimensional ceramic substrate |
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| CN204290939U true CN204290939U (en) | 2015-04-22 |
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| CN201420802185.3U Expired - Fee Related CN204290939U (en) | 2014-12-18 | 2014-12-18 | A kind of six bit digital delay lines based on three-dimensional ceramic substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105846036A (en) * | 2016-03-29 | 2016-08-10 | 成都集思科技有限公司 | Six-phase position digital delay line based on three-dimensional ceramic substrate |
| CN106229600A (en) * | 2016-08-09 | 2016-12-14 | 成都集思科技有限公司 | A kind of wideband delay line component |
-
2014
- 2014-12-18 CN CN201420802185.3U patent/CN204290939U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105846036A (en) * | 2016-03-29 | 2016-08-10 | 成都集思科技有限公司 | Six-phase position digital delay line based on three-dimensional ceramic substrate |
| CN106229600A (en) * | 2016-08-09 | 2016-12-14 | 成都集思科技有限公司 | A kind of wideband delay line component |
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Granted publication date: 20150422 Termination date: 20181218 |
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| CF01 | Termination of patent right due to non-payment of annual fee |