CN203890050U - Micro electro mechanical system and detection circuit - Google Patents

Micro electro mechanical system and detection circuit Download PDF

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Publication number
CN203890050U
CN203890050U CN201320892445.6U CN201320892445U CN203890050U CN 203890050 U CN203890050 U CN 203890050U CN 201320892445 U CN201320892445 U CN 201320892445U CN 203890050 U CN203890050 U CN 203890050U
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switch
circuit
signal
self
electric capacity
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潘华兵
郑泉智
陈灿锋
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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Abstract

The utility model provides a micro electro mechanical system and a detection circuit. Self-testing capacitor arrays in the detection circuit output periodically changed charges, so when the self-testing of the detection circuit is carried out, the operation can be carried out through the periodically changed charges output by the self-testing capacitor arrays, and the condition that the detection circuit driving module needs to generate high-pressure driving signals so that micro electro mechanical self-testing capacitors arranged in a micro electro mechanical sensor output periodical charge signals required by the self-testing is avoided. Therefore the participation of the micro electro mechanical sensor is not needed in the self-testing process of the detection circuit, the self-testing flow process of the detection circuit is simplified, and in addition, the self-testing reliability is improved; meanwhile, micro electro mechanical self-testing capacitors are also not needed in the micro electro mechanical sensor, so the design complexity of the micro electro mechanical sensor and the design difficulty of the detection circuit driving module are reduced.

Description

MEMS and testing circuit
Technical field
The utility model relates to technical field of integrated circuits, particularly a kind of MEMS and testing circuit.
Background technology
MEMS (MEMS) application is more and more, and it mainly comprises micro mechanical sensor and testing circuit, and wherein, micro mechanical sensor needs testing circuit to carry out the variation of detecting sensor, and does corresponding signal processing.What micro mechanical sensor adopted greatly is the mode of capacitance sensing, and the testing circuit of answering is in contrast used for detecting the capacitance variations of micromechanics sensing capacitance.In the starting stage of micro-electro-mechanical system design, need to judge whether micro mechanical sensor and testing circuit can normally work.Micro mechanical sensor can be tested by special detection method, but testing circuit preferably can have a kind of method of self-test to judge the quality of oneself; In addition, in the process using, if whole MEMS has damage, the self-test function that testing circuit carries also can judge that MEMS is that micro mechanical sensor damages or testing circuit damages.
At present, more MEMS adopts micromechanics to realize needed the self-test function of testing circuit electric capacity, in micro mechanical sensor, makes, and has brought higher complexity to like this design of micro mechanical sensor micromechanics; In addition, drive micromechanics self-test electric capacity generally to need higher voltage, this has increased difficulty to the driver module of testing circuit; And completing the participation that self-test needs micro mechanical sensor, this just needs micro mechanical sensor not damage just to carry out.
Please refer to Fig. 1, its structural representation that is existing MEMS.As shown in Figure 1, MEMS comprises testing circuit 10 and micro mechanical sensor 20, wherein, together with micromechanics self-test electric capacity 21 does with micromechanics sensing capacitance 22, forms micro mechanical sensor 20; Micromechanics self-test electric capacity 21 is the same with the way of micromechanics sensing capacitance 22.In self-test, by driver module 11, the pole plate of micromechanics self-test electric capacity 21 is added to needed self-test high-voltage driven signal; The variation of then reading electric capacity by signal-obtaining and the processing module 12 of testing circuit 10, the variation of this capacitance size finally embodies at the output of signal-obtaining and processing module 12, is a magnitude of voltage being different under non-test mode under normal circumstances; Finally judge by this magnitude of voltage whether testing circuit 10 normally works.
Just must be based upon under the condition that micro mechanical sensor 20 can normally work, if micro mechanical sensor 20, due to a variety of causes cisco unity malfunction, cannot complete separately the self-test function of testing circuit 10 self-test of testing circuit 10 like this; And the high-voltage driven signal needing need to additionally provide testing circuit 10 self-test time, and drive signal sometimes to need 20 samplings with micro mechanical sensor to read clock synchronous, increase the design complexities of circuit.
Further, please refer to Fig. 2, its micromechanics that is existing micro mechanical sensor is realized the brief principle figure of self-test.As shown in Figure 2,1S and 2S are the electric signal input ends of self-test high-voltage driven signal, and 1I and 2I are micro mechanical sensor electric charge outputs, and the signal-obtaining of this pair of output and testing circuit is connected with processing module.Add driving signal (for example sine voltage signal) at 1S and 2S self-test input, sine voltage signal produces electrostatic force F by micromechanics self-test capacitor plate e, electrostatic force F epromote micromechanics sensing capacitance and do sinusoidal vibration, from the electric charge of 1I and 2I output sinusoidal variations, with processing module, charge conversion is become to voltage signal by the signal-obtaining that detects micro mechanical sensor, and finally export a corresponding magnitude of voltage, complete self-test.
Be to complete separately self-test function for the very large problem of existing testing circuit, need to lean on micro mechanical sensor, so will cause inconvenience and the reliability of self-test flow process low; In addition because need to provide high pressure and synchronous driving signal to increase so again the design difficulty of testing circuit driver module; Micro mechanical sensor be also because will design the micromechanics self-test electric capacity of one group of comb teeth-shaped more, and improved the design complexities of micro mechanical sensor.
Utility model content
The purpose of this utility model is to provide a kind of MEMS and testing circuit, to solve in prior art, testing circuit cannot complete separately self-test function, need to lean on micro mechanical sensor, so will cause inconvenience and the reliability of self-test flow process low; In addition because need to provide high pressure and synchronous driving signal to increase so again the design difficulty of testing circuit driver module; Micro mechanical sensor be also because will design the micromechanics self-test electric capacity of one group of comb teeth-shaped more, and improved the problem of the design complexities of micro mechanical sensor.
For addressing the above problem, the utility model provides a kind of MEMS, and described MEMS comprises: micro mechanical sensor and the testing circuit being connected with described micro mechanical sensor; Wherein,
Described micro mechanical sensor comprises micromechanics sensing capacitance;
Described testing circuit comprises: self-test capacitor array and the signal-obtaining and the processing module that are connected with described self-test capacitor array; Wherein,
The electric charge that described self-test capacitor array changed in order to the output cycle;
Described signal-obtaining comprises with processing module: the charge amplifier, demodulator and the low pass filter that are connected in turn; Described signal-obtaining and processing module are exported a voltage signal in order to the electric charge changing according to the cycle of described self-test capacitor array output, and described voltage signal is in order to judge that whether described testing circuit normally works, and completes self-test function.
Optionally, in described MEMS, described self-test capacitor array comprises that magnitude circuit and the cycle being connected with described magnitude circuit realize circuit; Wherein,
Described magnitude circuit only has the half period of positive half period conversion to change electric charge in order to produce;
The described cycle realizes circuit and becomes the cycle that positive and negative half period has to change electric charge in order to changed to charge conversion the half period of only having positive half period conversion.
Optionally, in described MEMS, described magnitude circuit comprises the first circuit group, described the first circuit group comprises many groups capacitance group in parallel, every group of capacitance group comprises an electric capacity, first switch being connected with described electric capacity, a second switch being connected with described electric capacity and the common mode electrical level Vcm being connected with described second switch, wherein, the start signal of described the first switch is contrary with the start signal of described second switch.
Optionally, in described MEMS, multiple capacitances of organizing in capacitance group in parallel are sine wave more or triangular wave changes, not selected in the same time, only have the half-sine wave cycle of positive half period conversion to change electric charge or half triangular wave cycle variation electric charge thereby produce by the electric capacity in different capacitance group.
Optionally, in described MEMS, described magnitude circuit also comprises n+1 the first regulating circuit, n the second regulating circuit and one the 3rd regulating circuit of connecting with described the first circuit group, wherein, described n is natural number, described the first regulating circuit comprises that an electric capacity and one in parallel is subject to the switch of reset signal control, and the common mode electrical level Vcm being connected with described electric capacity and switch; Described the second regulating circuit comprises an electric capacity; Described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch.
Optionally, in described MEMS, described magnitude circuit also comprises one the 3rd regulating circuit and one the 4th regulating circuit of connecting with described the first circuit group, wherein, described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch; Described the 4th regulating circuit comprises a common mode electrical level Vcm who is subject to the switch of reset signal control and is connected with described switch.
Optionally, in described MEMS, the described cycle realizes circuit and comprises the first branch road and the second branch road with described the first branch circuit parallel connection, wherein,
The datum Vcom that described the first branch road comprises one the 5th switch and is connected with described the 5th switch;
The ground level GND that described the second branch road comprises one the 6th switch and is connected with described the 6th switch; The start signal of described the 6th switch is contrary with the start signal of described the 5th switch.
Optionally, in described MEMS, the formation circuit of the start signal of described the 5th switch comprises: the first parallel circuit, described the first parallel circuit comprises that the first generation circuit and second in parallel produces circuit, described first produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch be connected with a read signal PH_RS; Described second produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling and the inversion signal of a read signal connect;
The formation circuit of the start signal of described the 6th switch comprises: the second parallel circuit, described the second parallel circuit comprises that the 3rd generation circuit and the 4th in parallel produces circuit, described the 3rd produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch and the inversion signal of a read signal connect; The described the 4th produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling is connected with a read signal PH_RS.
Optionally, in described MEMS, the formation circuit of the start signal of described the 5th switch also comprises the buffer being connected with described the first parallel circuit; The formation circuit of the start signal of described the 6th switch also comprises the buffer being connected with described the second parallel circuit.
Optionally, in described MEMS,
Be between high period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b holds ground connection, a end is virtual earth end, and the electric charge of two ends ba is 0, when charge amplifier is during in reading state, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, thus the charge Q between b and a two ends bacompare previous reset mode increase Vcom*Cba;
Be between low period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, when charge amplifier is during in reading state, b termination GND, a end is virtual earth end, and the electric charge of two ends ba is 0, thus the charge Q between b and a two ends bacompare previous reset Reset state increase-Vcom*Cba;
Wherein, Cba is the capacitance of two ends ba.
Optionally, in described MEMS, the quantity of described self-test capacitor array is two, and two self-test capacitor arrays form differential configuration.
Optionally, in described MEMS, described charge amplifier, demodulator and low pass filter are differential configuration.
The utility model also provides a kind of testing circuit, and described testing circuit comprises: self-test capacitor array and the signal-obtaining and the processing module that are connected with described self-test capacitor array; Wherein,
The electric charge that described self-test capacitor array changed in order to the output cycle;
Described signal-obtaining comprises with processing module: the charge amplifier, demodulator and the low pass filter that are connected in turn; Described signal-obtaining and processing module are exported a voltage signal in order to the electric charge changing according to the cycle of described self-test capacitor array output, and described voltage signal is in order to judge that whether described testing circuit normally works, and completes self-test function.
Optionally, in described testing circuit, described self-test capacitor array comprises that magnitude circuit and the cycle being connected with described magnitude circuit realize circuit; Wherein,
Described magnitude circuit only has the half period of positive half period conversion to change electric charge in order to produce;
The described cycle realizes circuit and becomes the cycle that positive and negative half period has to change electric charge in order to changed to charge conversion the half period of only having positive half period conversion.
Optionally, in described testing circuit, described magnitude circuit comprises the first circuit group, described the first circuit group comprises many groups capacitance group in parallel, every group of capacitance group comprises an electric capacity, first switch being connected with described electric capacity, a second switch being connected with described electric capacity and the common mode electrical level Vcm being connected with described second switch, wherein, the start signal of described the first switch is contrary with the start signal of described second switch.
Optionally, in described testing circuit, multiple capacitances of organizing in capacitance group in parallel are sine wave more or triangular wave changes, not selected in the same time, only have the half-sine wave cycle of positive half period conversion to change electric charge or half triangular wave cycle variation electric charge thereby produce by the electric capacity in different capacitance group.
Optionally, in described testing circuit, described magnitude circuit also comprises n+1 the first regulating circuit, n the second regulating circuit and one the 3rd regulating circuit of connecting with described the first circuit group, wherein, described n is natural number, described the first regulating circuit comprises that an electric capacity and one in parallel is subject to the switch of reset signal control, and the common mode electrical level Vcm being connected with described electric capacity and switch; Described the second regulating circuit comprises an electric capacity; Described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch.
Optionally, in described testing circuit, described magnitude circuit also comprises one the 3rd regulating circuit and one the 4th regulating circuit of connecting with described the first circuit group, wherein, described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch; Described the 4th regulating circuit comprises a common mode electrical level Vcm who is subject to the switch of reset signal control and is connected with described switch.
Optionally, in described testing circuit, the described cycle realizes circuit and comprises the first branch road and the second branch road with described the first branch circuit parallel connection, wherein,
The datum Vcom that described the first branch road comprises one the 5th switch and is connected with described the 5th switch;
The ground level GND that described the second branch road comprises one the 6th switch and is connected with described the 6th switch; The start signal of described the 6th switch is contrary with the start signal of described the 5th switch.
Optionally, in described testing circuit, the formation circuit of the start signal of described the 5th switch comprises: the first parallel circuit, described the first parallel circuit comprises that the first generation circuit and second in parallel produces circuit, described first produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch be connected with a read signal PH_RS; Described second produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling and the inversion signal of a read signal connect;
The formation circuit of the start signal of described the 6th switch comprises: the second parallel circuit, described the second parallel circuit comprises that the 3rd generation circuit and the 4th in parallel produces circuit, described the 3rd produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch and the inversion signal of a read signal connect; The described the 4th produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling is connected with a read signal PH_RS.
Optionally, in described testing circuit, the formation circuit of the start signal of described the 5th switch also comprises the buffer being connected with described the first parallel circuit; The formation circuit of the start signal of described the 6th switch also comprises the buffer being connected with described the second parallel circuit.
Optionally, in described testing circuit,
Be between high period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b holds ground connection, a end is virtual earth end, and the electric charge of two ends ba is 0, when charge amplifier is during in reading state, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, thus the charge Q between b and a two ends bacompare previous reset mode increase Vcom*Cba;
Be between low period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, when charge amplifier is during in reading state, b termination GND, a end is virtual earth end, and the electric charge of two ends ba is 0, thus the charge Q between b and a two ends bacompare previous reset Reset state increase-Vcom*Cba;
Wherein, Cba is the capacitance of two ends ba.
Optionally, in described testing circuit, the quantity of described self-test capacitor array is two, and two self-test capacitor arrays form differential configuration.
Optionally, in described testing circuit, described charge amplifier, demodulator and low pass filter are differential configuration.
In the MEMS and testing circuit providing at the utility model, by the electric charge of the self-test capacitor array output cycle variation in testing circuit, thus in the time carrying out the self-test of testing circuit, the electric charge changing by the cycle of described self-test capacitor array output can carry out, thereby avoid needing testing circuit driver module generation high-voltage driven signal to make the cycle charge signal of the micromechanics self-test electric capacity output self-test needs in micro mechanical sensor, the self-test process of testing circuit no longer needs micro mechanical sensor to participate in thus, simplify the self-test flow process of testing circuit, and improve self-test reliability, meanwhile, in micro mechanical sensor, also no longer need micromechanics self-test electric capacity, thereby reduced the design difficulty of micro mechanical sensor design complexities and testing circuit driver module.
Brief description of the drawings
Fig. 1 is the structural representation of existing MEMS;
Fig. 2 is the brief principle figure that the micromechanics of existing micro mechanical sensor is realized self-test;
Fig. 3 is the structural representation of the MEMS of the utility model embodiment;
Fig. 4 is the circuit diagram of a self-test capacitor array of the utility model embodiment;
Fig. 5 is the partial circuit figure of another self-test capacitor array of the utility model embodiment;
Fig. 6 is the partial circuit figure of another self-test capacitor array of the utility model embodiment;
Fig. 7 is the generation circuit diagram of realizing the start signal of the 5th switch in circuit and the start signal of the 6th switch the cycle of the utility model embodiment;
Fig. 8 is the sequential chart of the part signal in the self-test capacitor array of the utility model embodiment;
Fig. 9 is the sequential chart of the part signal in the testing circuit of the utility model embodiment;
Figure 10 is the circuit diagram of two self-test capacitor arrays of the formation differential configuration of the utility model embodiment;
Figure 11 is the sequential comparison diagram of the output signal of two self-test capacitor arrays of the formation differential configuration of the utility model embodiment;
Figure 12 is the schematic diagram of the part-structure in the testing circuit that comprises differential configuration of the utility model embodiment;
Figure 13 is the sequential chart in multiple cycles of part signal in the testing circuit that comprises differential configuration of the utility model embodiment.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the MEMS the utility model proposes and testing circuit are described in further detail.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of aid illustration the utility model embodiment lucidly.
Please refer to Fig. 3, it is the structural representation of the MEMS of the utility model embodiment.As shown in Figure 3, described MEMS comprises: micro mechanical sensor 40 and the testing circuit 30 being connected with described micro mechanical sensor 40; Wherein,
Described micro mechanical sensor 40 comprises micromechanics sensing capacitance 41; That is to say, in the present embodiment, described micro mechanical sensor 40 can no longer arrange micromechanics self-test electric capacity;
Described testing circuit 30 comprises: self-test capacitor array 31 and the signal-obtaining and the processing module 32 that are connected with described self-test capacitor array 31; Wherein,
The electric charge that described self-test capacitor array 31 changed in order to the output cycle;
Described signal-obtaining comprises with processing module 32: the charge amplifier 321, demodulator 322 and the low pass filter 323 that are connected in turn; The electric charge that described signal-obtaining and processing module 32 changed in order to the cycle of exporting according to described self-test capacitor array 31 is exported a voltage signal, and described voltage signal is in order to judge that whether described testing circuit normally works, and completes self-test function.
Wherein, described cycle variation electric charge comprises that sine wave period changes electric charge or the triangular wave cycle changes electric charge.In the embodiment of the present application, change electric charge as example taking sine wave period.The triangular wave cycle changes electric charge by capacitance is made a change and can be realized, and the embodiment of the present application repeats no more this.
In the MEMS providing at the utility model, by the electric charge of the self-test capacitor array 31 output cycles variation in testing circuit 30, thus in the time carrying out the self-test of testing circuit 30, the electric charge that the cycle of exporting by described self-test capacitor array 31 changes can carry out, thereby avoid needing testing circuit 30 driver modules generation high-voltage driven signals to make the cycle charge signal of the micromechanics self-test electric capacity output self-test needs in micro mechanical sensor, the self-test process of testing circuit 30 no longer needs micro mechanical sensor 40 to participate in thus, simplify the self-test flow process of testing circuit 30, and improve self-test reliability, meanwhile, in micro mechanical sensor 40, also no longer need micromechanics self-test electric capacity, thereby reduced the design difficulty of micro mechanical sensor 40 design complexities and testing circuit 30 driver modules.
In the present embodiment, described self-test capacitor array 31 can be realized by the electric capacity in integrated circuit basic technology, that is to say, in prior art, need to form micromechanics self-test electric capacity by micromechanical process, required electric capacity when the MEMS providing by the present embodiment has been simplified self-test.
In the MEMS providing at the present embodiment, the variation of micro mechanical sensor 40 is mainly micromechanics self-test electric capacity can be no longer set, thereby has simplified the structure of micro mechanical sensor 40; And the structure of testing circuit 30 will occur to change greatly, therefore, in the subsequent description of the present embodiment, will introduce testing circuit 30.
In the present embodiment, described testing circuit 30 also comprises some other module, specifically comprise driver module 33, timing sequence generating circuit 34 and BIAS(biasing circuit) 35 and digital signal processing module 36, described driver module 33, timing sequence generating circuit 34, BIAS 35 and digital signal processing module 36 have all utilized structure of the prior art, and its role in described testing circuit 30 is also basic identical.For example, described timing sequence generating circuit 34 will produce Signed Domination signal PH_Vsin and read signal PH_RS, reset signal Reset etc., but it is also by producing the required number control signal of self-test capacitor array 31 in the present embodiment, is specially control signal B 0～B n-1deng; Described BIAS(biasing circuit) 35 main datum Vcom and the common mode electrical level Vcm of producing; Described digital signal processing module 36 will produce control signal D 0～D k-1deng.
In the present embodiment, the electric charge that the cycle that described charge amplifier 321 is exported described self-test capacitor array 31 changes reads, the read signal PH_RS that the controlled process reading produces in described timing sequence generating circuit 34, in the time that read signal PH_RS is low level, described charge amplifier 321 is in reset Reset state; In the time that read signal PH_RS is high level, described charge amplifier 321 is in reading state.
Please refer to Fig. 4, it is the circuit diagram of a self-test capacitor array of the utility model embodiment.Concrete, described self-test capacitor array 31 can be achieved by a circuit as shown in Figure 4.In the present embodiment, described self-test capacitor array 31 comprises magnitude circuit 311a, cycle of being connected with described magnitude circuit 311a realizes circuit 312; Wherein, described magnitude circuit 311a only has the half period of positive half period conversion to change electric charge in order to produce; The described cycle realizes half period of only having positive half period that circuit 312 is used for described magnitude circuit 311a to produce and changes charge conversion and become the electric charge that cycle that positive and negative half period has changes.
Wherein, described magnitude circuit can be achieved by multiple circuit, schematically shows three magnitude circuit in the present embodiment.
First, please continue to refer to Fig. 4, concrete, described magnitude circuit 311a the first circuit group, described the first circuit group comprises many groups capacitance group in parallel, every group of capacitance group comprises an electric capacity, first switch being connected with described electric capacity, a second switch being connected with described electric capacity and the common mode electrical level Vcm being connected with described second switch, and wherein, the start signal of described the first switch is contrary with the start signal of described second switch.For example, the first row capacitance group comprises capacitor C t0(clear and convenient for what represent, symbol C t0also represent the capacitance of corresponding capacitance, lower with), with described capacitor C t0the the first switch B being connected 0(clear and convenient for what represent, symbol B 0also represent to control the control signal of respective switch, lower with), with described capacitor C t0connected second switch and with described second switch connected common mode electrical level Vcm, wherein, described the first switch B 0start signal B 0with described second switch start signal on the contrary.At this, described capacitor C t0pass through second switch vcm is connected with common mode electrical level, and its object is, when described capacitor C t0when not selected, make this electric capacity can be not unsettled, thereby keep it stable.In the circuit design of self-test capacitor array, by capacitor C t0～C t(n-1)capacitance C t0～C t(n-1)variation according to periodic function designs, and for example in Fig. 8 shown in Ct0～Ct (n-1), Ct0～Ct (n-1) designs by sinusoidal cycles function.
In order to express easily, in this application, the expression of its corresponding capacitance of expression of electric capacity is identical, and the expression of its corresponding control signal of expression of switch is identical.
Please refer to Fig. 8, it is the sequential chart of the part signal in the self-test capacitor array of the utility model embodiment.As shown in Figure 8, by switch B 0～B n-1different unlatching sequential (wherein, B 0～B n-1high level represents corresponding switch closure, and the electric capacity in same capacitance group is selected), capacitor C t0～C t(n-1)not selected in the same time, because capacitor C t0～C t(n-1)capacitance C t0～C t(n-1)change to design by periodic function, thereby (always) electric capacity at matching self-test capacitor array 311 two ends forms the electric capacity of cycle variation, but only had positive half period, as C in Fig. 8 t0～C t(n-1)shown in waveform.
Please continue to refer to Fig. 4, in the present embodiment, described magnitude circuit 311a also comprises two the first regulating circuits, one second regulating circuit and one the 3rd regulating circuit that are connected with described the first circuit group, wherein, described the first regulating circuit comprises that an electric capacity in parallel (in two the first regulating circuits, is respectively C 1, C 3) and one to be subject to reset signal Reset(be the status signal of charge amplifier 321) switch controlled, and the common mode electrical level Vcm being connected with described electric capacity and switch; Described the second regulating circuit comprises a capacitor C 2; Described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch, and the capacitance of organizing electric capacity in capacitance group in parallel is binary system and changes more.For example, in described the 3rd regulating circuit, the first row capacitance group comprises capacitor C 0, with described capacitor C 0the 3rd switch D being connected 0, with described capacitor C 0the 4th switch being connected and with described the 4th switch connected datum V ref, wherein, described the 3rd switch D 0start signal D 0with described four switches start signal on the contrary.Same, said capacitor C 0by the 3rd switch with datum V refbe connected, its object is, when described capacitor C 0when not selected, make this electric capacity be unlikely to unsettled, thereby keep it stable.At this, capacitor C 0～2 k-1c 0be binary system and change, the capacitance of the electric capacity in two row of front and back differs 2 index times, and binary design can more convenient control and regulation amplitude size.
At this, suppose that the equivalent capacity size Csin that magnitude circuit 311a exports represents, the capacitance size (being the capacitance size that self-test capacitor array 31 is exported) between b end and a end can be expressed as follows:
C ba ≈ D 0 C 0 + D 1 2 C 0 + D 2 2 2 C 0 + · · · + D p 2 p C 0 + · · · + D k - 1 2 k - 1 C 0 ( C 0 + 2 C 0 + 2 2 C 0 + · · · + 2 p C 0 + · · · + 2 k - 1 C 0 ) + C 3 · C 2 C 1 + C 2 · C sin
The cycle amplitude size COEFFICIENT K sin that supposes again Csin, Ksin can be expressed as follows:
K sin ≈ D 0 C 0 + D 1 2 C 0 + D 2 2 2 C 0 + · · · + D p 2 p C 0 + · · · + D k - 1 2 k - 1 C 0 ( C 0 + 2 C 0 + 2 2 C 0 + · · · + 2 p C 0 + · · · + 2 k - 1 C 0 ) + C 3 · C 2 C 1 + C 2
C baelectric capacity can reduced representation as follows:
C ba＝K sin·C sin
A magnitude circuit has been shown in Fig. 4, then, has please refer to Fig. 5, Fig. 5 shows another magnitude circuit.As shown in Figure 5, n+1 the first regulating circuit, n the second regulating circuit and one the 3rd regulating circuit that magnitude circuit 311b comprises the first circuit group and connects with described the first circuit group, wherein, described n is natural number, described the first regulating circuit comprises that an electric capacity and one in parallel is subject to the switch of reset signal control, and the common mode electrical level Vcm being connected with described electric capacity and switch; Described the second regulating circuit comprises an electric capacity; Described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch.
At this, the magnitude circuit 311a of Fig. 4 shown in also can think a kind of special circumstances of the magnitude circuit 311b shown in Fig. 5, the situation that n equals 1.
Please refer to Fig. 6, it shows the 3rd magnitude circuit 311c, one the 3rd regulating circuit and one the 4th regulating circuit that described magnitude circuit 311c comprises the first circuit group and connects with described the first circuit group, wherein, described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch; Described the 4th regulating circuit comprises a common mode electrical level Vcm who is resetted the switch of Reset signal controlling and be connected with described switch.Wherein, the 3rd regulating circuit is identical with the 3rd regulating circuit shown in Fig. 4, and the embodiment of the present application repeats no more this.
Please continue to refer to Fig. 4, the described cycle realizes circuit 312 and comprises the first branch road and the second branch road with described the first branch circuit parallel connection, wherein, and the datum Vcom that described the first branch road comprises the 5th switch P H_Vcm and is connected with described the 5th switch P H_Vcm; The ground level GND that described the second branch road comprises the 6th switch P H_Gnd and is connected with described the 6th switch P H_Gnd; The start signal PH_Gnd of described the 6th switch P H_Gnd is contrary with the start signal PH_Vcm of described the 5th switch P H_Vcm.
Further, the present embodiment also shows the cycle and realizes the generation circuit of the start signal PH_Vcm of the 5th switch P H_Vcm in circuit 312 and the start signal PH_Gnd of the 6th switch P H_Gnd.Concrete, please refer to Fig. 7, its cycle for the utility model embodiment is realized the generation circuit diagram of the start signal of the 5th switch in circuit and the start signal of the 6th switch.
As shown in Figure 7, the formation circuit that the described cycle is realized the start signal PH_Vcm of the 5th switch in circuit 312 comprises: the first parallel circuit, described the first parallel circuit comprises that the first generation circuit and second in parallel produces circuit, described first produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch be connected with a read signal PH_RS; Described second produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling and the inversion signal of a read signal connect;
The formation circuit that the described cycle is realized the start signal PH_Gnd of the 6th switch in circuit 312 comprises: the second parallel circuit, described the second parallel circuit comprises that the 3rd generation circuit and the 4th in parallel produces circuit, described the 3rd produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch and the inversion signal of a read signal connect; The described the 4th produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling is connected with a read signal PH_RS.
Further, the formation circuit of realizing the start signal of the 5th switch in circuit 312 also comprises the buffer being connected with described the first parallel circuit the described cycle; The formation circuit that the described cycle is realized the start signal of the 6th switch in circuit 312 also comprises the buffer being connected with described the second parallel circuit.Driving force and the speed of the start signal PH_Vcm of the 5th switch that can further increase by described buffer and the start signal PH_Gnd of the 6th switch.
Please refer to Fig. 3 and Fig. 4, the described cycle realizes circuit 312 and specifically realizes in the following way the electric charge that the output cycle changes: a end in Fig. 4 is connected with the input of the operational amplifier in charge amplifier 321, is equivalent to virtual earth end.Known according to Fig. 7 and Fig. 9, in the time that Signed Domination signal PH_Vsin level reverses, the sequential low and high level of the start signal PH_Gnd of the start signal PH_Vcm of the 5th switch and the 6th switch reverses.Be between high period at Signed Domination signal PH_Vsin, when charge amplifier 321 in reset Reset state time while being low level (be read signal PH_RS), b end ground connection (i.e. the 6th switch closure, b end is connected with ground end GND), a end is virtual earth end, so the electric charge of two ends ba is 0, when charge amplifier 321 in reading state time while being high level (be read signal PH_RS), b termination Vcom(i.e. the 5th switch closure), a end is virtual earth end, so the electric charge of two ends ba is Vcom*Cba, between b and a two ends charge Q bacompare previous reset Reset state increase Vcom*Cba; Be in like manner between low period at Signed Domination signal PH_Vsin, when charge amplifier 321 in reset Reset state time while being low level (be read signal PH_RS), b termination Vcom, a end is virtual earth end, so the electric charge of two ends ba is Vcom*Cba, when charge amplifier 321 in reading state time while being high level (be read signal PH_RS), b termination GND, a end is virtual earth end, and the electric charge of two ends ba is 0, i.e. charge Q between b and a two ends bacompare previous reset Reset state increase-Vcom*Cba.At charge amplifier 321, in reading state while being high level (be read signal PH_RS), self-test capacitor array 31 enhanced charges can be expressed as follows:
That is:
It is the electric charge changing in the 31 output cycles of self-test capacitor array.Then the electric charge of this cycle variation will be transferred to feedback capacity Cfb above by charge amplifier 321, the final voltage signal V that the output cycle changes on charge amplifier 321 cA_OUT.The voltage signal V that wherein on charge amplifier 321, the cycle of output changes cA_OUTsequential chart can be with reference to figure 9; And Fig. 9 also shows the voltage signal V of the cycle variation of output on charge amplifier 321 cA_OUTduring through demodulator 322, the another one input signal V of demodulator 322 demotiming waveform.
Further, the quantity of described self-test capacitor array 31 can be two, and two self-test capacitor arrays 31 form differential configuration.Now, described charge amplifier 321, demodulator 322 and low pass filter 323 are differential configuration, and the capacitance sensor testing circuit that formed thus can have better anti-interference.Wherein, two self-test capacitor arrays of formation differential configuration please refer to Figure 10.As shown in figure 10, the difference of two self-test capacitor arrays that forms differential configuration is, with respect to self-test capacitor array 1, the start signal PH_Vcm of the 5th switch in self-test capacitor array 2 and the start signal PH_Gnd of the 6th switch exchange.Further, the output signal of two self-test capacitor arrays of formation differential configuration please refer to Figure 11.As shown in figure 11, form output signal (being the electric charge changing in the cycle) equal and opposite in direction, the single spin-echo of two self-test capacitor arrays of differential configuration.
Concrete, please refer to Figure 12, it is the schematic diagram of the part-structure in the testing circuit that comprises differential configuration of the utility model embodiment.As shown in figure 12, the electric charge that the common cycle that produces difference of self-test capacitor array 1 and self-test capacitor array 2 changes, the electric charge that the cycle of difference changes is transformed into the periodic voltage signal V of difference by charge amplifier cA_OUT, the output V of charge amplifier cA_OUTpass through again demodulator, the periodic voltage signal V of difference in demodulator cA_OUTanother input signal V with demodulator demo(input signal V demothe periodic voltage signal V with difference cA_OUTthe periodic signal of homophase) multiply each other, demodulate the output signal V of charge amplifier cA_OUTthe amplitude of cycle envelope signal, demodulation signal V out demo_OUToften, with high frequency clutter, therefore also pass through low pass filter filtering high frequency clutter at this, finally export V lPF_OUT.
Wherein, the output signal V of charge amplifier cA_OUTcan be expressed as:
Wherein C cArepresent the feedback capacity size of charge amplifier 321, i.e. C cA=C fb;
In the present embodiment, the gain of demodulator and low pass filter is all set to 1, thus, and the output signal V of low pass filter lPF_OUTthe amplitude that is periodic signal charge amplifier output and process LPF, the amplitude of cycle capacitor C sin is C t(n-1), the output signal V of low pass filter thus lPF_OUTthe signal magnitude obtaining can be expressed as:
V LPF _ OUT = K sin · V com · C t ( n - 1 ) C fb
Further, please refer to Figure 13, the sequential chart in multiple cycles of part signal in its testing circuit that comprises differential configuration that is the utility model embodiment.Wherein, C barepresent the capacitance variations (self-test capacitor array 1 and self-test capacitor array 2 convert the capacitance variations of only having positive half cycle to change to the charge variation of positive-negative half-cycle) of self-test capacitor array (differential configuration).Concrete, the electric charge that the cycle changes is through dielectric amplifier output voltage signal V cA_OUT, V cA_OUTenvelope be periodic signal, there is reset timing envelope inside; V in demodulator cA_OUTand V demomultiply each other and demodulate V cA_OUTthe amplitude V of cycle envelope signal demo_OUT, V demo_OUTthere is high frequency burr; Then, then by low pass filter filtering V demo_OUThigh frequency burr, output V lPF_OUT, V lPF_OUTit is a level and smooth level signal.
In the time carrying out self-test, the electric charge that the self-test capacitor array output cycle changes; Signal-obtaining and processing module are received from the electric charge of the cycle variation of testing capacitor array output, and export accordingly a voltage signal, and whether described voltage signal is working properly in order to judge described capacitance sensor testing circuit, completes self-test function.If described voltage signal values equals above V in expression formula lPF_OUTvalue, represent that testing circuit is working properly; If described voltage signal values departs from above V in expression formula lPF_OUTvalue, represent that testing circuit work is undesired.Thereby avoid needing testing circuit driver module generation high-voltage driven signal to make the cycle charge signal of the micromechanics self-test electric capacity output self-test needs in micro mechanical sensor, the self-test process of testing circuit no longer needs micro mechanical sensor to participate in thus, simplify the self-test flow process of testing circuit, and improved self-test reliability, reduce the design difficulty of micro mechanical sensor design complexities and testing circuit driver module.
Further, the electric charge of self-test capacitor array output cycle variation comprises: magnitude circuit produces only has the half period of positive half period conversion to change electric charge; Cycle realizes circuit and receives the half period of only having positive half period conversion that magnitude circuit produces and change electric charge, and the electric charge that changes of the cycle that obtains accordingly positive and negative half period and have.
When the quantity of described self-test capacitor array is two, and when two self-test capacitor arrays form differential configuration, the electric charge that the self-test capacitor array output cycle changes comprises: the self-test capacitor array of two formation differential configurations is the electric charge of output cycle variation all, and the electric charge that the cycle of exporting changes forms differential signal.
As fully visible, in the MEMS and testing circuit providing at the utility model embodiment, by the electric charge of the self-test capacitor array output cycle variation in testing circuit, thus in the time carrying out the self-test of testing circuit, the electric charge changing by the cycle of described self-test capacitor array output can carry out, thereby avoid needing testing circuit driver module generation high-voltage driven signal to make the cycle charge signal of the micromechanics self-test electric capacity output self-test needs in micro mechanical sensor, the self-test process of testing circuit no longer needs micro mechanical sensor to participate in thus, simplify the self-test flow process of testing circuit, and improve self-test reliability, meanwhile, in micro mechanical sensor, also no longer need micromechanics self-test electric capacity, thereby reduced the design difficulty of micro mechanical sensor design complexities and testing circuit driver module.
Foregoing description is only the description to the utility model preferred embodiment; the not any restriction to the utility model scope; any change, modification that the those of ordinary skill in the utility model field does according to above-mentioned disclosure, all belong to the protection domain of claims.

Claims (24)

1. a MEMS, is characterized in that, comprising: micro mechanical sensor and the testing circuit being connected with described micro mechanical sensor; Wherein,
Described micro mechanical sensor comprises micromechanics sensing capacitance;
Described testing circuit comprises: the electric charge that the self-test capacitor array of the electric charge that the output cycle changes and the cycle according to described self-test capacitor array output being connected with described self-test capacitor array change is exported a voltage signal, described voltage signal, in order to judge whether described testing circuit normally works, completes signal-obtaining and the processing module of self-test function; Wherein,
Described signal-obtaining comprises with processing module: the charge amplifier, demodulator and the low pass filter that are connected in turn.
2. MEMS as claimed in claim 1, it is characterized in that, described self-test capacitor array comprises that producing the magnitude circuit of only having half period of positive half period conversion to change electric charge and the half period by only having positive half period conversion being connected with described magnitude circuit changes charge conversion and become the cycle of the cycle variation electric charge that positive and negative half period has to realize circuit.
3. MEMS as claimed in claim 2, it is characterized in that, described magnitude circuit comprises the first circuit group, described the first circuit group comprises many groups capacitance group in parallel, every group of capacitance group comprises an electric capacity, first switch being connected with described electric capacity, a second switch being connected with described electric capacity and the common mode electrical level Vcm being connected with described second switch, wherein, the start signal of described the first switch is contrary with the start signal of described second switch.
4. MEMS as claimed in claim 3, it is characterized in that, multiple capacitances of organizing in capacitance group in parallel are sine wave more or triangular wave changes, electric capacity in different capacitance group, not selected in the same time, produce and only has the half-sine wave cycle of positive half period conversion to change electric charge or half triangular wave cycle variation electric charge.
5. MEMS as claimed in claim 3, it is characterized in that, described magnitude circuit also comprises n+1 the first regulating circuit, n the second regulating circuit and one the 3rd regulating circuit of connecting with described the first circuit group, wherein, described n is natural number, described the first regulating circuit comprises that an electric capacity and one in parallel is subject to the switch of reset signal control, and the common mode electrical level Vcm being connected with described electric capacity and switch; Described the second regulating circuit comprises an electric capacity; Described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch.
6. MEMS as claimed in claim 3, it is characterized in that, described magnitude circuit also comprises one the 3rd regulating circuit and one the 4th regulating circuit of connecting with described the first circuit group, wherein, described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch; Described the 4th regulating circuit comprises a common mode electrical level Vcm who is subject to the switch of reset signal control and is connected with described switch.
7. MEMS as claimed in claim 3, is characterized in that, the described cycle realizes circuit and comprises the first branch road and the second branch road with described the first branch circuit parallel connection, wherein,
The datum Vcom that described the first branch road comprises one the 5th switch and is connected with described the 5th switch;
The ground level GND that described the second branch road comprises one the 6th switch and is connected with described the 6th switch; The start signal of described the 6th switch is contrary with the start signal of described the 5th switch.
8. MEMS as claimed in claim 7, is characterized in that,
The formation circuit of the start signal of described the 5th switch comprises: the first parallel circuit, described the first parallel circuit comprises that the first generation circuit and second in parallel produces circuit, described first produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch be connected with a read signal PH_RS; Described second produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling and the inversion signal of a read signal connect;
The formation circuit of the start signal of described the 6th switch comprises: the second parallel circuit, described the second parallel circuit comprises that the 3rd generation circuit and the 4th in parallel produces circuit, described the 3rd produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch and the inversion signal of a read signal connect; The described the 4th produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling is connected with a read signal PH_RS.
9. MEMS as claimed in claim 8, is characterized in that, the formation circuit of the start signal of described the 5th switch also comprises the buffer being connected with described the first parallel circuit; The formation circuit of the start signal of described the 6th switch also comprises the buffer being connected with described the second parallel circuit.
10. MEMS as claimed in claim 9, is characterized in that,
Be between high period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b holds ground connection, a end is virtual earth end, and the electric charge of two ends ba is 0, when charge amplifier is during in reading state, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, thus the charge Q between b and a two ends bacompare previous reset mode increase Vcom*Cba;
Be between low period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, when charge amplifier is during in reading state, b termination GND, a end is virtual earth end, and the electric charge of two ends ba is 0, thus the charge Q between b and a two ends bacompare previous reset Reset state increase-Vcom*Cba;
Wherein, Cba is the capacitance of two ends ba.
11. MEMSs as described in any one in claim 1～10, is characterized in that, the quantity of described self-test capacitor array is two, and two self-test capacitor arrays form differential configurations.
12. MEMSs as claimed in claim 11, is characterized in that, described charge amplifier, demodulator and low pass filter are differential configuration.
13. 1 kinds of testing circuits, it is characterized in that, comprise: the electric charge that the self-test capacitor array of the electric charge that the output cycle changes and the cycle according to described self-test capacitor array output being connected with described self-test capacitor array change is exported a voltage signal, described voltage signal, in order to judge whether described testing circuit normally works, completes signal-obtaining and the processing module of self-test function; Wherein,
Described signal-obtaining comprises with processing module: the charge amplifier, demodulator and the low pass filter that are connected in turn.
14. testing circuits as claimed in claim 13, it is characterized in that, described self-test capacitor array comprises that producing the magnitude circuit of only having half period of positive half period conversion to change electric charge and the half period by only having positive half period conversion being connected with described magnitude circuit changes charge conversion and become the cycle of the cycle variation electric charge that positive and negative half period has to realize circuit.
15. testing circuits as claimed in claim 14, it is characterized in that, described magnitude circuit comprises the first circuit group, described the first circuit group comprises many groups capacitance group in parallel, every group of capacitance group comprises an electric capacity, first switch being connected with described electric capacity, a second switch being connected with described electric capacity and the common mode electrical level Vcm being connected with described second switch, wherein, the start signal of described the first switch is contrary with the start signal of described second switch.
16. testing circuits as claimed in claim 15, it is characterized in that, multiple capacitances of organizing in capacitance group in parallel are sine wave more or triangular wave changes, electric capacity in different capacitance group, not selected in the same time, produce and only has the half-sine wave cycle of positive half period conversion to change electric charge or half triangular wave cycle variation electric charge.
17. testing circuits as claimed in claim 15, it is characterized in that, described magnitude circuit also comprises n+1 the first regulating circuit, n the second regulating circuit and one the 3rd regulating circuit of connecting with described the first circuit group, wherein, described n is natural number, described the first regulating circuit comprises that an electric capacity and one in parallel is subject to the switch of reset signal control, and the common mode electrical level Vcm being connected with described electric capacity and switch; Described the second regulating circuit comprises an electric capacity; Described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch.
18. testing circuits as claimed in claim 15, it is characterized in that, described magnitude circuit also comprises one the 3rd regulating circuit and one the 4th regulating circuit of connecting with described the first circuit group, wherein, described the 3rd regulating circuit comprises many groups capacitance group in parallel, and every group of capacitance group comprises the 4th switch that the 3rd switch, that an electric capacity, one is connected with described electric capacity is connected with described electric capacity and the datum V being connected with described the 4th switch ref, wherein, the start signal of described the 3rd switch is contrary with the start signal of described the 4th switch; Described the 4th regulating circuit comprises a common mode electrical level Vcm who is subject to the switch of reset signal control and is connected with described switch.
19. testing circuits as claimed in claim 15, is characterized in that, the described cycle realizes circuit and comprises the first branch road and the second branch road with described the first branch circuit parallel connection, wherein,
The datum Vcom that described the first branch road comprises one the 5th switch and is connected with described the 5th switch;
The ground level GND that described the second branch road comprises one the 6th switch and is connected with described the 6th switch; The start signal of described the 6th switch is contrary with the start signal of described the 5th switch.
20. testing circuits as claimed in claim 19, is characterized in that,
The formation circuit of the start signal of described the 5th switch comprises: the first parallel circuit, described the first parallel circuit comprises that the first generation circuit and second in parallel produces circuit, described first produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch be connected with a read signal PH_RS; Described second produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling and the inversion signal of a read signal connect;
The formation circuit of the start signal of described the 6th switch comprises: the second parallel circuit, described the second parallel circuit comprises that the 3rd generation circuit and the 4th in parallel produces circuit, described the 3rd produce circuit comprises one be subject to Signed Domination signal PH_Vsin control switch, described in be subject to Signed Domination signal PH_Vsin control switch and the inversion signal of a read signal connect; The described the 4th produces circuit comprises that one is subject to the inversion signal of Signed Domination signal the switch of controlling, described in be subject to the inversion signal of Signed Domination signal the switch of controlling is connected with a read signal PH_RS.
21. testing circuits as claimed in claim 20, is characterized in that, the formation circuit of the start signal of described the 5th switch also comprises the buffer being connected with described the first parallel circuit; The formation circuit of the start signal of described the 6th switch also comprises the buffer being connected with described the second parallel circuit.
22. testing circuits as claimed in claim 21, is characterized in that,
Be between high period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b holds ground connection, a end is virtual earth end, and the electric charge of two ends ba is 0, when charge amplifier is during in reading state, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, thus the charge Q between b and a two ends bacompare previous reset mode increase Vcom*Cba;
Be between low period at Signed Domination signal PH_Vsin, when charge amplifier is during in reset mode, b termination Vcom, a end is virtual earth end, and the electric charge of two ends ba is Vcom*Cba, when charge amplifier is during in reading state, b termination GND, a end is virtual earth end, and the electric charge of two ends ba is 0, thus the charge Q between b and a two ends bacompare previous reset Reset state increase-Vcom*Cba;
Wherein, Cba is the capacitance of two ends ba.
23. testing circuits as described in any one in claim 13～22, is characterized in that, the quantity of described self-test capacitor array is two, and two self-test capacitor arrays form differential configurations.
24. testing circuits as claimed in claim 23, is characterized in that, described charge amplifier, demodulator and low pass filter are differential configuration.
CN201320892445.6U 2013-12-30 2013-12-30 Micro electro mechanical system and detection circuit Withdrawn - After Issue CN203890050U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103723673A (en) * 2013-12-30 2014-04-16 杭州士兰微电子股份有限公司 Micro electro mechanical system and detection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103723673A (en) * 2013-12-30 2014-04-16 杭州士兰微电子股份有限公司 Micro electro mechanical system and detection circuit
CN103723673B (en) * 2013-12-30 2015-12-16 杭州士兰微电子股份有限公司 MEMS and testing circuit

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