CN203871848U - Bus protective device based on voltage phase-locked networked sampling - Google Patents
Bus protective device based on voltage phase-locked networked sampling Download PDFInfo
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- CN203871848U CN203871848U CN201420287206.2U CN201420287206U CN203871848U CN 203871848 U CN203871848 U CN 203871848U CN 201420287206 U CN201420287206 U CN 201420287206U CN 203871848 U CN203871848 U CN 203871848U
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- Prior art keywords
- bus
- sampling
- phase
- locked
- protection
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S10/00—Systems supporting electrical power generation, transmission or distribution
- Y04S10/20—Systems supporting electrical power generation, transmission or distribution using protection elements, arrangements or systems
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- Emergency Protection Circuit Devices (AREA)
Abstract
The utility model discloses a bus protective device based on voltage phase-locked networked sampling. The bus protective device based on voltage phase-locked networked sampling comprises a PT merging unit, multiple spaced merging units, a switch and a bus protection module. The PT merging unit is connected with the spaced merging units. The PT merging unit and the spaced merging units are connected with the switch which is connected with the bus protection module. The bus protection module comprises an FPGA, a message resolver and a bus protector. The FPGA, the message resolver and the bus protector are connected in turn. The FPGA is used for receiving and transmitting process level network data. The message resolver is used for resolving a sampling message. The bus protector is used for transmitting a bus relay protection movement signal. Bus protection is performed on the basis of voltage phase-locked networked sampling. Sampling values are outputted by the switch so that sampling value message output is uniform. The number of the spaced merging units is arranged according to the requirements of the protected bus so that number arrangement is flexible and implement is flexible.
Description
Technical field
The utility model belongs to intelligent substation of electric power system and digital substation relay protection field, and what relate to is the protection equipment for busbar of a kind of transformer station sampled value Network Transmitting.
Background technology
Bus protection is one of main protection in electric power system.The safe and reliable operation of bus directly affects the reliability of power plant and transformer station's power supply.Along with digitized extensive application, traditional electric current, the bus protection of voltage analog access can not meet the Protection Technology requirement of intelligent substation.In order to solve the active demand of engineering application; both at home and abroad in succession develop the bus protection that some are applicable to sampled value Digital Transmission; in prior art scheme; general by receiving the tape deck data such as sampled value and failure wave-recording or network analyzer; after synchronous, realize bus protection; because the data that receive are not to be exported by same transmit port; form difference is unfavorable for power system fault analysis; bus protection receiver side port number is had to requirement; underaction when engineering construction, inapplicable multizone is suitable for.
For example, CN101854054A discloses a kind of digital transformer substation bus protection relay system, and this system comprises bus protection main website, bus protection substation, electronic mutual inductor and intelligent terminal; Bus protection main website judges whether generating region internal fault of bus according to the digital quantity of the digital quantity of the bus protection substation transmission receiving and intake or electronic mutual inductor output and GOOSE net intake; if generating region internal fault, directly by trip contact control related switch tripping operation of routine; also can be by sending control signal to described intelligent terminal, intelligent terminal is according to this control signal control related switch tripping operation.The problem that this utility model has solved conventional equipment interface and digitizer interface and deposited, the bus protection full having realized in digital improvement process drops into.But this application is still the digital quantity of the transmission between protection main website and protection substation and the digital quantity of switching value or electronic mutual inductor output, detection range is little, is unsuitable for promoting at multizone.
Utility model content
Utility model object: the bus protection of networking sampling does not rely on synchronizing signal and works; the actual use of quantity basis of interval merge cells arranges; arrange flexibly; simultaneously; based on the bus protection of the phase-locked networking of voltage sampling, can realize not relying on synchronised clock and just can play the good protective effect of electrical system bus, and the bus protection of other synchronous versions relatively; both reduce transformer substation construction cost, reduced again the overhead to protective device and switch resource.Its extensive use in intelligent substation, will produce very large Social benefit and economic benefit.
Technical solutions of the utility model are as follows:
Based on the protection equipment for busbar of the phase-locked networking sampling of voltage, comprise PT merge cells, some intervals merge cells, switch and bus protection module, PT merge cells is connected with interval merge cells, PT merge cells, interval merge cells are all connected with switch, and switch is connected with bus protection module; PT merge cells can provide homology voltage for interval merge cells, simultaneously also can sampling process layer network message.
Bus protection module comprises FPGA, packet parsing device and bus protection device, and FPGA, packet parsing device and bus protection device are linked in sequence successively; FPGA is used for receiving and dispatching process-level network data, and packet parsing device is for the parsing of the message of sampling, and bus protection device sends for bus relay protection actuating signal.
Packet parsing device comprises digital phase lock, sampling value message resolver, phase place correcting module and synchronization module; Digital phase lock, sampling value message resolver, phase place correcting module and synchronization module are linked in sequence successively.
Digital phase lock comprises phase discriminator, loop filter and voltage controlled oscillator, and phase discriminator, loop filter and voltage controlled oscillator successively order are connected, and the output of voltage controlled oscillator is connected with the input of phase discriminator.
The number of digital phase lock is identical with the number of interval merge cells, by digital phase lock, the arrival time delay markers of every frame message is carried out beat locking and eliminated shake, exported accurately the markers of sampling value message, for synchronization module synchronously provides accurate synchronizing information.
More preferably, loop filter is IIR type low pass filter.
More preferably, between FPGA and packet parsing device, be connected by dual port RAM or parallel Peripheral Interface.
More preferably, packet parsing device is connected by internal data bus with bus protection device.
More preferably, communicating by letter between bus protection device and protected bus device comprises the auxiliary communication of GOOSE service, station level MMS communication and MMI.
The technical solution of the utility model beneficial effect comprises: the utility model compared with prior art; beneficial effect is: the utility model carries out bus protection based on the phase-locked networking of voltage sampling; after adopting by each interval merge cells, send to switch; switch is exported to bus protection module; the output of sampled value is all to be exported by switch; sampling value message output is unified; the quantity of interval merge cells is according to the demand setting of protected bus; quantity arranges flexibly, and engineering construction is flexible.
Further; bus protection based on voltage lock networking sampling does not rely on synchronizing signal and works; energy realization does not rely on synchronised clock and just can play the good protective effect of electrical system bus; and the bus protection of other synchronous versions relatively; both reduce transformer substation construction cost, reduced again the overhead to protective device and switch resource.
Further, communicating by letter between bus protection device and bus device comprises the auxiliary communication of GOOSE service, station level MMS communication and MMI, and cost is low, applied widely.
Brief description of the drawings
Fig. 1 is the bus protection relay system schematic diagram of the utility model based on the phase-locked networking sampling of voltage;
Fig. 2 is the utility model bus protection modular structure schematic diagram;
Fig. 3 is the utility model packet parsing device structural representation;
Fig. 4 digital phase lock structural representation.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
Consult Fig. 1, based on the protection equipment for busbar of the phase-locked networking sampling of voltage, comprise PT merge cells, some intervals merge cells, switch and bus protection module, described PT merge cells is connected with interval merge cells, described PT merge cells, interval merge cells are all connected with switch, and described switch is connected with bus protection module; PT merge cells can provide homology voltage for interval merge cells, simultaneously also can sampling process layer network message.
As shown in Figure 2, described bus protection module comprises FPGA, packet parsing device and bus protection device, and described FPGA, packet parsing device and bus protection device are linked in sequence successively; Described FPGA is used for receiving and dispatching process-level network data, and described packet parsing device is for the parsing of the message of sampling, and described bus protection device sends for bus relay protection actuating signal.
As shown in Figure 3, packet parsing device comprises digital phase lock, sampling value message resolver, phase place correcting module and synchronization module; Described digital phase lock, sampling value message resolver, phase place correcting module and synchronization module are linked in sequence successively.
As shown in Figure 4, digital phase lock comprises phase discriminator, loop filter and voltage controlled oscillator, and described phase discriminator, loop filter and voltage controlled oscillator successively order are connected, and the output of described voltage controlled oscillator is connected with the input of phase discriminator.Input sample value message markers θ
1(t) be input in phase discriminator, start when initial θ at digital phase lock
2(t)=θ
1(t); Work as θ
1and θ (t)
2(t), when step-out, phase discriminator completes θ
1and θ (t)
2(t) time difference; Input variable V using time difference as loop filter
1(t), loop filter carries out low-pass filtering treatment, and output variable is V
2(t); V
2(t) as the input variable of voltage controlled oscillator, voltage controlled oscillator is pressed V
2(t) amplitude tracking regulates step-length, and completes θ within the time of 1 second
2(t) whole tracing process, has realized digital phase lock the arrival time delay markers of every frame message has been carried out to beat locking.What the transmission of the inside of phase discriminator, loop filter and voltage controlled oscillator to signal and processing procedure were all utilized is the function of assembly self, and processing procedure the application of component internal is not optimized.
Loop filter is IIR type low pass filter.
The number of digital phase lock is identical with the number of interval merge cells.
Between FPGA and packet parsing device, be connected by dual port RAM or parallel Peripheral Interface.
Packet parsing device is connected by internal data bus with bus protection device.
Communicating by letter between bus protection device and bus device comprises the auxiliary communication of GOOSE service, station level MMS communication and MMI.
Below be only preferred implementation of the present utility model; be noted that for those skilled in the art; not departing under the prerequisite of the utility model principle, can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (8)
1. the protection equipment for busbar based on the phase-locked networking sampling of voltage, it is characterized in that, comprise PT merge cells, some intervals merge cells, switch and bus protection module, described PT merge cells is connected with interval merge cells, described PT merge cells, interval merge cells are all connected with switch, and described switch is connected with bus protection module;
Described bus protection module comprises FPGA, packet parsing device and bus protection device, and described FPGA, packet parsing device and bus protection device are linked in sequence successively; Described FPGA is used for receiving and dispatching process-level network data, and described packet parsing device is for the parsing of the message of sampling, and described bus protection device sends for bus relay protection actuating signal.
2. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 1, is characterized in that, described packet parsing device comprises digital phase lock, sampling value message resolver, phase place correcting module and synchronization module; Described digital phase lock, sampling value message resolver, phase place correcting module and synchronization module are linked in sequence successively.
3. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 2; it is characterized in that; described digital phase lock comprises phase discriminator, loop filter and voltage controlled oscillator; described phase discriminator, loop filter and voltage controlled oscillator successively order are connected, and the output of described voltage controlled oscillator is connected with the input of phase discriminator.
4. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 3, is characterized in that, described loop filter is IIR type low pass filter.
5. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 2, is characterized in that, the number of described digital phase lock is identical with the number of interval merge cells.
6. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 1, is characterized in that, between described FPGA and packet parsing device, is connected by dual port RAM or parallel Peripheral Interface.
7. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 1, is characterized in that, described packet parsing device is connected by internal data bus with bus protection device.
8. the protection equipment for busbar based on the phase-locked networking sampling of voltage according to claim 1, is characterized in that, communicating by letter between described bus protection device and protected bus device comprises the auxiliary communication of GOOSE service, station level MMS communication and MMI.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420287206.2U CN203871848U (en) | 2014-05-30 | 2014-05-30 | Bus protective device based on voltage phase-locked networked sampling |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420287206.2U CN203871848U (en) | 2014-05-30 | 2014-05-30 | Bus protective device based on voltage phase-locked networked sampling |
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| Publication Number | Publication Date |
|---|---|
| CN203871848U true CN203871848U (en) | 2014-10-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420287206.2U Expired - Fee Related CN203871848U (en) | 2014-05-30 | 2014-05-30 | Bus protective device based on voltage phase-locked networked sampling |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253239A (en) * | 2016-08-15 | 2016-12-21 | 南京国电南自电网自动化有限公司 | Decentralized bus protection collocation method based on MapReduce framework |
-
2014
- 2014-05-30 CN CN201420287206.2U patent/CN203871848U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106253239A (en) * | 2016-08-15 | 2016-12-21 | 南京国电南自电网自动化有限公司 | Decentralized bus protection collocation method based on MapReduce framework |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141008 Termination date: 20170530 |