CN111506000B - Synchronous sampling device based on non-real-time bus - Google Patents

Synchronous sampling device based on non-real-time bus Download PDF

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CN111506000B
CN111506000B CN202010446211.3A CN202010446211A CN111506000B CN 111506000 B CN111506000 B CN 111506000B CN 202010446211 A CN202010446211 A CN 202010446211A CN 111506000 B CN111506000 B CN 111506000B
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sampling
fpga
real
time
sampling module
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CN111506000A (en
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霍银龙
吴凯
陈从靖
王宏
吴正伟
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Nanjing SAC Automation Co Ltd
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Nanjing SAC Automation Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0428—Safety, monitoring
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/26—Pc applications
    • G05B2219/2612—Data acquisition interface

Abstract

The invention discloses a synchronous sampling device based on a non-real-time bus, which comprises a mainframe box and an expansion case, wherein the mainframe box is connected with a CAN bus and comprises a first FPGA; the expansion cabinet comprises a second FPGA and a second sampling module; the first FPGA generates a first internal time reference and transmits the first internal time reference to the second FPGA; after receiving the first internal time reference, the second FPGA generates a second internal time reference synchronous with the first internal time reference; the second sampling module processes the obtained second internal time reference to obtain time information containing seconds and nanoseconds; the second sampling module generates sampling pulses, adds time information containing seconds and nanoseconds to each sampling value, sends the sampling values to the second FPGA, the second FPGA generates sampling pulses of alternating current analog quantity, and adds time information containing seconds and nanoseconds to each sampling value; and the second FPGA sends all the sampling values to the first FPGA. The invention does not depend on a real-time operating system and a real-time sampling mechanism, and can ensure the synchronization of alternating current sampling, switching value and DC direct current value.

Description

Synchronous sampling device based on non-real-time bus
Technical Field
The invention belongs to the technical field of communication of electric power digital substations, and particularly relates to a synchronous sampling device based on a non-real-time bus.
Background
The traditional fault recorder often uses a real-time bus and a real-time operating system, including a real-time bus such as SPI, I2C and the like to sample analog quantity and switching quantity. Because real-time sampling requires high CPU processing capacity, data sampling needs to be completed in real time. If the non-real-time bus is adopted, the load of the CPU can be effectively reduced, the universality of product design is improved, and the method has practical significance for subsequent replacement of the processor or use of a non-real-time operating system.
Disclosure of Invention
Aiming at the problems, the invention provides a synchronous sampling device based on a non-real-time bus, which does not depend on a real-time operating system and a real-time sampling mechanism, has strong universality and can ensure the synchronization of alternating current sampling, switching value and DC direct current value.
In order to achieve the technical purpose and achieve the technical effects, the invention is realized by the following technical scheme:
a non-real time bus based synchronous sampling apparatus, comprising:
the main case comprises a first FPGA;
at least one expansion cabinet, wherein the expansion cabinet comprises a second FPGA and a second sampling module which are connected;
the mainframe box and the expansion box are both connected with a CAN bus;
the first FPGA generates a first internal time reference and transmits the first internal time reference to a second FPGA; after receiving the first internal time reference, the second FPGA generates a second internal time reference synchronous with the first internal time reference;
the second sampling module processes the obtained second internal time reference to obtain time information containing seconds and nanoseconds;
the second sampling module generates sampling pulses, adds time information containing seconds and nanoseconds to each sampling value, then sends the sampling values to a corresponding second FPGA, and simultaneously the second FPGA generates sampling pulses of alternating current analog quantity and adds time information containing seconds and nanoseconds to each sampling value;
and the second FPGA sends all sampling values to the first FPGA to complete synchronous sampling.
Optionally, the main chassis further includes a first sampling module connected to the first FPGA, and the first sampling module processes the obtained first internal time reference to obtain time information including seconds and nanoseconds;
the first sampling module generates sampling pulses, time information containing seconds and nanoseconds is added to each sampling value, then the sampling values are sent to the corresponding first FPGA, meanwhile, the first FPGA generates sampling pulses of alternating current analog quantity, and time information containing seconds and nanoseconds is added to each sampling value.
Optionally, each second sampling module and each first sampling module are transmitted to the corresponding FPGA by using a packet splicing mechanism.
Optionally, the first internal time reference is transmitted in IRIG-B format; the first sampling module and the second sampling module comprise a first timer, a second timer and a third timer;
the first timer captures a first internal time reference;
when the second timer decodes the received first internal time reference in the IRIG-B format, the second timer is cleared at the time of the whole second and 10 groups of interval code elements of the IRIG-B to obtain time information containing seconds and nanoseconds;
and the third timer is used for generating switching value sampling pulses with sampling frequency of 10KHz and adding time information containing seconds and nanoseconds to each sampling value.
Optionally, the number of the first sampling module and the second sampling module is one or more, and when the number of the first sampling module and the second sampling module is more than one, the first sampling module and the second sampling module are open-in modules and/or direct current acquisition modules.
Optionally, when the second sampling module is an open-in module, after receiving the switching value message sent by the corresponding second sampling module, the second FPGA judges the switching value displacement and sends the switching value displacement to the first FPGA according to the format of the GOOSE message.
Optionally, the sending to the first FPGA according to the format of the GOOSE packet includes:
when the switching value has no displacement, the GOOSE message is sent according to a heartbeat message of 1 ms;
and after the switching value is shifted, sending a message to the first FPGA according to a GOOSE shift mechanism of 200us, 200us, 400us and 800 us.
Optionally, the synchronous sampling device based on the non-real-time bus further includes a processor, and after receiving the sampling message sent by the second FPGA, the first FPGA adds absolute time information synchronized with an external GPS device, and finally transmits the absolute time information to the processor through the PCI-E bus for fault recording and fault analysis.
Optionally, after receiving the message, the processor synchronizes data according to time information including seconds and nanoseconds.
Optionally, the first FPGA and the second FPGA respectively generate 10KHz sampling pulses through an internal digital phase-locked loop technology, and are used for collecting alternating current analog quantities.
Compared with the prior art, the invention has the beneficial effects that:
in the invention, because the alternating current analog quantity, the switching value and the DC direct current quantity are completed by different processors, and an error retransmission mechanism exists in the CAN-FD communication process, in order to ensure the synchronization of the alternating current sampling, the switching value and the DC direct current quantity, the invention adopts a synchronization mechanism of a non-real-time bus.
Drawings
In order that the present disclosure may be more readily and clearly understood, reference is now made to the following detailed description of the present disclosure taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a communication block diagram of a fault recorder according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an AC analog acquisition process according to an embodiment of the present invention
Fig. 3 is a schematic diagram of a switching value acquisition process according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the scope of the invention.
The following detailed description of the principles of the invention is provided in connection with the accompanying drawings.
Example 1
As shown in fig. 1 to 3, an embodiment of the present invention provides a synchronous sampling apparatus based on a non-real-time bus, including:
the main case comprises a first FPGA;
at least one expansion cabinet, wherein the expansion cabinet comprises a second FPGA and a second sampling module which are connected;
the mainframe box and the expansion box are both connected with a CAN bus, namely the CAN _ FD bus in fig. 1;
the first FPGA generates a first internal time reference and transmits the first internal time reference to a second FPGA; after receiving the first internal time reference, the second FPGA generates a second internal time reference synchronous with the first internal time reference; in the actual use process, the first FPGA is connected with the second FPGA through an IRIG-B time bus to transmit the first internal time reference; the first FPGA is also connected with external GPS equipment through an IRIG-B time bus to synchronize absolute time; the first FPGA is not only used for completing a time synchronization management function, but also used for recording various wave recording events;
the second sampling module processes the obtained second internal time reference to obtain time information containing seconds and nanoseconds;
the second sampling module generates sampling pulses, adds time information containing seconds and nanoseconds to each sampling value, then sends the sampling values to a corresponding second FPGA, and simultaneously the second FPGA generates sampling pulses of alternating current analog quantity and adds time information containing seconds and nanoseconds to each sampling value;
and the second FPGA sends all sampling values to the first FPGA to complete synchronous sampling.
In a specific implementation manner of the embodiment of the present invention, because the CAN-FD supports maximum 64-byte packet transmission, and multiple second sampling modules need bus contention, in order to improve communication efficiency of a bus, each second sampling module transmits to a corresponding FPGA by using a packet splicing mechanism, for example, each second sampling module may transmit to a corresponding second FPGA by using a packet splicing mechanism of 5 packets. The second sampling module may be a switch module and/or a dc module.
In a specific implementation of the embodiment of the present invention, the first internal time reference is transmitted in an IRIG-B format; the first sampling module and the second sampling module comprise a first timer, a second timer and a third timer;
the first timer captures a first internal time reference using its capture function;
when the second timer decodes the received first internal time reference in the IRIG-B format, the second timer is cleared at the time of the whole second and 10 groups of interval code elements of the IRIG-B to obtain time information containing seconds and nanoseconds; in specific implementation, 100 code elements in the format of the IRIG-B are equally divided into 10 groups, so that the interval between each group is 100ms, the second timer is a 24-bit timer, a main frequency clock is 100MHz, the counting range is 0-167772160 ns, the resolution is 10ns, the requirement of the sampling precision of a wave recorder is met, the second timer is used for counting from 0 when the code element interval of the IRIG-B is identified, and is cleared when the whole second moment and 10 groups of interval code elements of the IRIG-B are reached, and the synchronization of the second sampling module and the internal time reference of the first FPGA is completed;
the third timer is used for generating switching value sampling pulses with sampling frequency of 10KHz, and adding time information containing seconds and nanoseconds to each sampling value, namely adding an 8-byte internal time reference, wherein the 8-byte internal time reference comprises 4-byte second information and 4-byte nanosecond information, and the nanosecond information is generated by the second timer.
In a specific implementation manner of the embodiment of the present invention, the number of the first sampling module and the second sampling module is one or more, and when the number of the first sampling module and the second sampling module is more than one, the first sampling module and the second sampling module are open modules and/or direct current acquisition modules.
In a specific implementation manner of the embodiment of the present invention, when the second sampling module is an open-in module, after receiving the switching value packet sent by the corresponding second sampling module, the second FPGA determines the switching value shift, and sends the switching value shift to the first FPGA according to the format of the GOOSE packet. The sending to the first FPGA according to the format of the GOOSE packet includes:
when the switching value has no displacement, the GOOSE message is sent according to a heartbeat message of 1 ms;
and after the switching value is shifted, sending a message to the first FPGA according to a GOOSE shift mechanism of 200us, 200us, 400us and 800 us.
In a specific implementation manner of the embodiment of the present invention, the first FPGA and the second FPGA respectively use 10KHz sampling pulses generated by an internal digital phase-locked loop technology to collect ac analog quantities.
Example 2
Based on example 1, the inventive example differs from example 1 in that:
the synchronous sampling device based on the non-real-time bus further comprises a processor, after the first FPGA receives a sampling message sent by the second FPGA, absolute time information synchronous with external GPS equipment is added, and finally, the absolute time information is transmitted to the processor through the PCI-E bus for fault recording and fault analysis. And after receiving the message, the processor synchronizes data according to the time information containing seconds and nanoseconds.
Example 3
Based on example 1, the inventive example differs from example 1 in that:
the main case further comprises a first sampling module connected with the first FPGA, and the first sampling module processes the obtained first internal time reference to obtain time information containing seconds and nanoseconds;
the first sampling module generates sampling pulses, time information containing seconds and nanoseconds is added to each sampling value, then the sampling values are sent to the corresponding first FPGA, meanwhile, the first FPGA generates sampling pulses of alternating current analog quantity, and time information containing seconds and nanoseconds is added to each sampling value.
The first sampling module may be a switch module and/or a dc module.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A synchronous sampling device based on a non-real time bus, comprising:
the main case comprises a first FPGA;
at least one expansion cabinet, wherein the expansion cabinet comprises a second FPGA and a second sampling module which are connected;
the mainframe box and the expansion box are both connected with a CAN bus;
the first FPGA generates a first internal time reference and transmits the first internal time reference to a second FPGA; after receiving the first internal time reference, the second FPGA generates a second internal time reference synchronous with the first internal time reference;
the second sampling module processes the obtained second internal time reference to obtain time information containing seconds and nanoseconds;
the second sampling module generates sampling pulses, adds time information containing seconds and nanoseconds to each sampling value, then sends the sampling values to a corresponding second FPGA, and simultaneously the second FPGA generates sampling pulses of alternating current analog quantity and adds time information containing seconds and nanoseconds to each sampling value;
and the second FPGA sends all sampling values to the first FPGA to complete synchronous sampling.
2. The synchronous sampling device based on the non-real-time bus according to claim 1, wherein: the main case further comprises a first sampling module connected with the first FPGA, and the first sampling module processes the obtained first internal time reference to obtain time information containing seconds and nanoseconds;
the first sampling module generates sampling pulses, time information containing seconds and nanoseconds is added to each sampling value, then the sampling values are sent to the corresponding first FPGA, meanwhile, the first FPGA generates sampling pulses of alternating current analog quantity, and time information containing seconds and nanoseconds is added to each sampling value.
3. The synchronous sampling device based on the non-real-time bus according to claim 2, wherein: and each second sampling module and each first sampling module are transmitted to the corresponding FPGA by adopting a packet splicing mechanism.
4. The synchronous sampling device based on the non-real-time bus according to claim 2, wherein: the first internal time reference is transmitted in IRIG-B format; the first sampling module and the second sampling module comprise a first timer, a second timer and a third timer;
the first timer captures a first internal time reference;
when the second timer decodes the received first internal time reference in the IRIG-B format, the second timer is cleared at the time of the whole second and 10 groups of interval code elements of the IRIG-B to obtain time information containing seconds and nanoseconds;
and the third timer is used for generating switching value sampling pulses with sampling frequency of 10KHz and adding time information containing seconds and nanoseconds to each sampling value.
5. The synchronous sampling device based on the non-real-time bus according to claim 2, wherein: the number of the first sampling module and the second sampling module is one or more, and when the number of the first sampling module and the second sampling module is more, the first sampling module and the second sampling module are open modules and/or direct current acquisition modules.
6. The synchronous sampling device based on the non-real-time bus according to claim 1, wherein: and when the second sampling module is an open-in module, after receiving the switching value message sent by the corresponding second sampling module, the second FPGA judges the switching value deflection and sends the switching value deflection to the first FPGA according to the format of the GOOSE message.
7. The synchronous sampling device based on the non-real-time bus as claimed in claim 6, wherein: the sending to the first FPGA according to the format of the GOOSE packet includes:
when the switching value has no displacement, the GOOSE message is sent according to a heartbeat message of 1 ms;
and after the switching value is shifted, sending a message to the first FPGA according to a GOOSE shift mechanism of 200us, 200us, 400us and 800 us.
8. The synchronous sampling device based on the non-real-time bus according to claim 1, wherein: the synchronous sampling device based on the non-real-time bus further comprises a processor, after the first FPGA receives a sampling message sent by the second FPGA, absolute time information synchronous with external GPS equipment is added, and finally, the absolute time information is transmitted to the processor through the PCI-E bus for fault recording and fault analysis.
9. The synchronous sampling device based on the non-real-time bus according to claim 8, wherein: and after receiving the message, the processor synchronizes data according to the time information containing seconds and nanoseconds.
10. The synchronous sampling device based on the non-real-time bus according to claim 1, wherein: the first FPGA and the second FPGA are used for collecting alternating current analog quantity through 10KHz sampling pulses generated by an internal digital phase-locked loop technology.
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