CN2038669U - Mos element with double-grid - Google Patents
Mos element with double-grid Download PDFInfo
- Publication number
- CN2038669U CN2038669U CN 88220839 CN88220839U CN2038669U CN 2038669 U CN2038669 U CN 2038669U CN 88220839 CN88220839 CN 88220839 CN 88220839 U CN88220839 U CN 88220839U CN 2038669 U CN2038669 U CN 2038669U
- Authority
- CN
- China
- Prior art keywords
- grid
- voltage
- double
- mos device
- mos element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Abstract
The utility model discloses an MOS element with double-grid comprising two oxides grid zones with different thickness and respectively separated metallic layer grids, and a source electrode and a drain electrode can keep single. The thick-grid grid-voltage-channel conductance linear characteristic of the MOS element with double-grid can be adjusted the thin-grid grid-voltage, so the MOS element with double-grid can satisfy the application demand of voltage-conductance linear transform in extensive range.
Description
The utility model relates to the structure of a kind of Metal-oxide-semicondutor (MOS) device.Be particularly related to a kind of MOS device structure with two different-thickness oxide grid regions.
Existing MOS device all has only single even oxide layer grid region and single metal level grid, and in a single day device is made, and the linear characteristic of grid voltage～channel conduction is just fixing, can't regulate.This situation is for some application demand, particularly for realizing that in broad range voltage-electricity leads the application demand of translation function and can not adapt to.
In order to overcome the above-mentioned defective of prior art, the utility model is provided with the oxide grid region of two different-thickness in same MOS device, and on these two grid regions, the metal level grid is set respectively, and the source region of this dual-gate MOS structure both sides and drain region are communicated with, keep single source electrode and drain electrode.The channel conduction that forms between leak in the source is the shunt conductance of semiconductor surface raceway groove below two grid regions thus, and this just makes one of them grid voltage～channel conduction linear characteristic to be regulated by another grid voltage.Fig. 1 is the grid voltage～channel conduction characteristic curve of existing MOS device, and wherein ordinate G is a channel conduction, abscissa V
gBe grid voltage, the V of each MOS device
g～G characteristic curve is unique, can not regulate.Fig. 2 is double grid MOS device grid voltage of the present invention～channel conduction characteristic curve, and wherein ordinate G still is a channel conduction, abscissa V
G1Be the grid voltage of thick grid, V at this moment
G1～G characteristic curve can be by another thin grid grid voltage V
G2Regulate, particularly in application, often need V
G1When～G characteristic curve passed through initial point, this double grid MOS device total energy was by regulating V
G2Make it to realize.
No matter the utility model double grid MOS device is all can realize with the P raceway groove or with the structure of n raceway groove.Fig. 3 illustrates the P channel dual-bar MOS device architecture schematic diagram of an embodiment of the utility model, and wherein 1 is n type Si substrate, and 2 is thin gate oxide, and 3 are thin grid metal level grid, and 4 is thick grating oxide layer, and 5 is thick grid metal level grid, and 6 is P
+The source region, 7 is the metal level source electrode, 8 is P
+The drain region, 9 are the metal level drain electrode.The thick grating oxide layer of this embodiment (4) is controlled in 0.5 to 2.5 micron the scope, thin gate oxide (2) is controlled in 0.05 to 0.15 micron the scope, thick grid grid like this can adapt to the linear transformation of hundreds of volt high voltage～channel conductions, and can added dc low-voltage makes thick grid grid voltage～channel conduction characteristic curve pass through initial point on so thin grid grid by being adjusted in.Such double grid MOS device has four exits, as shown in Figure 4, thick grid grid exit g is arranged
1, thin grid grid exit g
2, source electrode exit S, drain electrode exit D.
In some applications,, often need in relatively broader number range, carry out the linear transformation that voltage～electricity is led, and the utility model double grid MOS device is realized the very easy and effective means of this class function just as in electric power measurement.
Description of drawings
Fig. 1 is the grid voltage～channel conduction characteristic curve of existing MOS device, wherein abscissa V
gBe grid voltage, ordinate G is a channel conduction.
Fig. 2 is thick grid grid voltage～channel conduction characterisitic family, wherein the abscissa V of the utility model double grid MOS device
G1Be thick grid grid voltage, ordinate G is a channel conduction, each root V
G1～G characteristic curve and a thin grid grid voltage value V
G2Corresponding.
Fig. 3 is an embodiment P of a utility model channel dual-bar MOS device architecture schematic diagram, and wherein 1 is n type Si substrate, and 2 is thin gate oxide, and 3 are thin grid metal level grid, and 4 is thick grating oxide layer, and 5 is thick grid metal level grid, and 6 is P
+The source region, 7 is the metal level source electrode, 8 is P
+The drain region, 9 are the metal level drain electrode.
Fig. 4 draws the end schematic diagram outward for the utility model double grid MOS device, wherein g
1Be thick grid grid exit, g
2Be thin grid grid exit, S is the source electrode exit, and D is the drain electrode exit.
Claims (2)
1, a kind of MOS device, it is characterized in that, it has the oxide grid region of two different-thickness, and on these two grid regions the metal level grid is set respectively, and the source electrode of both sides, two grid regions and drain electrode all interconnect and be single source electrode and drain electrode.
2, being characterized as according to the described MOS device of claim 1, in described two different-thickness oxide grid regions, thick grid region oxide thickness is in 0.5 to 2.5 micron scope, and thin grid region oxide thickness is in 0.05 to 0.15 micron scope.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 88220839 CN2038669U (en) | 1988-12-15 | 1988-12-15 | Mos element with double-grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 88220839 CN2038669U (en) | 1988-12-15 | 1988-12-15 | Mos element with double-grid |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2038669U true CN2038669U (en) | 1989-05-31 |
Family
ID=4852986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 88220839 Withdrawn CN2038669U (en) | 1988-12-15 | 1988-12-15 | Mos element with double-grid |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2038669U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361283C (en) * | 2002-10-21 | 2008-01-09 | 三星Sdi株式会社 | Method for manufacturing thin film transistor using double or multiple grid |
| CN101017848B (en) * | 2006-02-06 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | Separated dual bar field effect transistor |
| US8093114B2 (en) | 2006-02-06 | 2012-01-10 | Semiconductor Manufacturing International (Shanghai) Corporation | Method for making split dual gate field effect transistor |
-
1988
- 1988-12-15 CN CN 88220839 patent/CN2038669U/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361283C (en) * | 2002-10-21 | 2008-01-09 | 三星Sdi株式会社 | Method for manufacturing thin film transistor using double or multiple grid |
| CN101017848B (en) * | 2006-02-06 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | Separated dual bar field effect transistor |
| US8093114B2 (en) | 2006-02-06 | 2012-01-10 | Semiconductor Manufacturing International (Shanghai) Corporation | Method for making split dual gate field effect transistor |
| US8614487B2 (en) | 2006-02-06 | 2013-12-24 | Semiconductor Manufacturing International (Shanghai) Corporation | Split dual gate field effect transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA2278308C (en) | Semiconductor diodes having low forward conduction voltage drop and low reverse current leakage | |
| US5132753A (en) | Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs | |
| WO1986007195A1 (en) | Device comprising a hall element incorporated in an integrated circuit | |
| WO2006058216A3 (en) | Junction terminations structures for wide-bandgap power devices | |
| EP0080652A2 (en) | Phototransistor in MOS thin-film technology, method of manufacturing it and method of using it | |
| DE2846096C2 (en) | Solar cell made from semiconductor material | |
| GB1489390A (en) | Method for fabricating mos devices with a plurality of thresholds on a single semi-conductor substrate | |
| DE19918198B4 (en) | Structure of a P-channel trench MOSFET | |
| JPH0210678Y2 (en) | ||
| CN2038669U (en) | Mos element with double-grid | |
| CA2054795A1 (en) | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same | |
| JP2002203910A5 (en) | ||
| EP0704889A3 (en) | Power semiconductors with monolithically integrated test resistor and its fabrication | |
| CA2054644A1 (en) | Superconducting device having an extremely short superconducting channel formed of extremely thin oxide superconductor film and method for manufacturing same | |
| JPS5922360A (en) | Optical input mos type transistor | |
| DE2638045A1 (en) | INTEGRATED POWER SUPPLY CIRCUIT | |
| CA2054477A1 (en) | Superconducting device having an extremely short superconducting channel formed of oxide superconductor material and method for manufacturing the same | |
| Bai et al. | The roles of electric fields and illumination levels in passivating the surface of silicon solar cells | |
| EP0977271A3 (en) | Semiconductor IGBT module | |
| CA2085172A1 (en) | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same | |
| JPS5539636A (en) | Composite semiconductor | |
| JPS57180177A (en) | Semiconductor device | |
| JPS5636162A (en) | Charge transfer element | |
| EP0696066A3 (en) | Semiconductor switching device and power converter | |
| JPS6326554B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |