CN203827366U - Digital signal processing system tester based on IEEE1394 protocol - Google Patents
Digital signal processing system tester based on IEEE1394 protocol Download PDFInfo
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- CN203827366U CN203827366U CN201420182971.8U CN201420182971U CN203827366U CN 203827366 U CN203827366 U CN 203827366U CN 201420182971 U CN201420182971 U CN 201420182971U CN 203827366 U CN203827366 U CN 203827366U
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Abstract
The utility model discloses a digital signal processing system tester based on the IEEE1394 protocol. The tester comprises a data processing module and a power supply module. The data processing module is connected with a protocol communication module, a minimum DSP system module, a reset circuit module, a fan control circuit module, and a host communication module. The protocol communication module is provided with an industrial IEEE1394 interface. The host communication module is provided with USB interfaces. Through a high-speed digital signal processing technology and the IEEE1394 interface, the tester can capture data or events transmitted among devices and networks based on a bus technology, and perform storage, conversion, viewing, and statistics, and other follow-up work, thereby providing great convenience for establishment of the IEEE bus network and data monitoring, greatly reducing difficulty and cost of development of the device and the IEEE bus network, and improving development efficiency.
Description
Technical field
The utility model belongs to digital signal processing technique field, relates to a kind of digital information processing system tester based on IEEE1394 agreement.
Background technology
Initial real-time multimedia technical field, existing bussing technique cannot provide more at a high speed and reliably and ensure, Apple had proposed the bus protocol of IEEE1394 afterwards, be characterized in support point point to-point communication, support broadcast communication, up-to-date standard is supported the traffic rate of ring-type topological sum up to 3.2Gbps, be applied at first DV video camera, portable hard drive, along with scientific and technological progress and social demand, between industrial equipment, field of data transmission and aerospace field also start universal IEEE1394 bus.At present at IEEE1394 bus network development field, the domestic testing equipment that also there is no comprehensively to support IEEE1394-1995, IEEE1394a and IEEE1394b standard, existing testing equipment can only be obtained the data message relevant with this node simultaneously, cannot obtain whole piece bus message, and supporting rate is lower, not supporting bus isolation.
Utility model content
Main purpose of the present utility model is to provide a kind of digital information processing system tester based on IEEE1394 agreement, can support IEEE1394-1995, IEEE1394a and IEEE1394b standard comprehensively, solve existing testing equipment and can only obtain the data message relevant with this node, cannot obtain whole piece bus message and supporting rate is lower, the defect of supporting bus isolation not.
In order to realize goal of the invention, the technical scheme that the utility model adopts is, a kind of digital information processing system tester based on IEEE1394 agreement, include data processing module and power supply module, on data processing module, be connected with respectively protocol communication module, minimum dsp system module, reset circuit module, fan control circuitry module and host computer communication module, in protocol communication module, be provided with industrial IEEE1394 interface, on host computer communication module, be provided with USB interface, power supply module respectively with data processing module, protocol communication module, minimum dsp system module, reset circuit module, control circuit of intelligent fan module and host computer communication module connect to each module for power supply.
Digital signal processing module is provided with clock buffer circuit.
Feature of the present utility model is also, minimum dsp system module includes digital signal processing chip, code memory, DDR2 Installed System Memory and debugging interface.
The beneficial effects of the utility model are:
The utility model can be supported IEEE1394-1995, IEEE1394a and IEEE1394b standard comprehensively, by IEEE1394 protocol interface, can catch data or the event between the device network based on this bussing technique, transmitted, and store, change, check and add up etc. follow-up work, not only speed is high and supporting bus isolation, greatly facilitate setting up and data monitoring of IEEE bus network, the difficulty and the cost that greatly reduce the exploitation of equipment I EEE1394 bus network, more improved development efficiency.
Brief description of the drawings
Fig. 1 is that function of the present utility model realizes block diagram;
Fig. 2 is the reset circuit modular circuit structure chart of schematic diagram of the present utility model;
Fig. 3 is the temperature measuring circuit structure chart of digital signal processing chip of the present utility model and fpga chip;
Fig. 4 is fan control circuitry module drive circuit structure diagram of the present utility model;
Fig. 5 is that the utility model is for the low differential voltage linear voltage stabilizer circuit structure chart to the power supply of protocol communication module physical layer analog circuit;
Fig. 6 is that the utility model is for the low differential voltage linear voltage stabilizer circuit structure chart to the power supply of protocol communication module link layer analog circuit;
Fig. 7 is the DC/DC converter circuit structure chart of the utility model power supply module;
Fig. 8 is the low differential voltage linear voltage stabilizer circuit structure chart of the utility model for the digital signal processing chip to minimum dsp system module and Installed System Memory power supply;
Fig. 9 is that the utility model is for the low differential voltage linear voltage stabilizer circuit structure chart to minimum dsp system module kernel power supply;
In figure, 1. data processing module, 2. protocol communication module, 3. minimum dsp system module, 4. reset circuit module, 5. fan control circuitry module, 6. host computer communication module, 7. power supply module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is elaborated.
The utility model provides a kind of digital information processing system tester based on IEEE1394 agreement, as shown in Figure 1, include data processing module 1 and power supply module 7, on data processing module 1, be connected with respectively protocol communication module 2, minimum dsp system module 3, reset circuit module 4, fan control circuitry module 5 and host computer communication module 6, in protocol communication module 2, be provided with industrial IEEE1394 interface, on host computer communication module 6, be provided with USB interface, power supply module 7 respectively with data processing module 1, protocol communication module 2, minimum dsp system module 3, reset circuit module 4, control circuit of intelligent fan module 5 and host computer communication module 6 connect to each module for power supply.
When concrete enforcement, data processing module 1 adopts ultra-large field programmable logic device, and this chip is being undertaken the data communication function of whole system, and all chip is responsible thus in the data interaction of all component and central processing unit.In data processing module 1, be also provided with clock buffer circuit, ensure that whole system is operated under the beat of same clock source, form synchronous circuit, improve entire system performance, avoid the metastable state phenomenon in asynchronous clock domain.
Protocol communication module 2 link layer chips preferably adopt TSB82AA2, and physical chip adopts TSB81BA3, the highest speed that can support 800Mbps.Pci bus by 32 between digital signal processing chip in link layer chip and minimum dsp system module 3 is connected.
Minimum dsp system module 3 is responsible for data transmit-receive, computing and the protocol analysis of whole system, formed by digital signal processing chip, code memory, DDR2 Installed System Memory and debugging interface, digital signal processing chip is selected TI high speed digital signal processor (TMS320C6455), and kernel running frequency is 1GHz.
The reset of reset circuit module 4 need to have time of delay, as shown in Figure 2, U91 and U90 are for generation of reset signal, C90 is used for adjusting the electrification reset time, resetting time, KEY90 was hand-reset button along with capacitance changes and changes, and pressed this button complete machine and resetted, discharge after this button, reset signal keeps 80 milliseconds.R90, R91 is pull-up resistor, by U90, the first pin of U91 is pulled to high level under normal operation.
Fan control circuitry module 5 is passed through transducer decision circuitry working temperature by fpga chip (field programmable gate array), transducer is welded on the fpga chip back side, make fan work according to the automatic driving power pipe of program of setting, make within the temperature of whole circuit remains on normal range (NR), ensure the reliability of whole circuit working.As shown in Figure 3, U43, U48 are responsible for measuring respectively the temperature of digital signal processing chip and fpga chip, as shown in Figure 4, are responsible for realizing high current drive capability by field effect transistor U413.The temperature data that U43, U48 record passes to digital signal processing chip via FPGA, processor, according to Current Temperatures, calculates the air quantity that need to export when forefan, sends numerical value to FPGA, there is PWM generator in FPGA indoor design, the fan data providing according to digital signal processing chip, produces the pwm signal of corresponding duty ratio, realizes level translation and anti-phase via triode P21, driven by U413 again, export high-power PWM electric current, drive radiator fan, lower the temperature to system.In the time that ambient temperature raises, digital signal processing chip, according to the temperature recording, improves rotation speed of the fan, reaches the object of cooling.In the time that ambient temperature declines, digital signal processing chip can reduce rotation speed of the fan, to reduce the noise producing due to fan blade rotation.D43 and D44 are fan power supply selector switch, in the time using the fan of 5V driving, remove D43, retain D44, in the time using the fan of 12V driving, remove D44, retain D43, such design can realize in a kind of fan source of goods anxiety of model, has spare fans directly to replace.
Host computer communication module 6 adopts USB interface and the external world to realize normal data communication.
Power supply module 7 is by be converted to+5V of outside input power+12V ,+3.3V ,+1.7V, and then be converted to+2.5V of general+5V, be converted to+1.8V of+3.3V, be converted to+1.2V of+1.7V, these voltages can be stable the whole circuit working of giving provide support, and there is powering order.As shown in Figure 5, 5.0V voltage transition is become 1.95V voltage by low pressure difference linear voltage regulator U99, give the analog circuit power supply of protocol communication module 2 physical layers, as shown in Figure 6, 5.0V voltage transition is become the link layer analog circuit power supply of 2.5V voltage to protocol communication module 2 by low pressure difference linear voltage regulator U910, as shown in Figure 7, the voltage transition of the 12.0V that comes from Direct current power source socket is become 5.0V voltage by DC/DC converter U97 and peripheral devices thereof, U96 and peripheral devices thereof become the voltage transition of 12.0V the voltage of 1.7V, the voltage transition of the 12.0V that comes from Direct current power source socket is become 3.3V voltage by U95 and peripheral devices thereof.As shown in Figure 8,3.3V voltage transition is become 1.8V voltage by low pressure difference linear voltage regulator U92 and peripheral devices thereof, gives digital signal processing chip and the power supply of DDR2 Installed System Memory in minimum dsp system module 3.As shown in Figure 9,1.7V voltage transition is become 1.2V voltage by low pressure difference linear voltage regulator U93 and peripheral devices thereof, as the core voltage of DSP and FPGA.U94 and U98, for generation of correct electric sequence, ensure that 3.3V voltage is prior to 1.8V and 1.2V foundation.
The utility model is by high-speed digital signal treatment technology, by IEEE1394 protocol interface, can catch data or the event between the device network based on this bussing technique, transmitted, and store, change, check and add up etc. follow-up work, greatly facilitate setting up and data monitoring of IEEE bus network, greatly reduce difficulty and the cost of equipment I EEE1394 bus network exploitation, more improved development efficiency.
More than show and described general principle of the present utility model, principal character and advantage of the present utility model; above-mentioned execution mode and specification are principle of the present utility model; under the prerequisite that does not depart from the utility model spirit and scope, the utility model also has various changes and modifications, and these changes and improvements all fall in claimed scope of the present utility model.The protection range that the utility model requires is defined by claims and equivalent thereof.
Claims (3)
1. the digital information processing system tester based on IEEE1394 agreement, it is characterized in that, include data processing module (1) and power supply module (7), on described data processing module (1), be connected with respectively protocol communication module (2), minimum dsp system module (3), reset circuit module (4), fan control circuitry module (5) and host computer communication module (6), in described protocol communication module (2), be provided with industrial IEEE1394 interface, host computer communication module is provided with USB interface on (6), described power supply module (7) respectively with data processing module (1), protocol communication module (2), minimum dsp system module (3), reset circuit module (4), control circuit of intelligent fan module (5) and host computer communication module (6) connect to each module for power supply.
2. the digital information processing system tester of IEEE1394 agreement as claimed in claim 1, is characterized in that, described digital signal processing module (1) is provided with clock buffer circuit.
3. the digital information processing system tester of IEEE1394 agreement as claimed in claim 1, is characterized in that, described minimum dsp system module includes digital signal processing chip, code memory, DDR2 Installed System Memory and debugging interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420182971.8U CN203827366U (en) | 2014-04-16 | 2014-04-16 | Digital signal processing system tester based on IEEE1394 protocol |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420182971.8U CN203827366U (en) | 2014-04-16 | 2014-04-16 | Digital signal processing system tester based on IEEE1394 protocol |
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| Publication Number | Publication Date |
|---|---|
| CN203827366U true CN203827366U (en) | 2014-09-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420182971.8U Expired - Fee Related CN203827366U (en) | 2014-04-16 | 2014-04-16 | Digital signal processing system tester based on IEEE1394 protocol |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114837980A (en) * | 2022-05-16 | 2022-08-02 | 深圳宝新创科技股份有限公司 | Fan control circuit, fan and electronic equipment |
-
2014
- 2014-04-16 CN CN201420182971.8U patent/CN203827366U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114837980A (en) * | 2022-05-16 | 2022-08-02 | 深圳宝新创科技股份有限公司 | Fan control circuit, fan and electronic equipment |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140910 Termination date: 20150416 |
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| EXPY | Termination of patent right or utility model |